CDK2308AILP64

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

©2009 CADEKA Microcircuits LLC www.cadeka.com Ampl ify t he H uman Ex per ience CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters F E A T U R E S n 10-bit resolution n 20/40/65/80MSPS maximum sampling rate n Ultra-low power dissipation: 24/43/65/78mW n 61.6dB SNR at 80MSPS and 8MHz FIN n Internal reference circuitry n 1.8V core supply voltage n 1.7V – 3.6V I/O supply voltage n Parallel CMOS output n 64-pin QFN package (TQFP-64 package option also available) n Dual channel n Pin compatible with CDK2307 A P P L I C A T I O N S n Medical Imaging n Portable Test Equipment n Digital Oscilloscopes n IF Communication General Description The CDK2308 is a high performance, low power dual Analog-to-Digital Con- verters (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the com - plete full scale range. Several idle modes with fast startup times exist. Each channel can indepen - dently be powered down and the entire chip can either be put in Standby Mode or Power Down mode. The different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs. Functional Block Diagram

Ordering Information

Part Number Speed Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK2308AILP64 20MSPS QFN-64 Yes Yes -40°C to +85°C Tray CDK2308BILP64 40MSPS QFN-64 Yes Yes -40°C to +85°C Tray CDK2308CILP64 65MSPS QFN-64 Yes Yes -40°C to +85°C Tray CDK2308DILP64 80MSPS QFN-64 Yes Yes -40°C to +85°C Tray CLK_EXT CLKP CLKN CDK2308AITQ64 20MSPS TQFP-64 Yes Yes -40°C to +85°C Tray CDK2308BITQ64 40MSPS TQFP-64 Yes Yes -40°C to +85°C Tray CDK2308CITQ64 65MSPS TQFP-64 Yes Yes -40°C to +85°C Tray CDK2308DITQ64 80MSPS TQFP-64 Yes Yes -40°C to +85°C Tray Moisture sensitivity level for all parts is MSL-2A. Preliminary Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Pin Assignments Pin No. Pin Name Description 1, 18, 23 DVDD Digital and I/O-ring pre driver supply voltage, 1.8V

2 CM_EXT Common Mode voltage output

3, 9, 12 AVDD Analog supply voltage, 1.8V 4, 5, 8 AVSS Analog ground 6, 7 IP0, IN0 Analog input Channel 0 (non-inverting, inverting) 10, 11 IP1, IN1 Analog input Channel 1 (non-inverting, inverting)

13 DVSSCLK Clock circuitry ground

14 DVDDCLK Clock circuitry supply voltage, 1.8V

15 CLKP Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave)

16 CLKN Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground 17, 64 DVSS Digital circuitry ground 19 CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high. 20 DFRMT Data format selection. 0: Offset Binary, 1: Two's Complement 21 PD_N Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up, always apply Power Down mode before using Active mode to reset chip. 24, 41, 58 OVDD I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. 25, 40, 57 OVSS Ground for I/O ring Pin Configuration CDK2308 N/C N/C N/C N/C N/C N/C D0_5 D0_4 D0_3 DVDDCLK CLK_EXT_EN CLKN CLKP DVSSCLK CLK_EXT QFN-64, TQFP-64 QFN-64, TQFP-64 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B 22 OE_N_1 Output Enable Channel 1. Tristate when high

©2009 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Pin No. Pin Name Description

26 NC No Connect

27 NC No Connect

28 NC No Connect

29 D1_0 Output Data Channel 1 (LSB)

30 D1_1 Output Data Channel 1

31 D1_2 Output Data Channel 1

32 D1_3 Output Data Channel 1

33 D1_4 Output Data Channel 1

34 D1_5 Output Data Channel 1

35 D1_6 Output Data Channel 1

36 D1_7 Output Data Channel 1

37 D1_8 Output Data Channel 1

39 ORNG_1 Out of Range flag Channel 1. High when input signal is out of range 42 CLK_EXT Output clock signal for data synchronization. CMOS levels.

43 NC No Connect

44 NC No Connect

45 NC No Connect

46 D0_0 Output Data Channel 0

47 D0_1 Output Data Channel 0

48 D0_2 Output Data Channel 0

49 D0_3 Output Data Channel 0

50 D0_4 Output Data Channel 0

51 D0_5 Output Data Channel 0

52 D0_6 Output Data Channel 0

53 D0_7 Output Data Channel 0

54 D0_8 Output Data Channel 0

56 ORNG_0 Out of Range flag Channel 0. High when input signal is out of range. 59 OE_N_0 Output Enable Channel 0. Tristate when low. 60, 61 CM_EXTBC_1, CM_EXTBC_0 Bias control bits for the buffer driving pin CM_EXT 00: Off 01: 50uA 10: 500uA 11: 1mA 62, 63 SLP_N_1, SLP_N_0 Sleep Mode 00: Sleep Mode 01: Channel 0 active 10: Channel 1 active 11: Both channels active Pin Assignments (Continued)

38 D1_9 Output Data Channel 1 (MSB)

55 D0_9 Output Data Channel 0 (MSB)

Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Parameter Min Max Unit AVDD, AVSS -0.3 +2.3 V DVDD, DVSS -0.3 +2.3 V AVSS, DVSSCK, DVSS, OVSS -0.3 +0.3 V OVDD, OVSS -0.3 +3.9 V CKP, CKN, DVSSCK -0.3 +3.9 V Analog inputs and outpts (IPx, INx, AVSS) -0.3 +2.3 V Digital inputs -0.3 +3.9 V Digital outputs -0.3 +3.9 V Reliability Information Parameter Min Typ Max Unit Storage Temperature Range -60 +150 °C Lead Temperature (Soldering, 10s) J-STD-020 ESD Protection Human Body Model (HBM) 2kV Recommended Operating Conditions Parameter Min Typ Max Unit Operating Temperature Range -40 +85 °C Product TQFP-64, QFN-64 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet

Electrical Characteristics

(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DC Accuracy No Missing Codes Guaranteed Offset Error Midscale offset 1 LSB Gain Error Full scale range deviation from typical -6 6 %FS Gain Matching Gain matching between channels ±0.05 %FS ILE Integral Non-Linearity 12-bit level ±0.2 LSB VCMO Common Mode Voltage Output VAVDD/2 V Analog Input VCMI Input Common Mode Analog input common mode voltage VCM -0.1 VCM +0.2 V VFSR Full Scale Range Input Capacitance Differential input capacitance 2 pF Bandwidth Input bandwidth, full power 500 MHz Power Supply AVDD, DVDD Core Supply Voltage See Pin Configuration and Description OVDD I/O Supply Voltage Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD ≥ VOCVDD) 1.7 2.5 3.6 V DNL Differential Non-Linearity 12-bit level ±0.15 LSB Differential input voltage range 2 Vpp Supply voltage to all 1.8V domain pins. 1.7 1.8 2 V Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR Signal to Noise Ratio FIN = 2MHz 61.7 dBFS FIN = 8MHz 60 61.6 dBFS FIN ≃ FS/2 61.6 dBFS FIN = 20MHz 61.6 dBFS SNDR Signal to Noise and Distortion Ratio FIN = 2MHz 61.7 dBFS FIN = 8MHz 60 61.6 dBFS FIN ≃ FS/2 60.5 dBFS FIN = 20MHz 61.6 dBFS SFDR Spurious Free Dynamic Range FIN = 2MHz 80 dBc FIN = 8MHz 70 81 dBc FIN ≃ FS/2 70 dBc FIN = 20MHz 80 dBc HD2 Second order Harmonic Distortion FIN = 2MHz -90 dBc FIN = 8MHz -80 -90 dBc FIN ≃ FS/2 -90 dBc FIN = 20MHz -90 dBc HD3 Third order Harmonic Distortion FIN = 2MHz -80 dBc FIN = 8MHz -70 -81 dBc FIN ≃ FS/2 -70 dBc FIN = 20MHz -80 dBc ENOB Effective number of Bits FIN = 2MHz 10 bits FIN = 8MHz 9.7 9.9 bits FIN ≃ FS/2 9.8 bits FIN = 20MHz 9.9 bits XTALK Crosstalk Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz -105 dBc Power Supply AIDD Analog Supply Current 8.2 mA DIDD Digital Supply Current Digital core supply 1.7 mA OIDD Output Driver Supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.8 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 2.3 mA Analog Power Dissipation 14.8 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 8.8 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 23.6 mW Power Down Dissipation 9.9 µW Sleep Mode 1 Power Dissipation, Sleep mode one channel 15.2 mW Sleep Mode 2 Power Dissipation, Sleep mode both channels 7.7 mW Clock Inputs Max. Conversion Rate 20 MSPS Min. Conversion Rate 15 MSPS Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR Signal to Noise Ratio FIN = 2MHz 61.6 dBFS FIN = 8MHz 60 61.6 dBFS FIN ≃ FS/2 61.6 dBFS FIN = 30MHz 61.5 dBFS SNDR Signal to Noise and Distortion Ratio FIN = 2MHz 61.6 dBFS FIN = 8MHz 60 61.6 dBFS FIN ≃ FS/2 61.2 dBFS FIN = 30MHz 61.4 dBFS SFDR Spurious Free Dynamic Range FIN = 2MHz 80 dBc FIN = 8MHz 70 81 dBc FIN ≃ FS/2 72 dBc FIN = 30MHz 80 dBc HD2 Second order Harmonic Distortion FIN = 2MHz -90 dBc FIN = 8MHz -80 -90 dBc FIN ≃ FS/2 -85 dBc FIN = 30MHz -85 dBc HD3 Third order Harmonic Distortion FIN = 2MHz -80 dBc FIN = 8MHz -70 -81 dBc FIN ≃ FS/2 -72 dBc FIN = 30MHz -80 dBc ENOB Effective number of Bits FIN = 2MHz 9.9 bits FIN = 8MHz 9.7 9.9 bits FIN ≃ FS/2 9.9 bits FIN = 30MHz 9.9 bits XTALK Crosstalk Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz -100 dBc Power Supply AIDD Analog Supply Current 14.4 mA DIDD Digital Supply Current Digital core supply 3.4 mA OIDD Output Driver Supply 2.5V output driver supply, sine wave input, FIN = 1MHz 5.1 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 4.2 mA Analog Power Dissipation 25.9 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 16.6 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 42.5 mW Power Down Dissipation 9.7 µW Sleep Mode 1 Power Dissipation, Sleep mode one channel 25.7 mW Sleep Mode 2 Power Dissipation, Sleep mode both channels 11.3 mW Clock Inputs Max. Conversion Rate 40 MSPS Min. Conversion Rate 20 MSPS Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD=2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR Signal to Noise Ratio FIN = 8MHz 60 61.6 dBFS FIN = 20MHz 61.6 dBFS FIN ≃ FS/2 61.5 dBFS FIN = 40MHz 61.3 dBFS SNDR Signal to Noise and Distortion Ratio FIN = 8MHz 60 61.6 dBFS FIN = 20MHz 61.6 dBFS FIN ≃ FS/2 60.4 dBFS FIN = 40MHz 61.1 dBFS SFDR Spurious Free Dynamic Range FIN = 8MHz 70 77 dBc FIN = 20MHz 77 dBc FIN ≃ FS/2 70 dBc FIN = 40MHz 75 dBc HD2 Second order Harmonic Distortion FIN = 8MHz -80 -90 dBc FIN = 20MHz -95 dBc FIN ≃ FS/2 -85 dBc FIN = 40MHz -90 dBc HD3 Third order Harmonic Distortion FIN = 8MHz -70 -77 dBc FIN = 20MHz -77 dBc FIN ≃ FS/2 -70 dBc FIN = 40MHz -75 dBc ENOB Effective number of Bits FIN = 8MHz 9.7 9.9 bits FIN = 20MHz 9.9 bits FIN ≃ FS/2 9.7 bits FIN = 40MHz 9.9 bits XTALK Crosstalk Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz -97 dBc Power Supply AIDD Analog Supply Current 22 mA DIDD Digital Supply Current Digital core supply 5.2 mA OIDD Output Driver Supply 2.5V output driver supply, sine wave input, FIN = 1MHz 7.9 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 6.4 mA Analog Power Dissipation 39.6 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 25.4 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 65 mW Power Down Dissipation 9.3 µW Sleep Mode 1 Power Dissipation, Sleep mode one channel 38.2 mW Sleep Mode 2 Power Dissipation, Sleep mode both channels 15.7 mW Clock Inputs Max. Conversion Rate 65 MSPS Min. Conversion Rate 40 MSPS Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 9 Data Sheet (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR Signal to Noise Ratio FIN = 8MHz 60 61.6 dBFS FIN = 20MHz 61.2 dBFS FIN = 30MHz 61.3 dBFS FIN ≃ FS/2 61.3 dBFS SNDR Signal to Noise and Distortion Ratio FIN = 8MHz 60 61.3 dBFS FIN = 20MHz 60.7 dBFS FIN = 30MHz 61 dBFS FIN ≃ FS/2 59 dBFS SFDR Spurious Free Dynamic Range FIN = 8MHz 70 75 dBc FIN = 20MHz 75 dBc FIN = 30MHz 75 dBc FIN ≃ FS/2 65 dBc HD2 Second order Harmonic Distortion FIN = 8MHz -80 -90 dBc FIN = 20MHz -95 dBc FIN = 30MHz -90 dBc FIN ≃ FS/2 -80 dBc HD3 Third order Harmonic Distortion FIN = 8MHz -70 -75 dBc FIN = 20MHz -75 dBc FIN = 30MHz -75 dBc IN ENOB Effective number of Bits FIN = 8MHz 9.7 9.9 bits FIN = 20MHz 9.8 bits FIN = 30MHz 9.8 bits FIN ≃ FS/2 9.5 bits XTALK Crosstalk Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz -95 dBc Power Supply AIDD Analog Supply Current 26.5 mA DIDD Digital Supply Current Digital core supply 6.1 mA OIDD Output Driver Supply 2.5V output driver supply, sine wave input, FIN = 1MHz 9.5 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 7.6 mA Analog Power Dissipation 47.7 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 30 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 77.7 mW Power Down Dissipation 9.1 µW Sleep Mode 1 Power Dissipation, Sleep mode one channel 46.1 mW Sleep Mode 2 Power Dissipation, Sleep mode both channels 18.3 mW Clock Inputs Max. Conversion Rate 80 MSPS Min. Conversion Rate 65 MSPS F ≃ FS/2 -65 dBc Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 10 Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Clock Inputs Duty Cycle 20 80 % high Compliance CMOS, LVDS, LVPECL, Sine Wave Input Range Differential input swing Differential input swing, sine wave clock input Input Common Mode Voltage Keep voltages within ground and voltage of OVDD 0.3 VOVDD -0.3 V Input Capacitance Differential 2 pF Timing TPD Start Up Time Active Mode From Power Down Mode to Active Mode 900 clk cycles TSLP Start Up Time Mode From Sleep Mode to Active Mode 20 clk cycles TOVR Out Of Range Recovery Time 1 clk cycles TAP Aperture Delay 0.8 ns εRMS Aperture Jitter <0.5 ps TLAT Pipeline Delay 12 clk cycles TD Output Delay (see timing diagram) 5pF load on output bits 4 ns TDC Output Delay (see timing diagram) Relative to CLK_EXT 2 ns Logic Inputs VIH High Level Input Voltage VOVDD ≥ 3.0V 2 V VOVDD = 1.7V – 3.0V 0.8 • VOVDD V VIL Low Level Input Voltage VOVDD ≥ 3.0V 0 0.8 V VOVDD = 1.7V – 3.0V 0 0.2 • VOVDD V IIH High Level Input Leakage Current -10 10 µA IIL Low Level Input Leakage Current -10 10 µA CI Input Capacitance 3 pF Logic Outputs VOH High Level Output Voltage VOVDD-0.1 V VOL Low Level Output Voltage 0.1 V CL Max Capacitive Load Post-driver supply voltage equal to pre-driver supply voltage VOVDD = VOCVDD 5 pF Post-driver supply voltage above 2.25V (1) 10 pF Note: (1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum. 400 mVpp

1.6 Vpp

Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 13 Data Sheet The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in equation 1. SNRjitter = 20 • log (2 • π • FIN • εt) where FIN is the signal frequency, and εt is the total rms jitter measured in seconds. The rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable per - formance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock refer- ences (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. The jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter per - formance is obtained with LVDS or LVPECL clock with fast edges. CMOS and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be retimed with a low jitter master clock as the last operation before it is applied to the ADC clock input. Digital Outputs Digital output data are presented on parallel CMOS form. The voltage on the OV DD pin set the levels of the CMOS outputs. The output drivers are dimensioned to drive a wide range of loads for OVDD above 2.25V, but it is rec- ommended to minimize the load to ensure as low tran - sient switching currents and resulting noise as possible. In applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the ADC chip. The timing is described in the Timing Diagram section. Note that the load or equivalent delay on CLK_EXT always should be lower than the load on data outputs to ensure sufficient timing margins. The digital outputs can be set in tristate mode by setting the OE_N signal high. The CDK2308 employs digital offset correction. This means that the output code will be 4096 with the positive and negative inputs shorted together(zero differential). How - ever, small mismatches in parasitics at the input can cause this to alter slightly. The offset correction also results in possible loss of codes at the edges of the full scale range. With “NO” offset correction, the ADC would clip in one end before the other, in practice resulting in code loss at the opposite end. With the output being centered digitally, the output will clip, and the out of range flags will be set, before max code is reached. When out of range flags are set, the code is forced to all ones for over-range and all zeros for under-range. Data Format Selection The output data are presented on offset binary form when DFRMT is low (connect to OV SS). Setting DFRMT high (connect to OV DD) results in 2’s complement output format. Details are shown in Table 1 on page 14. Reference Voltages The reference voltages are internally generated and buff - ered based on a bandgap voltage reference. No external decoupling is necessary, and the reference voltages are not available externally. This simplifies usage of the ADC since two extremely sensitive pins, otherwise needed, are removed from the interface. Operational Modes The operational modes are controlled with the PD_N and SLP_N pins. If PD_N is set low, all other control pins are overridden and the chip is set in Power Down mode. In this mode all circuitry is completely turned off and the internal clock is disabled. Hence, only leakage current contributes to the Power Down Dissipation. The startup time from this mode is longer than for other idle modes as all references need to settle to their final values before normal operation can resume. The SLP_N bus can be used to power down each channel independently, or to set the full chip in Sleep Mode. In this mode internal clocking is disabled, but some low band- width circuitry is kept on to allow for a short startup time. However, Sleep Mode represents a significant reduction in supply current, and it can be used to save power even for short idle periods. The input clock should be kept running in all idle modes. However, even lower power dissipation is possible in Power Down mode if the input clock is stopped. In this case it is important to start the input clock prior to enabling active mode. Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

©2009 CADEKA Microcircuits LLC www.cadeka.com 14 Data Sheet Table 1: Data Format Description for 2Vpp Full Scale Range Differential Input Voltage (IPx - INx) Output data: Dx_9 : Dx_0 (DFRMT = 0, offset binary) Output Data: Dx_9 : Dx_0 (DFRMT = 1, 2’s complement)

1.0 V 11 1111 1111 01 1111 1111

+0.24mV 10 0000 0000 00 0000 0000 -0.24mV 01 1111 1111 11 1111 1111 -1.0V 00 0000 0000 10 0000 0000 Mechanical Dimensions A /uni03B81 1.14 D E E1 1.14 Pin 1 ID Dia. 0.20 Pin 1 ID 0.05 Dia. seating plane 0.45 G L Lbe A CB aaa C A ccc C bbb C A aaa C B bbb C B F

0.10 M C B A

NOTES: 1. All dimensions are in millimeters. 2. Die thickness allowable is 0.305mm maximum (.012 inches maximum) 3. Dimensioning & tolerances conform to ASME y14.5m. -1994. 4. Dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip. 5. The pin #1 identifier must be placed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max 0.08mm. 8. Applied for exposed pad and terminals. Exclude embedding part of exposed pad from measuring. 9. Applied only to terminals. 10. Package corners unless otherwise specipied are r0.175±0.025mm. TOP VIEW BOTTOM VIEW SIDE VIEW Inches Millimeters Symbol Min Typ Max Min Typ Max A 2 – 0.026 0.028 – 0.65 0.7 A 3 0.008 REF 0.2 REF D 0.354 BSC 9.00 BSC D 1 0.354 BSC 8.75 BSC E 0.354 BSC 9.00 BSC E 1 0.344 BSC 8.75 BSC F 0.05 – – 1.3 – – e 0.020 BSC 0.50 BSC Tolerance of Form and Position aaa 0.10 0.004 bbb 0.10 0.004 ccc 0.05 0.002 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B

For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) Data Sheet Ampl ify t he H uman Ex per ience Mechanical Dimensions (Continued) Symbol Min Typ Max Min Typ Max A 1 0.002 – 0.006 0.05 – 0.15 D 0.472 BSC 12.00 BSC D 1 0.393 BSC 10.00 BSC E 0.472 BSC 12.00 BSC E 1 0.393 BSC 10.00 BSC R 2 0.003 – 0.008 0.08 – 0.20 /uni03B82 11° 12° 13° 11° 12° 13° /uni03B83 11° 12° 13° 11° 12° 13° c 0.004 – 0.008 0.09 0.20 L 1 0.039 REF 1.00 REF e 0.020 BSC 0.520 BSC D 2 0.295 7.50 E 2 0.295 7.50 aaa 0.008 0.20 bbb 0.008 0.20 ccc 0.003 0.08 ddd 0.003 0.08 Inches Millimeters NOTES: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maxmum plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. 3. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. TOP VIEW DETAIL SIDE VIEW SIDE VIEW Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308Rev 2B