CDK1307BILP40

CDK1307 CADEKA | Alldatasheet

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Technical content

©2008 CADEKA Microcircuits LLC www.cadeka.com Ampl ify t he H uman Ex per ience CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters (ADCs) F E A T U R E S n 13-bit resolution n 20/40/65/80MSPS max sampling rate n Ultra-Low Power Dissipation: 19/33/50/60mW n 72.4dB SNR at 8MHz FIN n Internal reference circuitry n 1.8V core supply voltage n 1.7 – 3.6V I/O supply voltage n Parallel CMOS output n 40-pin QFN package n Pin compatible with CDK1308 A P P L I C A T I O N S n Medical Imaging n Portable Test Equipment n Digital Oscilloscopes n IF Communication General Description The CDK1307 is a high performance ultra low power Analog-to-Digital Converter (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary struc- ture. Digital error correction is employed to ensure no missing codes in the complete full scale range. Two idle modes with fast startup times exist. The entire chip can either be put in Standby Mode or Power Down mode. The two modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK1307 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave, and CMOS clock inputs. Functional Block Diagram

Ordering Information

Part Number Speed Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK1307AILP40 20MSPS QFN-40 Yes Yes -40°C to +85°C Tray CDK1307BILP40 40MSPS QFN-40 Yes Yes -40°C to +85°C Tray CDK1307CILP40 65MSPS QFN-40 Yes Yes -40°C to +85°C Tray CDK1307DILP40 80MSPS QFN-40 Yes Yes -40°C to +85°C Tray Moisture sensitivity level for all parts is MSL-3.

©2008 CADEKA Microcircuits LLC www.cadeka.com 2 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 Pin Assignments Pin No. Pin Name Description 0 VSS Ground connection for all power domains. Exposed pad 1, 11, 16 DVDD Digital and I/O-ring pre driver supply voltage, 1.8V

2 CM_EXT Common Mode voltage output

3, 4, 7 AVDD Analog supply voltage, 1.8V 5, 6 IP, IN Analog input (non-inverting, inverting) 8 DVDDCLK Clock circuitry supply voltage, 1.8V

9 CLKP Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave)

10 CLKN Clock input, inverting. For CMOS input on CLKP, Connect CLKN to ground 12 CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high. 13 DFRMT Data format selection. 0: Offset Binary, 1: Two's Complement 14 PD_N Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up always apply Power Down mode before using Active Mode to reset chip. 15 OE_N Output Enable. Tristate when high 17, 18, 25, 26, 36, 37 OVDD I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V

19 D_0 Output Data (LSB, 13-bit output or 1Vpp full scale range)

20 D_1 Output Data LSB, 12-bit output 2Vpp full scale range)

21 D_2 Output Data

22 D_3 Output Data

2CM_EXT 4AVDD 3AVDD 1DVSS 6IN 8DVDDCLK 7AVDD 10CLKN 9CLKP 5IP

29 D_6

27 CLK_EXT

28 D_5

30 D_7

25 OVDD

23 D_4

24 ORNG

21 D_2

22 D_3

26 OVDD

12CLK_EXT_EN 14PD_N 13DFRMT 11DVDD 16DVDD 18OVDD 17OVDD 20D_1 19D_0 15OE_N

39 CM_EXTBC_0

37 OVDD

38 CM_EXTBC_1

40 SLP_N

35 D_12

33 D_10

34 D_11

31 D_8

32 D_9

36 OVDD

©2008 CADEKA Microcircuits LLC www.cadeka.com 3 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 Pin No. Pin Name Description

23 D_4 Output Data

24 ORNG Out of Range flag. High when input signal is out of range 27 CLK_EXT Output clock signal for data synchronization. CMOS levels

28 D_5 Output Data

29 D_6 Output Data

30 D_7 Output Data

31 D_8 Output Data

32 D_9 Output Data

33 D_10 Output Data

34 D_11 Output Data (MSB for 1Vpp full scale range, see Reference Voltages section)

35 D_12 Output Data (MSB for 2Vpp full scale range)

38, 39 CM_EXTBC_1, CM_EXTBC_0 Bias control bits for the buffer driving pin CM_EXT 00: OFF 10: 50μA 10: 500μA 11: 1mA

40 SLP_N Sleep Mode when low

Pin Assignments (Continued)

©2008 CADEKA Microcircuits LLC www.cadeka.com 4 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Parameter Min Max Unit AVDD -0.3 +2.3 V DVDD -0.3 +2.3 V AVSS, DVSSCK, DVSS, OVSS -0.3 +0.3 V OVDD, OVSS -0.3 +3.9 V CLKP, CLKN -0.3 +3.9 V Analog inputs and outpts (IPx, INx) -0.3 +2.3 V Digital inputs -0.3 +3.9 V Digital outputs -0.3 +3.9 V Reliability Information Parameter Min Typ Max Unit Junction Temperature TBD °C Storage Temperature Range -60 +150 °C Lead Temperature (Soldering, 10s) TBD °C ESD Protection Product QFN-40 Human Body Model (HBM) 2kV Charged Device Model (CDM) TBD Recommended Operating Conditions Parameter Min Typ Max Unit Operating Temperature Range -40 +85 °C

©2008 CADEKA Microcircuits LLC www.cadeka.com 5 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1

Electrical Characteristics

(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DC Accuracy No Missing Codes Guaranteed Offset Error Midscale offset TBD mV Gain Error Full scale range deviation from typical -6 6 %FS DNL Differential Non-Linearity 12-bit level -0.5 0.5 LSB INL Integral Non-Linearity 12-bit level -1 1 LSB VCMO Common Mode Voltage Output VAVDD/2 V Analog Input VCMI Input Common Mode Analog input common mode voltage VCM -0.1 VCM +0.1 V VFSR Full Scale Range, Normal Differential input voltage range, 2.0 Vpp Full Scale Range, Option Differential input voltage range, 1V (see section Reference Voltages)

1.0 Vpp

Input Capacitance Differential input capacitance 1.8 pF Bandwidth Input bandwidth, full power 500 MHz Power Supply AVDD, DVDD Core Supply Voltage Supply voltage to all 1.8V domain pins. See Pin Configuration and Description 1.7 1.8 2.0 V OVDD I/O Supply Voltage Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD ≥ VOCVDD) 1.7 2.5 3.6 V

©2008 CADEKA Microcircuits LLC www.cadeka.com 6 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR Signal to Noise Ratio FIN = 2MHz 72.7 dBFS FIN = 8MHz 72.6 dBFS FIN ≃ FS/2 72.3 dBFS FIN = 20MHz 72.0 dBFS SINAD Signal to Noise and Distortion Ratio FIN = 2MHz 72.4 dBFS FIN = 8MHz 72.0 dBFS FIN ≃ FS/2 71.3 dBFS FIN = 20MHz 71.4 dBFS SFDR Spurious Free Dynamic Range FIN = 2MHz 84.9 dBc FIN = 8MHz 88.7 dBc FIN ≃ FS/2 80.1 dBc FIN = 20MHz 85.5 dBc HD2 Second order Harmonic Distortion FIN = 2MHz -97.6 dBc FIN = 8MHz -100 dBc FIN ≃ FS/2 -101 dBc FIN = 20MHz -95.7 dBc HD3 Third order Harmonic Distortion FIN = 2MHz -94.6 dBc FIN = 8MHz -88.7 dBc FIN ≃ FS/2 -80.1 dBc FIN = 20MHz -96.8 dBc ENOB Effective number of Bits FIN = 2MHz 11.7 bits FIN = 8MHz 11.7 bits FIN ≃ FS/2 11.6 bits FIN = 20MHz 11.6 bits Power Supply AIDD Analog Supply Current 7.8 mA DIDD Digital Supply Current Digital core supply 1.0 mA OIDD Output Driver Supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 1.7 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 1.3 mA Analog Power Dissipation 14.0 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 5.1 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 19.1 mW Power Down Dissipation 9.9 μW Sleep Mode Power Dissipation, Sleep mode 9.2 mW Clock Inputs Max. Conversion Rate 20 MSPS Min. Conversion Rate 15 MSPS

©2008 CADEKA Microcircuits LLC www.cadeka.com 7 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR Signal to Noise Ratio FIN = 2MHz 73.2 dBFS FIN = 8MHz 73.0 dBFS FIN ≃ FS/2 72.5 dBFS FIN = 30MHz 71.2 dBFS SINAD Signal to Noise and Distortion Ratio FIN = 2MHz 72.1 dBFS FIN = 8MHz 72.0 dBFS FIN ≃ FS/2 71.7 dBFS FIN = 30MHz 70.6 dBFS SFDR Spurious Free Dynamic Range FIN = 2MHz 81.3 dBc FIN = 8MHz 82.0 dBc FIN ≃ FS/2 81.6 dBc FIN = 30MHz 82.1 dBc HD2 Second order Harmonic Distortion FIN = 2MHz -97.5 dBc FIN = 8MHz -103 dBc FIN ≃ FS/2 -95.3 dBc FIN = 30MHz -85.1 dBc HD3 Third order Harmonic Distortion FIN = 2MHz -82.5 dBc FIN = 8MHz -85.3 dBc FIN ≃ FS/2 -81.6 dBc FIN = 30MHz -95.8 dBc ENOB Effective number of Bits FIN = 2MHz 11.7 bits FIN = 8MHz 11.7 bits FIN ≃ FS/2 11.6 bits FIN = 30MHz 11.4 bits Power Supply AIDD Analog Supply Current 13.4 mA DIDD Digital Supply Current Digital core supply 1.7 mA OIDD Output Driver Supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 3.3 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 2.4 mA Analog Power Dissipation 24.1 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 9.1 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 33.2 mW Power Down Dissipation 9.7 μW Sleep Mode Power Dissipation, Sleep mode 14.2 mW Clock Inputs Max. Conversion Rate 40 MSPS Min. Conversion Rate 20 MSPS

©2008 CADEKA Microcircuits LLC www.cadeka.com 8 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR Signal to Noise Ratio FIN = 8MHz 73.1 dBFS FIN = 20MHz 72.2 dBFS FIN ≃ FS/2 71.6 dBFS FIN = 40MHz 70.4 dBFS SINAD Signal to Noise and Distortion Ratio FIN = 8MHz 72.0 dBFS FIN = 20MHz 71.8 dBFS FIN ≃ FS/2 70.7 dBFS FIN = 40MHz 69.6 dBFS SFDR Spurious Free Dynamic Range FIN = 8MHz 82.1 dBc FIN = 20MHz 84.8 dBc FIN ≃ FS/2 78.7 dBc FIN = 40MHz 79.6 dBc HD2 Second order Harmonic Distortion FIN = 8MHz -97.3 dBc FIN = 20MHz -101 dBc FIN ≃ FS/2 -90.4 dBc FIN = 40MHz -91.1 dBc HD3 Third order Harmonic Distortion FIN = 8MHz -84.2 dBc FIN = 20MHz -90.2 dBc FIN ≃ FS/2 -78.7 dBc FIN = 40MHz -89.7 dBc ENOB Effective number of Bits FIN = 8MHz 11.7 bits FIN = 20MHz 11.6 bits FIN ≃ FS/2 11.5 bits FIN = 40MHz 11.3 bits Power Supply AIDD Analog Supply Current 20.4 mA DIDD Digital Supply Current Digital core supply 2.3 mA OIDD Output Driver Supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 5.1 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 3.5 mA Analog Power Dissipation 36.7 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 12.9 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 49.6 mW Power Down Dissipation 9.3 μW Sleep Mode Power Dissipation, Sleep mode 20.4 mW Clock Inputs Max. Conversion Rate 65 MSPS Min. Conversion Rate 40 MSPS

©2008 CADEKA Microcircuits LLC www.cadeka.com 9 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR Signal to Noise Ratio FIN = 8MHz 72.4 dBFS FIN = 20MHz 71.8 dBFS FIN = 30MHz 71.0 dBFS FIN ≃ FS/2 70.5 dBFS SINAD Signal to Noise and Distortion Ratio FIN = 8MHz 70.7 dBFS FIN = 20MHz 70.8 dBFS FIN = 30MHz 70.2 dBFS FIN ≃ FS/2 69.6 dBFS SFDR Spurious Free Dynamic Range FIN = 8MHz 78.2 dBc FIN = 20MHz 79.4 dBc FIN = 30MHz 79.1 dBc FIN ≃ FS/2 79.7 dBc HD2 Second order Harmonic Distortion FIN = 8MHz -97.2 dBc FIN = 20MHz -94.2 dBc FIN = 30MHz -91.6 dBc FIN ≃ FS/2 -81.8 dBc HD3 Third order Harmonic Distortion FIN = 8MHz -78.2 dBc FIN = 20MHz -79.4 dBc FIN = 30MHz -83.0 dBc FIN ≃ FS/2 -79.7 dBc ENOB Effective number of Bits FIN = 8MHz 11.5 bits FIN = 20MHz 11.5 bits FIN = 30MHz 11.4 bits FIN ≃ FS/2 11.3 bits Power Supply AIDD Analog Supply Current 24.5 mA DIDD Digital Supply Current Digital core supply 2.9 mA OIDD Output Driver Supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 6.1 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 4.1 mA Analog Power Dissipation 44.1 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 15.5 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 59.6 mW Power Down Dissipation 9.1 μW Sleep Mode Power Dissipation, Sleep mode 24.1 mW Clock Inputs Max. Conversion Rate 80 MSPS Min. Conversion Rate 65 MSPS

©2008 CADEKA Microcircuits LLC www.cadeka.com 10 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Clock Inputs Duty Cycle 20 80 % high Compliance CMOS, LVDS, LVPECL, Sine Wave Input Range Differential input swing -200 200 mVpp Differential input swing, sine wave clock input -800 800 mVpp Input Common Mode Voltage Keep voltages within ground and voltage of OVDD 0.3 VOVDD -0.3 V Input Capacitance Differential 1.7 pF Timing TPD Start Up Time from Power Down From Power Down Mode to Active Mode References has reached 99% of final value 900 clk cycles TSLP Start Up Time from Sleep From Sleep Mode to Active Mode 0.5 μs TOVR Out Of Range Recovery Time 1 clk cycles TAP Aperture Delay 0.8 ns εRMS Aperture Jitter <0.5 ps TLAT Pipeline Delay 12 clk cycles TD Output Delay 5pF load on output bits (see timing diagram) 4 ns 10pF load on output bits (see timing diagram) TBD ns TDC Output Delay Relative to CLK_EXT See timing diagram 2 ns Logic Inputs VIH High Level Input Voltage VOVDD ≥ 3.0V 2 V VOVDD = 1.7V – 3.0V 0.8 • VOVDD V VIL Low Level Input Voltage VOVDD ≥ 3.0V 0 0.8 V VOVDD = 1.7V – 3.0V 0 0.2 • VOVDD V IIH High Level Input Leakage Current -10 10 μA IIL Low Level Input Leakage Current -10 10 μA CI Input Capacitance 3 pF Logic Outputs VOH High Level Output Voltage -0.1 +VOVDD V VOL Low Level Output Voltage 0.1 V CL Max Capacitive Load Post-driver supply voltage equal to pre-driver supply voltage VOVDD = VOCVDD 5 pF Post-driver supply voltage above 2.25V (1) 10 pF Note: (1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum.

©2008 CADEKA Microcircuits LLC www.cadeka.com 13 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in the equation below: SNRjitter = 20 • log (2 • π • FIN • εt) where FIN is the signal frequency, and εt is the total rms jitter measured in seconds. The rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable per - formance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost im - portance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. The jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter per - formance is obtained with LVDS or LVPECL clock with fast edges. CMOS and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be re- timed with a low jitter master clock as the last operation before it is applied to the ADC clock input. Digital Outputs Digital output data are presented on parallel CMOS form. The voltage on the OVDD pin set the levels of the CMOS outputs. The output drivers are dimensioned to drive a wide range of loads for OVDD above 2.25V, but it is rec - ommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. In ap - plications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the ADC chip. The timing is described in the Timing Diagram section. Note that the load or equivalent delay on CK_EXT always should be lower than the load on data outputs to ensure sufficient timing margins. The digital outputs can be set in tristate mode by setting the OE_N signal high. The CDK1307 employs digital offset correction. This means that the output code will be 4096 with shorted inputs. However, small mismatches in parasitics at the input can cause this to alter slightly. The offset correction also re - sults in possible loss of codes at the edges of the full scale range. With no offset correction, the ADC would clip in one end before the other, in practice resulting in code loss at the opposite end. With the output being centered digitally, the output will clip, and the out of range flags will be set, before max code is reached. When out of range flags are set, the code is forced to all ones for over-range and all zeros for under-range. Data Format Selection The output data are presented on offset binary form when DFRMT is low (connect to OV SS). Setting DFRMT high (connect to OV DD) results in 2’s complement output format. Details are shown in Table 1 on page 14. The data outputs can be used in three different configurations. Normal mode: All 13-bits are used. MSB is D_12 and LSB is D_0. This mode gives optimum performance due to reduced quanti- zation noise. 12-bit mode: The LSB is left unconnected such that only 12 bits are used. MSB is D_12 and LSB is D_1. This mode gives slightly reduced performance, due to increased quantization noise. Reduced full scale range mode: The full scale range is reduced from 2Vpp to 1Vpp which is equivalent to 6dB gain in the ADC frontend. MSB is D_11 and LSB is D_0. Note that the codes will wrap around when exceeding the full scale range, and that out of range bits should be used to clamp output data. See section Reference Voltages for details. This mode gives slightly reduced performance.

©2008 CADEKA Microcircuits LLC www.cadeka.com 14 ADVANCE Data Sheet CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 Table 2: Data Format Description for 1Vpp Full Scale Range Differential Input Voltage (IP - IN) Output data: D_11: D_0 (DFRMT = 0) (2’s Complement) Out of Range (Use Logical AND Function for &) Output Data: D_11: D_0 (DFRMT = 1) (2’s Complement) Out of Range (Use Logical AND Function for &) > 0.5V 0111 1111 1111 D_12 = 1 & D_11 = 1 0111 1111 1111 D_12 = 0 & D_11 = 1 0.5V 0111 1111 1111 0111 1111 1111 +0.24mV 0000 0000 0000 0000 0000 0000 -0.24mV 1111 1111 1111 1111 1111 1111 -0.5V 1000 0000 0000 1000 0000 0000 < -0.5V 1000 0000 0000 D_12 = 0 & D_11 = 0 1000 0000 0000 D_12 = 1 & D_11 = 0 Reference Voltages The reference voltages are internally generated and buff- ered based on a bandgap voltage reference. No external decoupling is necessary, and the reference voltages are not available externally. This simplifies usage of the ADC since two extremely sensitive pins, otherwise needed, are removed from the interface. If a lower full scale range is required the 13-bit output word provides sufficient resolution to perform digital scaling with an equivalent impact on noise compared to adjusting the reference voltages. A simple way to obtain 1.0V pp input range with a 12-bit output word is shown in the Table 2 below. Note that only 2‘s complement output data are available in this mode and that out of range conditions must be determined based on a two bit output. The output code will wrap around when the code goes outside the full scale range. The out of range bits should be used to clamp the output data for overrange conditions. Operational Modes The operational modes are controlled with the PD_N and SLP_N pins. If PD_N is set low, all other control pins are overridden and the chip is set in Power Down mode. In this mode all circuitry is completely turned off and the internal clock is disabled. Hence, only leakage current contributes to the Power Down Dissipation. The startup time from this mode is longer than for other idle modes as all references need to settle to their final values before normal operation can resume. The SLP_N bus can be used to power down each channel independently, or to set the full chip in Sleep Mode. In this mode internal clocking is disabled, but some low band - width circuitry is kept on to allow for a short startup time. However, Sleep Mode represents a significant reduction in supply current, and it can be used to save power even for short idle periods. The input clock could be kept running in all idle modes. However, even lower power dissipation is possible in Power Down mode if the input clock is stopped. In this case it is important to start the input clock prior to en - abling active mode. Table 1: Data Format Description for 2Vpp Full Scale Range Differential Input Voltage (IP - IN) Output data: D_12 : D_0 (DFRMT = 0, offset binary) Output Data: D_12 : D_0 (DFRMT = 1, 2’s complement)

1.0 V 1 1111 1111 1111 0 1111 1111 1111

+0.24mV 1 0000 0000 0000 0 0000 0000 0000 -0.24mV 0 1111 1111 1111 1 1111 1111 1111 -1.0V 0 0000 0000 0000 1 0000 0000 0000

For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) ADVANCE Data Sheet designed by CDK1307 Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs Rev 0.1 Ampl ify t he H uman Ex per ience Mechanical Dimensions NOTE: Package dimensions in millimeter unless otherwise noted. Symbol Min Typ Max Min Typ Max A 2 – 0.023 0.028 – 0.65 0.7 A 3 0.008 REF 0.2 REF D 0.236 BSC 6.00 BSC D 1 0.226 BSC 5.75 BSC e 0.020 BSC 0.50 BSC R 0.004 0.008 – 0.1 0.2 – Inches Millimeters Pin 1 ID - Dia. 0.5 (Top Side) Pin 1 ID - Dia. R Pin 0 Exposed Pad F G A /uni03B81 L be 1.14 0.45 D D D2 D1