CDK1306 CADEKA | Alldatasheet

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Technical content

©2008 CADEKA Microcircuits LLC www.cadeka.com CDK1306 10-bit, 40 MSPS 160mW A/D Converter REV 1A CDK1306 10-bit, 40 MSPS 160mW A/D Converter Ampl ify th e Human Exp eri ence

features

n Tri-state output buffers n High ESD protection: 3,500V minimum n Selectable +3V or +5V logic I/O

applications

n All high-speed applications where low power dissipation is required n Video imaging n Medical imaging n Radar receivers n IR imaging n Digital communications General Description The CDK1306 is a 10-bit, low power analog-to-digital converter capable of minimum word rates of 40 MSPS. The on-chip track-and-hold function assures very good dynamic performance without the need for external components. The input drive requirements are minimized due to the CDK1306 low input capacitance of only 5pF. Power dissipation is extremely low at only 160mW typical at 40 MSPS with a power supply of +5.0V. The digital outputs are +3V or +5V, and are user selectable. The CDK1306 is pin-compatible with an entire family of 10-bit, CMOS converters (CDK1304/05/06), which simplifies upgrades. The CDK1306 has incorporated proprietary circuit design* and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS- compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The CDK1306 is available in 28-lead SOIC and 32-lead small (7mm square) TQFP packages over the commercial temperature range. Block Diagram

Ordering Information

Part Number Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK1306CSO28 SOIC-28 Yes Yes 0°C to +70°C Rail CDK1306CSO28_Q SOIC-28 No No 0°C to +70°C Rail CDK1306CTQ32 TQFP-32 Yes Yes 0°C to +70°C Rail CDK1306CTQ32_Q TQFP-32 No No 0°C to +70°C Rail Moisture sensitivity level for SOIC-28 is MSL-1 and TQFP is MSL-3.

©2008 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet CDK1306 10-bit, 40 MSPS 160mW A/D Converter REV 1A Pin Configuration SOIC-28 TQFP-32 Pin Assignments SOIC-28 TQFP-32 Pin Name Description 1,8 3,4,28,29 AGND Analog Ground 2 30 VRHF Reference High Force 3 31 VRHS Reference High Sense 5 32 VRLS Reference Low Sense 6 1 VRLF Reference Low Force 9 5 VCAL Calibration Reference 7 2 VIN Analog Input 10 6,7 AVDD Analog VDD 11 8,9 DVDD Digital VDD 12 10,11 DGND Digital Ground 13 12 CLK Input Clock ƒCLK = FS (TTL) 15 14 EN Output Enable 16-20, 23-27 15-19, 22-26 D0-D9 Tri-State Data Output, (D0 = LSB) 28 27 D10 Tri-State Output Overrange 14 13 DAV Data Valid Output 22 21 OVDD Digital Output Supply 21 20 OGND Digital Output Ground 4 – N/C No Connect CDK1306 CDK1306

©2008 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet CDK1306 10-bit, 40 MSPS 160mW A/D Converter REV 1A Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Parameter Min Max Unit Supply Voltages AVDD +6 V DVDD +6 V Input Voltages Analog input -0.5 AVDD +0.5 V V Ref 0 AVDD V CLK input VDD V AVDD – DVDD -100 100 mV AGND – DGND -100 100 mV Digital Outputs 10 mA Reliability Information Parameter Min Typ Max Unit Storage Temperature Range -65 +150 °C Recommended Operating Conditions Parameter Min Typ Max Unit Operating Temperature Range 0 +70 °C Junction Temperature Range +175 °C Lead Temperature (soldering 10 seconds) +300 °C

©2008 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet CDK1306 10-bit, 40 MSPS 160mW A/D Converter REV 1A

Electrical Characteristics

(TA = TMin to TMax, AVDD = DVDD = OVDD = +5V, VIN = 0 to 4V, ƒclk = 40 MSPS, VRHS = 4V, VRLS = 0V; unless otherwise noted) symbol parameter conditions Min typ Max units Resolution 10 bits DC Performance DLE Differential Linearity Error(1) -0.5 +0.5 LSB ILE Integral Linearity Error(1) -1.0 +1.0 LSB No Missing Codes Guaranteed Analog Input Input Voltage Range(1) VRLS VRHS V Input Resistance(2) 50 kΩ Input Capacitance 5 pF Input Bandwidth Small Signal 250 MHz Gain Error ±2.0 LSB Offset Error ±2.0 LSB Reference Input Resistance(1) 200 400 600 Ω Bandwidth Small Signal 150 MHz Voltage Range V RLS (2) 0 2.0 V V RHS (2) 3.0 AVDD V V RHS – VRLS 4.0 V Δ (VRHF – VRHS) 90 mV Δ (VRLS – VRLF) 75 mV Reference Settling Time VRHS 15 CLK Cycle VRLS 20 CLK Cycle Conversion Characteristics Maximum Conversion Rate(1) 40 MHz Minimum Conversion Rate(2) 2 MHz Pipeline Delay (Latency)(2) 12 CLK Cycle Aperture Delay Time 4.0 ns Aperture Jitter Time 15 pspp Dynamic Performance ENOB Effective Number of Bits ƒIN = 3.58MHz 9.2 Bits ƒIN = 10.3MHz 8.8 Bits SNR Signal-to-Noise Ratio w/o Harmonics ƒIN = 3.58MHz(1) 56 58 dB ƒIN = 10.3MHz(1) 55 57 dB THD Total Harmonic Distortion ƒIN = 3.58MHz(1), 9 distortion bins from 1024 pt FFT 61 63 dB ƒIN = 10.3MHz(1), 9 distortion bins from 1024 pt FFT 56 58 dB SINAD Signal-to-Noise and Distortion ƒIN = 3.58MHz(1) 54 57 dB ƒIN = 10.3MHz(1) 53 55 dB SFDR Spurious Free Dynamic Range ƒIN = 1MHz 64 dB Differential Phase ±0.3 deg Differential Gain ±0.3 % notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data.

©2008 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet CDK1306 10-bit, 40 MSPS 160mW A/D Converter REV 1A (TA = TMin to TMax, AVDD = DVDD = OVDD = +5V, VIN = 0 to 4V, ƒclk = 40 MSPS, VRHS = 4V, VRLS = 0V; unless otherwise noted) symbol parameter conditions Min typ Max units Digital Inputs Logic “1“ Voltage(1) 2.0 V Logic “0“ Voltage(1) 0.8 V Maximum Input Current Low(1) -10 +10 μA Maximum Input Current High(1) -10 +10 μA Input Capacitance +5 pF Digital Outputs Logic “1“ Voltage(1) IOH = 0.5mA 3.5 V Logic “0“ Voltage(1) IOL = 1.6mA 0.4 V TR Rise Time 15pF load 10 ns TF Fall Time 15pF load 10 ns Output Enable to Data Output Delay 20pF load, TA = 25°C 10 ns 50pF load over temp 22 ns Power Supply Requirements OVDD Digital Voltage Supply(2) 3.0 5.0 V DVDD 4.75 5.0 5.25 V AVDD 4.75 5.0 5.25 V AIDD Digital Voltage Current(1) 14 22 mA DIDD 18 23 mA Power Dissipation(1) 160 225 mW notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data.

The variations in aperture delay for successive samples. Small signal (50mV) bandwidth (3dB) of analog input stage. Error in the width of each code from its theoretical value. each particular code to the true straight line. to 50% of the full-scale value. noise power. Harmonics are excluded. power of the measured sinusoidal signal. single largest harmonic or spurious signal. Figure 1. Timing Diagram 1

sible latch-up condition on powerup. that provides common reference levels for each ADC section. Table 2. Clock Cycles

1 Reference zero sampling

2 Auto-zero comparison

3 Auto-calibrate comparison

4 Input sample

16 Data transfer

to the corresponding digital output is 12 clock cycles. response to a reference zero. samples the input during a clock cycle. from the input by transmission gates. measured between the ladder sense lines, VRHS and VRLS. voltages across part-to-part and temperature variations. gain errors of less than ±2 LSB can be obtained. lent to the voltage drop from VRLF to VRLS.

ditions without degrading analog transition times. Figure 7. On-Chip Protection Circuit delay VDD power to the device. Table 3. Output Data Information logic 1 as long as D10 remains at logic 1.

For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. caDeKa Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) Data Sheet CDK1306 10-bit, 40 MSPS 160mW A/D Converter REV 1A Ampl ify th e Human Exp eri ence Mechanical Dimensions A B C D E F J K L G I Inches Millimeters Symbol Min Max Min Max A 0.346 0.362 8.80 9.20 B 0.272 0.280 6.90 7.10 C 0.346 0.362 8.80 9.20 D 0.272 0.280 6.90 7.10 E 0.031 Typ 0.80 BSC F 0.012 0.016 0.30 0.40 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.037 0.041 0.95 1.05 J 0.007 0.17 K 7°0° 0° 7° L 0.020 0.030 0.50 0.75 H I Inches Millimeters Symbol Min Max Min Max A 0.699 0.709 17.75 18.01 B 0.005 0.011 0.13 0.28 C D E 0.050 Typ 1.27 BSC 0.018 Typ 0.46 BSC F 0.090 G 0.031 0.039 0.79 0.99 0.0077 0.0083 0.20 0.21 0.096 2.29 2.44 H 0.396 0.416 10.06 10.57 I 0.286 0.292 7.26 7.42 F A B C D E G HI H