CDK1302 CADEKA | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 9
Technical content
©2008 CADEKA Microcircuits LLC www.cadeka.com CDK1302 8-bit, 750 MSPS, Flash A/D Converter REV 1A CDK1302 8-bit, 750 MSPS, Flash A/D Converter Ampl ify th e Human Exp eri ence
Ordering Information
Part Number Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK1302AEMQ80 MQUAD-80 Yes Yes -25°C to +85°C Rail CDK1302AEMQ80_Q MQUAD-80 No No -25°C to +85°C Rail CDK1302BEMQ80 MQUAD-80 Yes Yes -25°C to +85°C Rail CDK1302BEMQ80_Q MQUAD-80 No No -25°C to +85°C Rail Moisture sensitivity level for all parts is MSL-1.
features
n 1:2 Demuxed ECL compatible outputs n Wide input bandwidth – 900MHz n Low input capacitance – 15pF n Metastable errors reduced to 1 LSB n Monolithic for low cost n Gray code output
applications
n Radar, EW, ECM n Direct RF down-conversion General Description The CDK1302 is a full parallel (flash) analog-to-digital converter capable of digitizing full scale (0 to -2V) inputs into eight-bit digital words at an update rate of 750 MSPS. The ECL-compatible outputs are demultiplexed into two separate output banks, each with differential data ready outputs to ease the task of data capture. The CDK1302’s wide input bandwidth and low capacitance eliminate the need for external track-and-hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The CDK1302 operates from a single – 5.2V supply, with a nominal power dissipation of 5.5W. The CDK1302 is available in an 80-lead surface-mount MQuad package over the industrial temperature range (-25°C to +85°C). Block Diagram
©2008 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet CDK1302 8-bit, 750 MSPS, Flash A/D Converter REV 1A Pin Configuration MQUAD-80 CDK1302 Pin Assignments Pin Name Description VEE Negative Supply Nominally -5.2V AGND Analog Ground VRTF Reference Voltage Force Top, Nominally 0V VRTS Reference Voltage Sense Top VRM Reference Voltage Middle, Nominally -1V VRBF Reference Voltage Force Bottom, Nominally -2V VRBS Reference Voltage Sense Bottom VIN Analog Input Voltage, Can Be Either Voltage or Sense DGND Digital Ground D0-D7A Data Output Bank A D0-D7B Data Output Bank B DRA Data Ready Bank A DRA Not Data Ready Bank A DRB Data Ready Bank B DRB Not Data Ready Bank B D8A Overrange Output Bank A D8B Overrange Output Bank B CLK Clock Input CLK Clock Input
©2008 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet CDK1302 8-bit, 750 MSPS, Flash A/D Converter REV 1A Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de - vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Parameter Min Max Unit Supply Voltages Negative Supply Voltage (VEE to GND) -7.0 +0.5 V Ground Voltage Differential -0.5 +0.5 V Input Voltages Analog Input +0.5 VEE +0.5 V Reference Input +0.5 VEE +0.5 V Digital Input +0.5 VEE +0.5 V Reference Current Input (VRT to VRB) 35 mA Output Voltages Digital Output Current 0 -28 mA Reliability Information Parameter Min Typ Max Unit Storage Temperature Range -65 +150 °C Recommended Operating Conditions Parameter Min Typ Max Unit Operating Temperature Range - ambient -25 +85 °C Operating Temperature - case +125 °C Operating Temperature - junction +150 °C Lead Temperature, (soldering 10 seconds) +300 °C
©2008 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet CDK1302 8-bit, 750 MSPS, Flash A/D Converter REV 1A
Electrical Characteristics
(TJ = TC = TA = +25°C , VEE = -5.2V, VRB = -2.0V, VRM = -1.0V, VRT = 0.00V, ƒCLK = 750MHz, Duty Cycle=50%, unless otherwise specified) cDK1302a cDl1302B symbol parameter conditions Min typ Max Min typ Max units Resolution 8 8 bits DC Performance DLE Differential Linearity Error(1) ƒclk = 100MHz -1.0 +1.0 -1.5 +1.5 LSB ILE Integral Linearity Error(1) ƒclk = 100MHz -0.85 +0.95 -0.95 +1.5 LSB No Missing Codes Guaranteed Guaranteed Analog Input Input Voltage Range(1) VRB VRT VRB VRT V Input Bias Current(1) VIN = 0V 0.75 2.0 0.75 2.0 mA Input Resistance 15 15 kΩ Input Capacitance Over Full Input Range 15 15 pF Input Bandwidth Small Signal 900 900 MHz Large Signal 500 500 MHz Offset Error(2) VRT -30 +30 -30 +30 mV Offset Error(2) VRB -30 +30 -30 +30 mV Input Slew Rate 5 5 V/ns Clock Synchronous Input Currents 2 2 μA Reference Input Ladder Resistance(1) 60 80 60 80 Ω Reference Bandwidth 30 30 MHz Timing Characteristics Maximum Sample Rate(1) 750 750 MHz Aperture Jitter 2 2 ps Acquisition Time 250 250 ps Dynamic Performance SNR Signal-to-Noise Ratio ƒIN = 50MHz(1) 46 44 dB ƒIN = 250MHz(1) 44 42 dB THD Total Harmonic Distortion ƒIN = 50MHz(1) -45 -43 dBc ƒIN = 250MHz(1) -37 -35 dBc SFDR Spurious Free Dynamic Range ƒIN = 50MHz(1) 48 44 dB ƒIN = 250MHz(1) 40 36 dB SINAD Signal-to-Noise and Distortion ƒIN = 50MHz(1) 43 41 dB ƒIN = 250MHz(1) 36 34 dB notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. 3. Typical Thermal Impedance: θJC = +4°C/W.
©2008 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet CDK1302 8-bit, 750 MSPS, Flash A/D Converter REV 1A (TJ = TC = TA = +25°C , VEE = -5.2V, VRB = -2.0V, VRM = -1.0V, VRT = 0.00V, ƒCLK = 750MHz, Duty Cycle=50%, unless otherwise specified) cDK1302a cDK1302B symbol parameter conditions Min typ Max Min typ Max units Dynamic Inputs Input High Voltage(1) CLK, CLK -1.1 -0.7 -1.1 -0.7 V Input Low Voltage(1) CLK, CLK -1.8 -1.5 -1.8 -1.5 V tPWH Clock Pulse Width High(1) 0.67 0.5 0.67 0.5 ns tPWL Clock Pulse Width Low(1) 0.67 0.5 0.67 0.5 ns Digital Outputs Logic 1 Voltage(1) -1.1 -0.9 -1.1 -0.9 V Logic 0 Voltage(1) -1.8 -1.5 -1.8 -1.5 V Rise Time 20% to 80% 450 450 ps Fall Time 20% to 80% 450 450 ps Power Supply Requirements IEE Current(1) VIN = 0V 1.05 1.2 1.05 1.2 A Power Dissipation(1) 5.5 6.25 5.5 6.25 W notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. 3. Typical Thermal Impedance: θJC = +4°C/W.
codes while rejecting common mode noise. can provide full ECL swings into 50Ω loads. Figure 1. Typical Interface Circuit Diagram
VEE is the supply pin with AGND as ground for the device. device as possible with at least a 0.01μF ceramic capacitor. appropriately bypassed as shown in Figure 1. has constant capacitance and induces less slew rate distortion. lines to ensure the proper output rise and fall times. VRM may be bypassed for limited temperature operation. noise suppression if so desired. Table 1. Output Coding device is properly heat sinked.
then clocked through each one’s individual clock buffer. bit decoders when the CLK is changed from high to low. takes one clock cycle from the input to the data outputs. Figure 2. Timing Diagram
For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. caDeKa Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) Data Sheet CDK1302 8-bit, 750 MSPS, Flash A/D Converter REV 1A Ampl ify th e Human Exp eri ence Mechanical Dimensions Schematic Diagrams Input Circuit Output Circuit Clock Circuit MQUAD-80 INCHES MILLIMETERS SYMBOL MIN TYP MAX MIN TYP MAX A 0.904 0.923 22.95 23.45 B 0.777 0.781 19.74 19.84 C 0.472 12.00 D 0.541 0.545 13.74 13.84 E 0.667 0.687 16.95 17.45 F 0.031 0.80 G 0.012 0.018 0.30 0.45 H 0.109 0.134 2.76 3.40 I 0.010 0.024 0.25 0.60 J 0.724 18.40 K 0.099 0.110 2.51 L 0° 7° 0° 7° M 0.029 0.041 0.73 1.03