CDK1300

CDK1300 CADEKA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs REV 1A Data Sheet ©2008 CADEKA Microcircuits LLC www.cadeka.com Ampl ify th e Human Exp eri ence CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs

features

n TTL/CMOS/PECL input logic compatible n High conversion rate: 250 MSPS n Single +5V power supply n Very low power dissipation: 310mW n 220MHz full power bandwidth n Power-down mode n +3.0V/+5.0V (LVCMOS) digital output logic compatibility n Single/demuxed output ports selectable

applications

n High-speed instrumentation n Digital Sampling Oscilloscopes (DSO) n Projection display systems General Description The CDK1300 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process. An advanced folding and interpolating architecture provides both a high conversion rate and very low power dissipation of only 310mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5V common mode reference is provided on chip for the single-ended input mode to minimize external components. The CDK1300 digital outputs are demuxed (double-wide) with both dual- channel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0V and +5.0V compatible. The CDK1300 is available in a 44-lead TQFP surface mount package over the industrial temperature range of -40°C to +85°C. Block Diagram

Ordering Information

Part Number Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK1300ITQ44 TQFP-44 Yes Yes -40°C to +85°C Rail CDK1300ITQ44_Q TQFP-44 No No -40°C to +85°C Rail Moisture sensitivity level for all parts is MSL-1.

©2008 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs REV 1A Pin Configuration TQFP-44 CDK1300 Pin Assignments Pin No. Pin Name Description 40 VIN+ Non-inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally

39 VIN- Inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally

16-9 DA0–DA7 Data output bank A; 3V/5V LVCMOS compatible 19-26 DB0–DB7 Data output bank B; 3V/5V LVCMOS compatible

28 DCLKOUT Non-inverted data output clock; 3V/5V LVCMOS compatible

27 DCLKOUT Inverted data output clock; 3V/5V LVCMOS compatible

4 CLK Non-inverted clock input pin; 100k pulldown to AGND, internally

3 CLK Inverted clock input pin; 17.5k pullup to Vcc and 7.5k pulldown to AGND, internally

5 RESET

RESET synchronizes the data sampling and data output bank relationship when in dual channel mode (DMODE1 = 0); 100k pulldown to AGND, internally 6 RESET Inverted RESET input pin; 17.5k pullup to Vcc and 7.5 pulldown to AGND, internally 32, 31 DMODE1,2 Internally: 100k pulldown to AGND on DMODE1 50k pullup to Vcc on DMODE2 Data output mode pins: DMODE1 = 0, DMODE2 = 0: parallel dual channel output DMODE1 = 0, DMODE2 = 1: interleaved dual channel output DMODE1 = 1, DMODE2 = x: single channel data output on bank a (125 MSPS max) 2 PD Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down mode; 100k pulldown to AGND, internally 37 VCM 2.5V common mode voltage reference output 35, 36, 42, 43 AVCC +5V analog supply 7, 17, 30 OVDD +3V/+5V digital output supply 1, 33, 34, 38, 41, 44 AGND Analog ground 8, 18, 29 DGND Digital ground

©2008 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs REV 1A Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de - vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Parameter Min Max Unit Supply Voltage AVCC +6 V OVDD +6 V Input Voltages Analog inputs -0.5V Vcc +0.5V V Digital inputs -0.5V Vcc +0.5V V Reliability Information Parameter Min Typ Max Unit Storage Temperature Range -65 +125 °C Recommended Operating Conditions Parameter Min Typ Max Unit Operating Temperature Range -40 +85 °C

©2008 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs REV 1A

Electrical Characteristics

(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) symbol parameter conditions Min typ Max units Resolution 8 bits DC Performance DLE Differential Linearity Error +25°C, ƒIN = 1KHz -0.7/1.05 LSB -40°C to +85°C, ƒIN = 1KHz -0.95/+1.5 LSB ILE Integral Linearity Error +25°C, ƒIN = 1KHz ±1.7 LSB -40°C to +85°C, ƒIN = 1KHz ±2.25 LSB No Missing Codes @250 MSPS, ƒIN = 1KHz Guaranteed Analog Input Input Voltage Range with respect to VIN- ±470 mVpp VCM Input Common Mod(2) 2.3 2.5 2.0 V Input Bias Current +25°C 10 µA Input Resistance +25°C 50 kΩ Input Capacitance +25°C 4 pF Input Bandwidth +25°C (-3dB of FS) 220 MHz Gain Error +25°C 2 % Offset Error +25°C ±10 mV PSRR Offset Power Supply Rejection Ratio AVcc = 5V ±0.25V 0.5 mV/V Timing Characteristics Conversion Rate(1) 250 MSPS tpd1 Output Delay (Clock-to-Data)(2) -40°C to +85°C 6 8 10.5 ns Output Delay Tempco 22 ps/°C tap Aperture Delay Time 0.5 ns Aperture Jitter Time 2.0 ps-RMS Pipeline Delay (Latency) Single Channel Mode 2.5 Cycle Demuxed Interleaved Mode 2.5 Cycle Demuxed Parallel Mode Channel B 2.5 Cycle Channel A 3.5 Cycle CLK to DCLKOUT Delay Time tpd2 Single Channel Mode(2) 4 6 7 ns tpd3 Dual Channel Mode(2) 5.3 6.16 7.8 ns Dynamic Performance ENOB Effective Number of Bits ƒIN = 70MHz, +25°C(1) 5.8 6.4 Bits ƒIN = 70MHz, -40°C to +85°C(2) 5.5 6.0 Bits SNR Signal-to-Noise Ratio ƒIN = 70MHz, +25°C(1) 42 43 dB ƒIN = 70MHz, -40°C to +85°C(2) 36 40 dB THD Total Harmonic Distortion ƒIN = 70MHz, +25°C(1) -43 -40 dB ƒIN = 70MHz, -40°C to +85°C(2) -42 -37 dB SINAD Signal-to-Noise and Distortion ƒIN = 70MHz , +25°C(1) 37 40 dB ƒIN = 70MHz, -40°C to +85°C(2) 35 38 dB notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data.

©2008 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs REV 1A (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) symbol parameter conditions Min typ Max units Power Supply Requirements AVcc Analog Voltage Supply(2) 4.75 5.0 5.25 V OVDD Digital Voltage Supply(2) 2.75 5.25 V AVcc Current(1) 62 70 mA Power Dissipation(1) with Internal Voltage Reference 310 350 mW Common Mode Reference Output Voltage(1) 2.45 2.5 2.55 V Voltage Tempco 100 ppm/°C Output Impedance IOUT = ±50µA 1 kΩ PSRR Power Supply Rejection Ratio 63 mV/V Clock and Reset Inputs (Differential and Single-Ended) VDIFF Differental Signal Amplitude(1) 400 mVpp VIHD Differental High Input Voltage(2) 1.4 5 V VILD Differental Low Input Voltage(2) 0 3.9 V VCMD Differental Common Mode Input(2) 1.2 4.1 V VIH Single-Ended High Input Voltage(2) 1.8 V VIL Single-Ended Low Input Voltage(2) 1.2 V IIH High Input Current(1) VID = 1.5V -100 20 +100 µA IIL Low Input Current(1) VID = 1.5V -100 20 +100 µA Power Down and Mode Control Inputs (Single-Ended) High Input Voltage(2) 2.0 AVcc V Low Input Voltage(2) 0 1.0 V Max Input Current Low(1) -100 10 +100 µA Max Input Current High <4.0V(1) -100 10 +100 µA Digital Outputs Logic “1“ Voltage(1) IOH = -0.5mA OVDD-2.0 OVDD-0.06 V Logic “0“ Voltage(1) IOL = +1.6mA 0.13 0.2 V TR/TF Data OVDD = 3V, 10pF load 3.5 ns OVDD = 5V, 10pF load 2.0 ns TR/TF DCLK OVDD = 3V, 10pF load 1.3 ns OVDD = 5V, 10pF load 0.7 ns notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data.

©2008 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs REV 1A Typical Performance Characteristics (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) AC Performance vs. Temperature AC Performance vs. Temperature AVcc Current vs. Temperature AVcc Current Power Down vs. Temp. Voltage Offset Error vs. Temperature Percent Gain Error vs. Temperature -40 -20 0 40 Temperature (°C) SFDR, SNR, –THD, SINAD (dB) 20 100 SFDR –THD SINAD 60 80 SNR in = 70MHz 0 50 100 200 Sample Rate (MSPS) SFDR, SNR, –THD, SINAD (dB) 150 300 SFDR –THD SINAD 250 SNR in = 70MHz -40 -20 0 40 100 Temperature (°C) AVCC Current (mA) 20 60 80 -40 -20 0 40 3.0 2.8 2.6 2.4 2.2 2.0 Temperature (°C) AVcc (mA) 20 10060 80 -40 -20 0 40 6.0 4.0 2.0 -2.0 -4.0 -6.0 Temperature (°C) mV 20 10060 80 -40 -20 0 40 100 1.06 1.05 1.04 1.03 1.02 1.01 1.00 Temperature (°C) Gain (%) 20 60 80

©2008 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs REV 1A Typical Performance Characteristics (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) Input Bandwidth Common-Mode Ref. Voltage vs. VCC Total Power vs. Clock Frequency Diff. Input Common-Mode Oper. Range 0 100 200 400 Input Frequency (MHz) dB 300 600500 -2.50 -2.40 -2.42 -2.44 -2.46 -2.48 VCC (V) VCMOUT (V) 120 100 Clock Frequency (MHz) mA 0 50 100 200 300150 250 OVDD = 5V OVDD = 3V Clock Frequency (MHz) mA 0 25 50 100 15075 125 OVDD = 5V OVDD = 3V 1000 300 400 500 600 700 800 Clock Frequency (MHz) Power Dissipation (mW) 0 50 100 200 300150 250 OVDD = 5V OVDD = 3V -50 -40 0-20 40 100 Temperature (°C) Volts (V) 20 60 80 Common-Mode Operationg Range

and also performs single-ended to differential conversion. has hold mode feedthrough cancellation devices. cross-coupled to generate the eighth scale zero crossings. output bank via the differential RESET input. Figure 1. Single Mode Timing Diagram

Figure 2. Dual Mode Timing Diagram

For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. caDeKa Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) Data Sheet Ampl ify th e Human Exp eri ence CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs REV 1A Mechanical Dimensions Index C PIN1 E F G H I J K A B TQFP-44 INCHES MILLIMETERS SYMBOL MIN TYP MAX MIN TYP MAX A 0.472 12.00 B 0.394 10.00 C 0.394 10.00 D 0.472 12.00 E 0.031 0.80 F 0.012 0.018 0.300 0.45 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.018 0.030 0.45 0.75 J 0.039 1.00 K 0-7° 0-7° D Evaluation Board The TBD evaluation board is available to aid designers in demonstrating the full performance of the CDK1300. This board includes a clock driver and reset circuit, ad - justable references and common mode, a single-ended to differential input buffer and a single-ended to differential transformer (1:1). An application note (TBD) describing the operation of this board, as well as information on the testing of the CDK1300, is also available. Contact the factory for price and availability of the TBD.