CDCVF2505-Q1 TI1 | Alldatasheet
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V DD 3.3 V 1Y2 D P (TOP VIEW) ACKAGE
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www.ti.com SCAS867 DECEMBER 2008 3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER Qualified for Automotive
Applications
µ A (Typically) in Power Down Mode Phase-Locked Loop Clock Driver for Synchronous DRAM and General-Purpose Internal Feedback Loop Is Used to Ω On-Chip Series Damping Resistors Operating Frequency: MHz to 200 MHz Integrated RC PLL Loop Filter Eliminates the Need for External Components Low Jitter (Cycle-to-Cycle): 150 ps Over the Range MHz to 200 MHz Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Is Used to Tune the Input-Output Delay) Three-States Outputs When There Is No Input Clock Operates From Single 3.3-V Supply Available in 8-Pin SOIC Package The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0 and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN. Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost. Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference. The CDCVF2505 is characterized for operation from C to ORDERING INFORMATION (1) T A PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING C to C SOIC D Reel of 2500 CDCVF2505IDRQ1 CKV05Q (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Typical <10 MHz Power Down 3-State CLKOUT 1Y0 1Y1 1Y2 1Y3 CLKIN PLL 25 /c87 25 /c87 25 /c87 25 /c87 25 /c87 CDCVF2505-Q1 SCAS867 DECEMBER 2008 www.ti.com FUNCTION TABLE INPUT OUTPUTS CLKIN 1Y[0 CLKOUT L L L H H H MHz (1) Z Z (1) Below MHz (typical) the device goes into power-down mode, during which the PLL is turned off and the outputs enter into Hi-Z mode. If a 10-MHz signal is applied at CLKIN, the PLL turns on, reacquires lock, and stabilizes after approximately 100 µ The outputs are then enabled. FUNCTIONAL BLOCK DIAGRAM TERMINAL FUNCTIONS NAME NO. I/O outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25- Ω series O damping resistor. 1Y2 1Y3 Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver. CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLKIN must CLKIN I have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid signal is applied, a stabilization time (100 µ is required for the PLL to phase lock the feedback signal to CLKIN. Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is made inside CLKOUT O the chip and an external feedback loop should NOT be connected. CLKOUT can be loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs. GND Power Ground V DD 3.3V Power 3.3-V supply Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1
(1) ELECTROSTATIC DISCHARGE INFORMATION RECOMMENDED OPERATING CONDITIONS TIMING REQUIREMENTS CDCVF2505-Q1 www.ti.com SCAS867 DECEMBER 2008 over operating free-air temperature range (unless otherwise noted) V DD Supply voltage range 0.5 V to 4.3 V V I Input voltage range (2) (3) 0.5 V to V DD 0.5 V V O Output voltage range (2) (3) 0.5 V to V DD 0.5 V I IK Input clamp current V I or V I V DD mA I OK Output clamp current V O or V O V DD mA I O Continuous total output current V O to V DD mA θ JA Package thermal impedance (4) 97.1 C/W T stg Storage temperature range C to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) This value is limited to 4.3 V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7. ESD MODEL LIMIT HBM Human-Body Model 2000 V MM Machine Model 300 V CDM Charged-Device Model 1000 V MIN NOM MAX UNIT V DD Supply voltage 3.3 3.6 V V IH High-level input voltage 0.7 V DD V V IL Low-level input voltage 0.3 V DD V V I Input voltage V DD V I OH High-level output current mA I OL Low-level output current mA T A Operating free-air temperature C over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN NOM MAX UNIT f clk Clock frequency 200 MHz MHz to MHz (1) Input clock duty cycle MHz to 200 MHz Stabilization time (2) 100 µ s (1) Specified by design. (2) Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCVF2505-Q1
(1) CDCVF2505-Q1 SCAS867 DECEMBER 2008 www.ti.com over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V DD MIN TYP (1) MAX UNIT V IK Input voltage I I mA V 1.2 V I OH 100 µ A MIN to MAX V DD 0.2 V OH High-level output voltage I OH mA V 2.1 V I OH mA V 2.4 I OL 100 µ A MIN to MAX 0.2 V OL Low-level output voltage I OL mA V 0.8 V I OL mA V 0.55 V O V V I OH High-level output current mA V O 1.65 V 3.3 V V O V V I OL Low-level output current mA V O 1.65 V 3.3 V I I Input current V I V or V DD µ A C i Input capacitance V I V or V DD 3.3 V 4.2 pF Yn 2.8 C o Output capacitance V I V or V DD 3.3 V pF CLKOUT 5.2 (1) All typical values are at nominal V DD and T A over recommended ranges of supply voltage and operating free-air temperature, C L pF, V DD 3.3 V 0.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT t pd Propagation delay, normalized (see Figure CLKIN to Yn, f MHz to 200 MHz 150 150 ps t sk(o) Output skew (3) Yn to Yn 150 ps f MHz to 200 MHz 150 t c(jit_cc) Jitter (cycle to cycle) (see Figure ps f MHz to MHz 200 400 odc Output duty cycle (see Figure f MHz to 200 MHz at 50% V DD t r Rise time V O 0.4 V to V 0.5 ns t f Fall time V O V to 0.4 V 0.5 ns (1) Not production tested (2) All typical values are at nominal V DD and T A (3) The t sk(o) specification is only valid for equal loading of all outputs. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1
25 50 75 100 125 150 175 200 f – Frequency – MHz – Propagation Delay T ime – ps tpd, PROPAGATION DELAY TIME vs FREQUENCY (TYPICAL VALUES at 3.3 V, 25°C) tpd Load: CLKOUT = 12 pF || 500 ,/c87 Yn = 25 pF || 500 /c87 -1400 -1050 -700 -350 350 700 1050 1400 -30 -20 -10 0 10 20 30 – Pr opagation Delay T ime – ps t , PROPAGA , f = 100 MHz PD TION DELAY TIME vs DELTA LOAD (TYPICAL V , 25°C) CLOCK FREQUENCY ALUES at 3.3 V tpd Delta Load – pF CLKOUT = Yn = 25 pF || 500 /c87 3 pF || 500 /c87 NOTE: Delta Load = CLKOUT Load – Yn Load Yn = 25 pF Yn = 3 pF CLKOUT 3 pF to 25 pF CLKOUT 3 pF to 25 pF -13 -4 -50 -100 -150 0 50 100 – Propagation Delay T ime – ps50 100 f – Frequency – MHz tpd, TYPICAL PROPAGATION DELAY TIME vs FREQUENCY (TUNED FOR MINIMUM DELAY) 150 150 200 Load: CLKOUT = 21 pF || 500 ,/c87 Yn = 25 pF || 500 /c87 tpd 47.5 52.5 25 50 75 100 125 150 175 200 DUTY CYCLE vs FREQUENCY Duty Cyc le – % f – Frequency – MHz Load: CLKOUT = 12 pF || 500 ,/c87 Yn = 25 pF || 500 /c87 CDCVF2505-Q1 www.ti.com SCAS867 DECEMBER 2008 Figure Figure Figure Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCVF2505-Q1
25 50 75 100 125 150 175 200 – Cycle-to-Cycle Jitter – ps f – Frequency – MHz CYCLE-to-CYCLE JITTER vs FREQUENCY tc(jit_CC) Typical Values at 3.3 V, T A = 25/c176C 100 120 0 20 40 60 80 100 120 140 160 180 200 – Supply Current – mA I , SUPPLY CURRENT FREQUENCY CC vs Worst Case at VCC = 3.6 V, TA = 85°C, Load:Y and CLKOUT = 25 pF || 500 /c87 f – Frequency – MHz ICC CDCVF2505-Q1 SCAS867 DECEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1
500 /c87Yn = 25 pF || 500 CLKOUT = 12 pF || 500 /c87 /c87 From Output Under Test 50% VDD tpd CLKIN 1Y0–1Y3 2 V
0.4 V 50% VDD
0.4 V tr tf 3 V 0 V V OH VOL tsk(o) Any Y Any Y 50 % V DD 50 % VDD tc1 tc2 tc(jit_CC) = tc1 – t c2 CDCVF2505-Q1 www.ti.com SCAS867 DECEMBER 2008 Figure Test Load Circuit Figure Voltage Threshold for Measurements, Propagation Delay pd Figure Output Skew Figure 10. Cycle-to-Cycle Jitter Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCVF2505-Q1
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCVF2505IDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CDCVF2505-Q1 :
- Catalog:CDCVF2505 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2009 Addendum-Page 1
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