CDCVF2310 TI1 | Alldatasheet
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5 1Y(4...0) CLK CD CVF2310 2 5 Ω 52 5 Ω 2Y(4.. .0) Logic2G GND VDD VDD VDD VDD VDD GND GND GND GND Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community CDCVF2310 SCAS666D – JUNE 2001– REVISED OCTOBER 2015 CDCVF23102.5-Vto3.3-VHigh-PerformanceClockBuffer
1 Features 3 Description
The CDCVF2310 device is a high-performance, low- 1• High-Performance 1:10 Clock Driver skew clock buffer that operates up to 200 MHz. Two• Operates up to 200 MHz at VDD 3.3 V banks of five outputs each provide low-skew copies
- Pin-to-Pin Skew < 100 ps at VDD 3.3 V of CLK. After power up, the default state of the outputs is low regardless of the state of the control• VDD Range: 2.3 V to 3.6 V pins. For normal operation, the outputs of bank• Operating Temperature Range –40°C to 105°C 1Y[0:4] or 2Y[0:4] can be placed in a low state when• Supports 105ºC Ambient Temperature (see the control pins (1G or 2G, respectively) are held low Thermal Considerations) and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be• Output Enable Glitch Suppression switched into the buffer mode when the control pins• Distributes One Clock Input to Two Banks of Five (1G and 2G) are held high and a negative clock edgeOutputs is detected on the CLK input. The device operates in
- 25-Ω On-Chip Series Damping Resistors a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized• Packaged in 24-Pin TSSOP output enable sequence to distribute full period clock signals.2 Applications The CDCVF2310 is characterized for operation from• General-Purpose Applications –40°C to 85°C. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CDCVF2310 TSSOP (24) 4.40 mm × 7.80 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SCAS666D – JUNE 2001– REVISED OCTOBER 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (January 2008) to Revision D Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
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www.ti.com SCAS666D – JUNE 2001– REVISED OCTOBER 2015
5 Pin Configuration and Functions
NAME NO. Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the1G 11 I 1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high. Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the2G 13 I 2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high. 1Y[0:4] 3, 4, 5, 8, 9 O Buffered output clocks 2Y[0:4] 21, 20, 17, 16, 12 O Buffered output clocks CLK 24 I Input reference frequency GND 1, 6, 7, 18, 19 — Ground 2, 10, 14, 15, 22,VDD — DC power supply, 2.3 V – 3.6 V23
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Supply voltage –0.5 4.6 V VI (2) (3) Input voltage –0.5 VDD + 0.5 V VO (2) (3) Output voltage –0.5 VDD + 0.5 V IIK Input clamp current VI < 0 or VI> VDD ±50 mA Output clampIOK VO < 0 or VO > VDD ±50 mAcurrent Continuous totalIO VO = 0 to VDD ±50 mAoutput current TJ Maximum junction temperature 125 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) This value is limited to 4.6 V maximum. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CDCVF2310
SCAS666D – JUNE 2001– REVISED OCTOBER 2015 www.ti.com
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000ElectrostaticV(ESD) Vdischarge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See (1) MIN NOM MAX UNIT 2.3 2.5 VDD Supply voltage V 3.3 3.6 VDD = 3 V to 3.6 V 0.8 VIL Low-level input voltage V VDD = 2.3 V to 2.7 V 0.7 VDD = 3 V to 3.6 V 2 VIH High-level input voltage V VDD = 2.3 V to 2.7 V 1.7 VI Input voltage 0 VDD V VDD = 3 V to 3.6 V 12 IOH High-level output current mA VDD = 2.3 V to 2.7 V 6 VDD = 3 V to 3.6 V 12 IOL Low-level output current mA VDD = 2.3 V to 2.7 V 6 TA Operating free-air temperature –40 85 °C (1) Unused inputs must be held high or low to prevent them from floating.
6.4 Thermal Information
THERMAL METRIC (1) PW (TSSOP) UNIT
24 PINS
RθJA Junction-to-ambient thermal resistance 91.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 31.2 °C/W RθJB Junction-to-board thermal resistance 46.4 °C/W ψJT Junction-to-top characterization parameter 1.5 °C/W ψJB Junction-to-board characterization parameter 45.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIK Input voltage VDD = 3 V II = –18 mA –1.2 V II Input current VI = 0 V or VDD ±5 μA -40°C to 85°C 80 μACLK = 0 V or VDD ,IDD Static device current IO = 0 mA ≤105°C 100 μA CI Input capacitance VDD = 2.3 V to 3.6 V VI = 0 V or VDD 2.5 pF CO Output capacitance VDD = 2.3 V to 3.6 V VI = 0 V or VDD 2.8 pF (1) All typical values are at respective nominal VDD.
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www.ti.com SCAS666D – JUNE 2001– REVISED OCTOBER 2015 Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VDD = 3.3 V ±0.3 V VDD = min to max IOH = –100 μA VDD – 0.2 VOH High-level output voltage IOH = –12 mA 2.1 V VDD = 3 V IOH = –6 mA 2.4 VDD = min to max IOL = –100 μA 0.2 VOL Low-level output voltage IOL = 12 mA 0.8 V VDD = 3 V IOL = 6 mA 0.55 VDD = 3 V VO = 1 V –28 IOH High-level output current VDD = 3.3 V VO = 1.65 V –36 mA VDD = 3.6 V VO = 3.135 V –14 VDD = 3 V VO = 1.95 V 28 IOL Low-level output current VDD = 3.3 V VO = 1.65 V 36 mA VDD = 3.6 V VO = 0.4 V 14 VDD = 2.5 V ±0.2 V VDD = min to max IOH = –100 μA VDD – 0.2 VOH High-level output voltage V VDD = 2.3 V IOH = –6 mA 1.8 VDD = min to max IOL = 100 μA 0.2 VOL Low-level output voltage V VDD = 2.3 V IOL = 6 mA 0.55 VDD = 2.3 V VO = 1 V –17 IOH High-level output current VDD = 2.5 V VO = 1.25 V –25 mA VDD = 2.7 V VO = 2.375 V –10 VDD = 2.3 V VO = 1.2 V 17 IOL Low-level output current VDD = 2.5 V VO = 1.25 V 25 mA VDD = 2.7 V VO = 0.3 V 10
6.6 Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT VDD = 3 V to 3.6 V 0 200 fclk Clock frequency MHz VDD = 2.3 V to 2.7 V 0 170
6.7 Jitter Characteristics
Characterized using CDCVF2310 Performance EVM when VDD= 3.3 V. Outputs not under test are terminated to 50 Ω. PARAMETER TEST CONDITIONS TYP UNIT 12 kHz to 5 MHz, fout = 30.72 MHz 52 tjitter Additive phase jitter from input to output 1Y0 fs rms 12 kHz to 20 MHz, fout = 125 MHz 45 Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: CDCVF2310
SCAS666D – JUNE 2001– REVISED OCTOBER 2015 www.ti.com
6.8 Switching Characteristics
VDD= 3.3V ±0.3V (see Figure 2) and over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tPLH f = 0 MHz to 200 MHzCLK to Yn 1.3 2.8 nsFor circuit load, see Figure 2.tPHL tsk(o) Output skew (Ym to Yn) (1) (see Figure 4) 100 ps tsk(p) Pulse skew (see Figure 5) 250 ps tsk(pp) Part-to-part skew 500 ps tr Rise time (see Figure 3) VO = 0.4 V to 2 V 0.7 2 V/ns tf Fall time (see Figure 3) VO = 2 V to 0.4 V 0.7 2 V/ns tsu(en) Enable setup time, G_high before CLK ↓ 0.1 ns tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns th(en) Enable hold time, G_high after CLK ↓ 0.4 ns th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns (1) The tsk(o) specification is only valid for equal loading of all outputs.
6.9 Switching Characteristics
VDD= 2.5V ±0.2V (see Figure 2) and over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tPLH f = 0 MHz to 170 MHzCLK to Yn 1.5 3.5 nsFor circuit load, see Figure 2.tPHL tsk(o) Output skew (Ym to Yn) (1) (see Figure 4 ) 170 ps tsk(p) Pulse skew (see Figure 5) 400 ps tsk(pp) Part-to-part skew 600 ps tr Rise time (see Figure 3) VO = 0.4 V to 1.7 V 0.5 1.4 V/ns tf Fall time (see Figure 3) VO = 1.7 V to 0.4 V 0.5 1.4 V/ns tsu(en) Enable setup time, G_high before CLK ↓ 0.1 ns tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns th(en) Enable hold time, G_high after CLK ↓ 0.4 ns th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns (1) The tsk(o) specification is only valid for equal loading of all outputs.
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6.10 Typical Characteristics
Figure 1. Supply Current vs Frequency
1.7 V or 2 V
7 Parameter Measurement Information
A. CL includes probe and jig capacitance. Figure 2. Test Load Circuit Figure 3. Voltage Waveforms Propagation Delay Times Figure 4. Output Skew Figure 5. Pulse Skew
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25 Ω 25 Ω 25 Ω 25 Ω 25 Ω 25 Ω 25 Ω 25 Ω 25 Ω 25 Ω Logic Control Logic Control 1Y0 1Y1 1Y2 1Y3 1Y4 2Y0 2Y1 2Y2 2Y3 2Y4 CLK CDCVF2310 www.ti.com SCAS666D – JUNE 2001– REVISED OCTOBER 2015
8 Detailed Description
8.1 Overview
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5- V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Output Enable Glitch Suppression Circuit
edge triggered by the input clock) (see Figure 6). Figure 6. Enable and Disable Mode Relative to CLK↓
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8.4 Device Functional Modes
Table 1 lists the functional modes for the CDCVF2310. Table 1. Function Table follows the input CLK if the control pin is held high.
100 MHZ
50 Trace/c87
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
outputs as necessary in the application.
9.2 Typical Application
Figure 7. Example System Configuration
9.2.1 Design Requirements
The CDCVF2310 shown in Figure 7 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator. The CPU is configured to control the output state through 1G.
- The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near the CDCVF2310 to closely match the characteristic impedance of the trace to minimize reflections.
- The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the CDCVF2310.
- The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used. The PLL receiver features internal biasing, so AC-coupling can be used when common-mode voltage is mismatched.
9.2.2 Detailed Design Procedure
output impedance of the CDCVF2310 to that of the characteristic impedance of the transmission line.
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9.2.3 Application Curves
Figure 9. CDCVF2310 Output Phase Noise 169.6 fsFigure 8. CDCVF2310 Output Phase Noise 89.1 fs additive jitter when integrated from 12 kHz to 5 MHz for this configuration. Figure 10. CDCVF2310 Configured as Gate Function for Output Clock Suppression Circuit for required timings.
10 Power Supply Recommendations
jitter or phase noise is critical to applications. required for proper operation. Figure 12 shows this recommended power supply decoupling method. Figure 11. Power Supply Decoupling
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11 Layout
11.1 Layout Guidelines
of the capacitor using a low-impedance connection to the ground plane.
11.2 Layout Example
Figure 12. PCB Conceptual Layout
11.3 Thermal Considerations
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following: Using Thermal Calculation Tools for Analog Components, SLUA566
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 16-Jul-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CDCVF2310PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKV2310 CDCVF2310PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKV2310 CDCVF2310PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKV2310 CDCVF2310PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKV2310 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
www.ti.com 16-Jul-2015 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CDCVF2310 :
- Enhanced Product: CDCVF2310-EP NOTE: Qualified Version Definitions:
- Enhanced Product - Supports Defense, Aerospace and Medical Applications
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCVF2310PWR TSSOP PW 24 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2015 Pack Materials-Page 2
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