CDCV857B TI | Alldatasheet
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Technical content
/C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0044 /C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0073 /C0050/C0046/C0053/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 SCAS689 − FEBRUARY 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM
Applications
/C0068Spread Spectrum Clock Compatible /C0068Operating Frequency: 60 MHz to 200 MHz /C0068Low Jitter (cycle-cycle): ±50 ps /C0068Low Static Phase Offset: ±50 ps /C0068Low Jitter (Period): ±35 ps /C0068Distributes One Differential Clock Input to
10 Differential Outputs
/C0068Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low /C0068Operates From Dual 2.5-V Supplies /C0068Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior BGA Package /C0068Consumes < 100-µA Quiescent Current /C0068External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks /C0068Meets/Exceeds the Latest DDR JEDEC Spec JESD82−1
description
The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT ). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD ). When PWRDWN is high, theoutputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state) and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs. When AV DD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857B is also able to track spread spectrum clocking for reduced EMI. Since the CDCV857B is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857B is characterized for both commercial and industrial temperature ranges. AVAILABLE OPTIONS TA TSSOP (DGG) MicroStar Junior BGA (GQL) 0°C to 85°C CDCV857BDGG CDCV857BGQL −40°C to 85°C CDCV857BIGG — FUNCTION TABLE (Select Functions) INPUTS OUTPUTS PLL AV DD PWRDWN CLK CLK Y[0:9] Y[0:9] FBOUT FBOUT GND H L H L H L H Bypassed/Off GND H H L H L H L Bypassed/Off X L L H Z Z Z Z Off X L H L Z Z Z Z Off
2.5 V (nom) H L H L H L H On
2.5 V (nom) H H L H L H L On
2.5 V (nom) X <20 MHz <20 MHz Z Z Z Z Off
Copyright 2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments Incorporated.
/C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0044 /C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0073 /C0050/C0046/C0053/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 SCAS689 − FEBRUARY 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A B C D E F 321 G H CLK NC NC NC NC NC NC NC NC NC NC GND MicroStar Junior (GQL) Package (TOP VIEW) GND J K NC GND VDDQ VDDQ AGND GND AV DD CLK VDDQ GND GND GND PWRDN VDDQ FBIN FBIN VDDQ FBOUT FBOUT GND V DDQ V DDQ V DDQ GND V DDQ GND GND VDDQ GND GND VDDQ VDDQ CLK CLK VDDQ AV DD AGND GND VDDQ GND GND V DDQ GND GND V DDQ PWRDWN FBIN FBIN VDDQ FBOUT FBOUT GND V DDQ GND DGG PACKAGE (TOP VIEW)
/C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0044 /C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0073 /C0050/C0046/C0053/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 SCAS689 − FEBRUARY 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram Y829 Y739 Y644 Y546 Y422 Y320 Y210 Y15 Y03 Y927 FBOUT32 Power Down and Test Logic PLL PWRDWN AV DD CLK CLK FBIN FBIN FBOUT
/C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0044 /C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0073 /C0050/C0046/C0053/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 SCAS689 − FEBRUARY 2003
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DESCRIPTIONNAME DGG GQL DESCRIPTION AGND 17 H1 Ground for 2.5-V analog supply AV DD 16 G2 2.5-V Analog supply CLK, CLK 13, 14 F1, F2 I Differential clock input FBIN, FBIN 35, 36 F5, F6 I Feedback differential clock input FBOUT, FBOUT 32, 33 H6, G5 O Feedback differential clock output GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 A3, A4, C1, C2, C5, C6, H2, H5, K3, K4 Ground PWRDWN 37 E6 I Output enable for Y and Y VDDQ 4, 11, 12, 15, 21, 28, 34, 38, 45 B3, B4, E1, E2, E5, G1, G6, J3, J4 2.5-V Supply Y[0:9] 3, 5, 10, 20, 22, 27, 29, 39, 44, A1, B2, D1, J2, K1, A6, B5, D6, J5, K6 O Buffered output copies of input clock, CLK 23, 26, 30, 40, 43, 47 A2, B1, D2, J1, K2, A5, B6, D5, J6, K5 O Buffered output copies of input clock, CLK absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
/C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0044 /C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0073 /C0050/C0046/C0053/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 SCAS689 − FEBRUARY 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 4) MIN TYP MAX UNIT Supply voltage VDDQ 2.3 2.7 V Supply voltage AV DD VDDQ − 0.12 2.7 V Low-level input voltage, VIL CLK, CLK, FBIN, FBIN VDDQ /2 – 0.18 VLow-level input voltage, VIL PWRDWN −0.3 0.7 V High-level input voltage, VIH CLK, CLK, FBIN, FBIN VDDQ /2 + 0.18 VHigh-level input voltage, VIH PWRDWN 1.7 VDDQ + 0.3 V DC input signal voltage (see Note 5) –0.3 VDDQ + 0.3 V Differential input signal voltage, VID (see Note 6) dc CLK, FBIN 0.36 VDDQ + 0.6 VDifferential input signal voltage, VID (see Note 6) ac CLK, FBIN 0.7 VDDQ + 0.6 V Input differential pair cross voltage, VIX (see Note 7) VDDQ /2 – 0.2 VDDQ /2 + 0.2 V High-level output current, IOH −12 mA Low-level output current, IOL 12 mA Input slew rate, SR 1 4 V/ns Operating free-air temperature, TA Commercial 0 85 °COperating free-air temperature, TA Industrial −40 85 NOTES: 4. The unused inputs must be held high or low to prevent them from floating. 5. The dc input signal voltage specifies the allowable dc execution of the differential input. 6. The differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 7. The differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK Input voltage All inputsVDDQ = 2.3 V, II = –18 mA –1.2 V VOH High-level output voltage VDDQ = min to max, IOH = –1 mA VDDQ – 0.1 VVOH High-level output voltage VDDQ = 2.3 V, IOH = –12 mA 1.7 V VOL Low-level output voltage VDDQ = min to max, IOL = 1 mA 0.1 VVOL Low-level output voltage VDDQ = 2.3 V, IOL = 12 mA 0.6 V VOD Output voltage swing/C0125 Differential outputs are terminated with 120Ω /CL = 14 pF (See 1.1 VDDQ – 0.4 V VOX Output differential cross-voltage/C0119 with 120Ω /CL = 14 pF (See Figure 3) VDDQ /2 – 0.15VDDQ /2 VDDQ /2 + 0.15 V II Input current VDDQ = 2.7 V, VI = 0 V to 2.7 V ±10 µA IOZ High-impedance state output currentVDDQ = 2.7 V, VO = VDDQ or GND ±10 µA IDDPD Power-down current on VDDQ + AVDD CLK and CLK = 0 MHz; PWRDWN = Low; Σ of IDD and AIDD 20 100 µA AIDD Supply current on AVDD fO = 170 MHz 7 10 mAAIDD Supply current on AVDD fO = 200 MHz 9 12 mA C I Input capacitance VDDQ = 2.5 V, VI = VDDQ or GND 2 2.5 3.5 pF † All typical values are at a respective nominal VDDQ . ‡ The differential output signal voltage specifies the differential voltage VTR − VCP , where VTR is the true output level and VCP is the complementary output level. § The differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing. The frequency range is 100 MHz to 200 MHz.
/C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0044 /C0067/C0068/C0067/C0086/C0056/C0053/C0055/C0066/C0073 /C0050/C0046/C0053/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 SCAS689 − FEBRUARY 2003
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Without load fO = 170 MHz 100 110 Without load fO = 200 MHz 105 120 Differential outputs terminated with fO = 170 MHz 200 240 IDD Dynamic current on VDDQ terminated with 120 Ω/CL = 0 pF fO = 200 MHz 210 250 mA Differential outputs terminated with fO = 170 MHz 260 300 terminated with 120 Ω/CL = 14 pF fO = 200 MHz 280 320 ∆C Part-to-part input capacitance variation VDDQ = 2.5 V, VI = VDDQ or GND 1 pF C I(∆) Input capacitance difference between CLK and CLKB, FBIN, and FBINB VDDQ = 2.5 V, VI = VDDQ or GND 0.25 pF C O Output capacitance VDDQ = 2.5 V, VO = VDDQ or GND 2.5 3 3.5 pF † All typical values are at a respective nominal VDDQ . timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT fCLK Operating clock frequency 60 200 MHzfCLK Application clock frequency 60 200 MHz Input clock duty cycle 40% 60% Stabilization time/C0123 (PLL mode) 10 µs Stabilization time/C0125 (Bypass mode) 30 ns † The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. ‡ A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND). switching characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH /C0119 Low to high level propagation delay time Test mode/CLK to any output 3.5 ns tPHL /C0119 High-to low level propagation delay time Test mode/CLK to any output 3.5 ns tjit(per)/C0087Jitter (period), See Figure 7
66 MHz −60 60 ps
tjit(per)/C0087Jitter (period), See Figure 7 100/133/167/200 MHz −35 35 ps tjit(cc)/C0087Jitter (cycle-to-cycle), See Figure 4
66 MHz −75 75
pstjit(cc)/C0087Jitter (cycle-to-cycle), See Figure 4 100/133/167/200 MHz −50 50 ps tjit(hper)/C0087Half-period jitter, See Figure 8
66 MHz −100 100
pstjit(hper)/C0087Half-period jitter, See Figure 8 100/133/167/200 MHz −75 75 ps tslr(o) Output clock slew rate, See Figure 9 Load: 120 Ω/14 pF 1 2 V/ns t(Ø) Static phase offset, See Figure 5
66 MHz –100 100
pst(Ø) Static phase offset, See Figure 5 100/133/167/200 MHz –50 50 ps tsk(o) Output skew, See Figure 6 Load: 120 Ω/14 pF 70 100 ps tr, tf Output rise and fall times (20% − 80%) Load: 120 Ω/14 pF 600 900 ps § Refers to the transition of the noninverting output. ¶ This parameter is assured by design but can not be 100% production tested.
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 3. Output Load Test Circuit for Crossing Point Figure 4. Cycle-to-Cycle Jitter
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Figure 7. Period Jitter Figure 8. Half-Period Jitter Figure 9. Input and Output Slew Rates
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCV857BDGG ACTIVE TSSOP DGG 48 40 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CDCV857BDGGR ACTIVE TSSOP DGG 48 2000 None Call TI Call TI CDCV857BGQLR ACTIVE VFBGA GQL 56 1000 None Call TI Level-2A-220C-4 WKS CDCV857BIDGG ACTIVE TSSOP DGG 48 40 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CDCV857BIDGGR ACTIVE TSSOP DGG 48 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 Addendum-Page 1
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97
48 PINS SHOWN
0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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