CDCV857ADGGG4

CDCV857A_08 TI1 | Alldatasheet

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Technical content

2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM

Applications

/C0068 Spread Spectrum Clock Compatible /C0068 Operating Frequency: 60 to 180 MHz /C0068 Low Jitter (cyc–cyc): ±50 ps /C0068 Distributes One Differential Clock Input to Ten Differential Outputs /C0068 Three-State Outputs When the Input Differential Clocks Are <20 MHz /C0068 Operates From Dual 2.5-V Supplies /C0068 Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior BGA Package /C0068 Consumes < 200-µA Quiescent Current /C0068 External Feedback PIN (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks

description

The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK ) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD ). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs. When AV DD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able to track spread spectrum clocking for reduced EMI. Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C. Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments Incorporated.

2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002

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A B C D E F 321 G H CLK NC NC NC NC NC NC NC NC NC NC GND MicroStar Junior (GQL) Package (TOP VIEW) GND J K NC GND VDDQ VDDQ AGND GND AV DD CLK VDDQ GND GND GND PWRDN VDDQ FBIN FBIN VDDQ FBOUT FBOUT GND V DDQ V DDQ V DDQ GND V DDQ GND GND VDDQ GND GND VDDQ VDDQ CLK CLK VDDQ AV DD AGND GND VDDQ GND GND V DDQ GND GND V DDQ PWRDWN FBIN FBIN VDDQ FBOUT FBOUT GND V DDQ GND DGG PACKAGE (TOP VIEW)

2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE (Select Functions) INPUTS OUTPUTS PLL AV DD PWRDWN CLK CLK Y[0:9] Y[0:9] FBOUT FBOUT GND H L H L H L H Bypassed/Off GND H H L H L H L Bypassed/Off X L L H Z Z Z Z Off X L H L Z Z Z Z Off

2.5 V (nom) H L H L H L H On

2.5 V (nom) H H L H L H L On

2.5 V (nom) X <20 MHz <20 MHz Z Z Z Z Off

2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002

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AGND 17 H1 Ground for 2.5-V analog supply AV DD 16 G2 2.5-V Analog supply CLK, CLK 13, 14 F1, F2 I Differential clock input FBIN, FBIN 35, 36 F5, F6 I Feedback differential clock input FBOUT, FBOUT 32, 33 H6, G5 O Feedback differential clock output GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 A3, A4, C1, C2, C5, C6, H2, H5, K3, K4 Ground PWRDWN 37 E6 I Output enable for Y and Y VDDQ 4, 11, 12, 15, 21, 28, 34, 38, 45 B3, B4, E1, E2, E5, G1, G6, J3, J4 2.5-V Supply Y[0:9] 3, 5, 10, 20, 22, 27, 29, 39, 44, A1, B2, D1, J2, K1, A6, B5, D6, J5, K6 O Buffered output copies of input clock, CLK 23, 26, 30, 40, 43, 47 A2, B1, D2, J1, K2, A5, B6, D5, J6, K5 O Buffered output copies of input clock, CLK absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.

2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 4) MIN TYP MAX UNIT Supply voltage, VDDQ, AVDD 2.3 2.7 V Low level input voltage VIL CLK, CLK, FBIN, FBIN VDDQ /2 – 0.18 VLow level input voltage, VIL PWRDWN –0.3 0.7 V High level input voltage VIH CLK, CLK, FBIN, FBIN VDDQ /2 + 0.18 VHigh level input voltage, VIH PWRDWN 1.7 VDDQ + 0.3 V DC input signal voltage (see Note 5) –0.3 VDDQ V Differential input signal voltage VID (see Note 6) DC CLK, FBIN 0.36 VDDQ + 0.6 VDifferential input signal voltage, VID (see Note 6) AC CLK, FBIN 0.7 VDDQ + 0.6 V Output differential cross-voltage, VOX (see Note 7) VDDQ /2 – 0.2 VDDQ /2 VDDQ /2 + 0.2 V Input differential pair cross-voltage, VIX (see Note 7) VDDQ /2 – 0.2 VDDQ /2 + 0.2 V High-level output current, IOH –12 mA Low-level output current, IOL 12 mA Input slew rate, SR 1 4 V/ns Operating free-air temperature, TA 0 85 °C NOTES: 4. Unused inputs must be held high or low to prevent them from floating. 5. DC input signal voltage specifies the allowable dc execution of differential input. 6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing.

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK Input voltage All inputs VDDQ = 2.3 V, II = –18 mA –1.2 V VOH High level output voltage VDDQ = min to max, IOH = –1 mA VDDQ – 0.1 VVOH High-level output voltage VDDQ = 2.3 V, IOH = –12 mA 1.7 V VOL Low level output voltage VDDQ = min to max, IOL = 1 mA 0.1 VVOL Low -level output voltage VDDQ = 2.3 V, IOL = 12 mA 0.6 V IOH High-level output currentVDDQ = 2.3 V, VO = 1 V –18 –32 mA IOL Low-level output currentVDDQ = 2.3 V, VO = 1.2 V 26 35 mA VO Output voltage swing Differential outputs are terminated with 1.1 VDDQ – 0.4 VOX Output differential cross-voltage/C0119 Differential outputs are terminated with 120 Ω VDDQ /2 – 0.2 VDDQ /2 VDDQ /2 + 0.2 V II Input current VDDQ = 2.7 V, VI = 0 V to 2.7 V ±10 µA IOZ High-impedance-state output current VDDQ = 2.7 V, VO = VDDQ or GND ±10 µA IDDPD Power down current on VDDQ + AVDD CLK and CLK = 0 MHz; PWRDWN = Low; Σ of IDD and AIDD 100 200 µA Differential outputs terminated with fO = 180 MHz 275 330 IDD Dynamic current on VDDQ terminated with 120 Ω /CL = 14 pF fO = 167 MHz 250 300 mAIDD Dynamic current on VDDQ Differential outputs terminated with fO = 180 MHz 225 275 mA terminated with 120 Ω /CL = 0 pF fO = 167 MHz 210 250 AIDD Supply current on AVDD fO = 180 MHz 10 12 mAAIDD Supply current on AV DD fO = 167 MHz 8 10 mA C I Input capacitance VCC = 2.5 V VI = VCC or GND 2 2.5 3 pF C O Output capacitance VCC = 2.5 V VO = VCC or GND 2.5 3 3.5 pF † All typical values are at respective nominal VDDQ . ‡ The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input signal voltage and VCP is the complementary input signal voltage. § Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing. timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT fCLK Operating clock frequency 60 180 MHzfCLK Application clock frequency 60 180 MHz Input clock duty cycle 40% 60% Stabilization time/C0087 (PLL mode) 10 µs Stabilization time/C0087 (Bypass mode) 30 ns ¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application.

2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics PARAMETER TEST CONDITIONS MIN TYP /C0123 MAX UNIT tPLH /C0125 Low to high level propagation delay time Test mode/CLK to any output 4.5 ns tPHL /C0125 High-to low level propagation delay time Test mode/CLK to any output 4.5 ns tjit( )/C0119 Jitter (period) See Figure 6

66 MHz –55 55 ps

tjit(per)/C0119 Jitter (period), See Figure 6 100/133/167/180 MHz –35 35 ps tjit( )/C0119 Jitter (cycle to cycle) See Figure 3

66 MHz –60 60

pstjit(cc)/C0119 Jitter (cycle-to-cycle), See Figure 3 100/133/167/180 MHz –50 50 ps tjit(h )/C0119 Halfperiod jitter See Figure 7

66 MHz –100 100

pstjit(hper)/C0119 Half-period jitter, See Figure 7 100/133/167/180 MHz –75 75 ps tslr(i) Input clock slew rate, See Figure 8 1 4 V/ns tslr(o) Output clock slew rate, See Figure 8 1 2 V/ns /C0119

66 MHz –180 180

/C0119 SSC off 100/133 MHz –130 130 td(Ø )/C0119 Dynamic phase offset (this includes jitter), See 167/180 MHz –90 90 pstd(Ø )/C0119 y( j ) , Figure 4(b) 66 MHz –230 230 ps SSC on 100/133 MHz –170 170 167/180 MHz –100 100 t(Ø ) Staticphase offset See Figure 4(a)

66 MHz –150 150

pst(Ø ) Static phase offset, See Figure 4(a) 100/133/167/180 MHz –100 100 ps tsk(o)/C0087 Output skew, See Figure 5 75 ps tr, tf Output rise and fall times (20% – 80%) Load: 120 Ω /14 pF 650 900 ps † All typical values are at a respective nominal VDDQ . ‡ Refers to transition of noninverting output. § This parameter is assured by design but can not be 100% production tested. ¶ All differential output pins are terminated with 120 Ω /14 pF.

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Figure 1. IBIS Model Output Load (used for slew rate measurement) Figure 2. Output Load Test Circuit Figure 3. Cycle-to-Cycle Jitter

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Figure 6. Period Jitter Figure 7. Half-Period Jitter Figure 8. Input and Output Slew Rates

2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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GQL (R-PBGA-N56) PLASTIC BALL GRID ARRAY ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ 4200583/D 06/2002 4,60 4,40 7,10 6,90 3X Via Hole Without Ball Missing Via Hole Indicates Pin A1 Quadrant M0,05 0,65 0,08 0,65 0,35 0,45 1,00 MAX Seating Plane 0,15 0,25 123 6 45 3,25 A C B E D F K G H J 0,325 5,85 0,325 A1 Corner Bottom View 56×∅ NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar Junior BGA configuration D. Falls within JEDEC MO-225 variation BA. E. This package is tin-lead (SnPb). Refer to the 56 ZQL package (drawing 4204437) for lead-free. MicroStar Junior is a trademark of Texas Instruments.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCV857ADGG ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCV857ADGGG4 ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCV857ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCV857ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCV857AGQLR ACTIVE BGA MI CROSTA R JUNI OR GQL 56 1000 TBD SNPB Level-2A-220C-4 WKS (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 13-Feb-2006 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CDCV857AGQLR BGA MI CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCV857ADGGR TSSOP DGG 48 2000 346.0 346.0 41.0 CDCV857AGQLR BGA MICROSTAR JUNIOR GQL 56 1000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2

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