CDCV850IDGGRG4

CDCV850DGG TI1 | Alldatasheet

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2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM

Applications

/C0068Spread Spectrum Clock Compatible /C0068Operating Frequency: 60 to 140 MHz /C0068Low Jitter (cyc−cyc): ±75 ps /C0068Distributes One Differential Clock Input to Ten Differential Outputs /C0068Two-Line Serial Interface Provides Output Enable and Functional Control /C0068Outputs Are Put Into a High-Impedance State When the Input Differential Clocks Are <20 MHz /C006848-Pin TSSOP Package /C0068Consumes <250-μA Quiescent Current /C0068External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks

description

The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK ) to ten differential pairs of clock outputs (Y[0:9], Y[0:9] ) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are con- trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA, SCLK), and the analog power input (AVDD). A two-line serial interface can put the individual output clock pairs in a high-impedance state. When the AVDD terminal is tied to GND, the PLL is turned off and bypassed for test purposes. The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 kΩ). Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit is written to the control register. The registers must be accessed in sequential order (i.e., random access of the registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in applications where this programming option is not required (after power up, all output pairs will then be enabled). When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz), the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI. Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up, as well as changes to various 2-line serial registers that affect the PLL. The CDCV850 is characterized in a temperature range from −40°C to 85°C. Copyright © 2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. GND VDDQ GND GND VDDQ SCLK CLK CLK VDDI AVDD AGND GND VDDQ GND GND V DDQ GND GND V DDQ SDATA FBIN FBIN VDDQ FBOUT FBOUT GND V DDQ GND DGG PACKAGE (TOP VIEW)

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013

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T PACKAGED DEVICES TA TSSOP (DGG) −40°C to 85°C CDCV850DGG FUNCTION TABLE (Select Functions) INPUTS OUTPUTS† PLLAVDD CLK CLK Y[0:9] Y[0:9] FBOUT FBOUT PLL GND L H L H L H Bypassed/Off GND H L H L H L Bypassed/Off

2.5 V (nom) L H L H L H On

2.5 V (nom) H L H L H L On

2.5 V (nom) <20 MHz <20 MHz Hi-Z Hi-Z Hi-Z Hi-Z Off

† Each output pair (except FBOUT, FBOUT) can be put into a high-impedance state through the 2-line serial interface. functional block diagram PLL AVDD VDDI Interface Logic CLK FBIN FBIN CLK SDATA SCLK 2-Line Serial FBOUT FBOUT

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AGND 17 Ground for 2.5-V analog supply AVDD 16 2.5-V analog supply CLK, CLK 13, 14 I Differential clock input FBIN, FBIN 35, 36 I Feedback differential clock input FBOUT, FBOUT 32, 33 O Feedback differential clock output GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 Ground SCLK 12 I Clock input for 2-line serial interface SDATA 37 I/O Data input/output for 2-line serial interface VDDQ 4, 11, 21, 28, 34, 38, 2.5-V supply VDDI 15 I 2.5-V or 3.3-V supply for 2-line serial interface Y[0:9] 3, 5, 10, 20, 22, 27, 29, 39, 44, O Buffered output copies of input clock, CLK 23, 26, 30, 40, 43, 47 O Buffered output copies of input clock, CLK

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observe d. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) MIN TYP MAX UNIT Supply voltage VDDQ, AVDD 2.3 2.7 VSupply voltage VDDI (see Note 5) 2.3 3.6 V CLK, CLK, HCSL Buffer only 0 0.24 Low level input voltage V CLK, CLK −0.3 VDDQ − 0.4 VLow level input voltage, VIL FBIN, FBIN VDDQ/2 − 0.18 V SDATA, SCLK 0.3 × VDDI CLK, CLK, HCSL Buffer only 0.66 0.71 High level input voltage V CLK, CLK 0.4 VDDQ + 0.3 VHigh level input voltage, VIH FBIN, FBIN VDDQ/2 + 0.18 V SDATA, SCLK 0.7 × VDDI DC input signal voltage (see Note 6) –0.3 VDDQ + 0.3 V Differential input signal voltage V (see Note 7) DC CLK, FBIN 0.36 VDDQ + 0.6 VDifferential input signal voltage, VID (see Note 7) AC CLK, FBIN 0.2 VDDQ + 0.6 V Input differential pair cross-voltage, VIX (see Note 8) 0.45×(VIH−VIL) 0.55×(VIH−VIL) V High-level output current, IOH −12 mA Low level output current I 12 V Low-level output current, IOL SDATA 3 mA Input slew rate, SR (see Figure 8) 1 4 V/ns SSC modulation frequency 30 33.3 kHz SSC clock input frequency deviation 0 −0.50 kHz Operating free-air temperature, TA −40 85 °C NOTES: 4. Unused inputs must be held high or low to prevent them from floating. 5. All devices on the serial interface bus, with input levels related to VDDI, must have one common supply line to which the pullup resistor is connected to. 6. DC input signal voltage specifies the allowable dc execution of differential input. 7. Differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 8. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing.

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input voltage All inputs VDDQ = 2.3 V, II = –18 mA –1.2 V V High level output voltage VDDQ = min to max, IOH = –1 mA VDDQ – 0.1 VVOH High-level output voltage VDDQ = 2.3 V, IOH = –12 mA 1.7 V Lll t t VDDQ = min to max, IOL = 1 mA 0.1 VOL Low-level output voltage VDDQ = 2.3 V, IOL = 12 mA 0.6 VVOL voltage SDATA VDDI = 3.0 V, IOL = 3 mA 0.4 V IOH High-level output current VDDQ = 2.3 V, VO = 1 V –18 –32 mA IOL Low-level output current VDDQ = 2.3 V, VO = 1.2 V 26 35 mA VO Output voltage swing For load condition see Figure 3 1.1 VDDQ – 0.4 V VOX Output differential cross voltage VDDQ/2 − 0.2 VDDQ/2 VDDQ/2 + 0.2 V II Input current SDATA, SCLK VDDQ = 3.6 V, VI = 0 V to 3.6 V +10/−50 μA II Input current CLK, FBIN VDDQ = 2.7 V, VI = 0 V to 2.7 V ±10 μA IOZ High-impedance-state output current VDDQ = 2.7 V, VO = VDDQ or GND ±10 μA IDDPD Power-down current on VDDQ + AVDD CLK at 0 MHz; Σ of IDD and AIDD 150 250 μA IDDPD Power down current on VDDI CLK at 0 MHz; VDDQ = 3.6 V 3 20 μA IDD Dynamic current on VDDQ VDDQ = 2.7 V, f O = 100 MHz All differential output pairs are terminated with 120 Ω / CL = 4 pF 205 230 mA AI(DD) Supply current on AVDD AVDD = 2.7 V, fO = 100 MHz 4 6 mA IDDI Supply current on VDDI VDDI = 3.6 V SCLK and SDATA = 3.6 V 1 2 mA CI Input capacitance VDDQ = 2.5 V VI = VDDQ or GND 2 2.5 3 pF CO Output capacitance VDDQ = 2.5 V VO = VDDQ or GND 2.5 3 3.5 pF † All typical values are at respective nominal VDDQ. ‡ The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input signal voltage and VCP is the complementary input signal voltage (see Figure 3).

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013

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timing requirements over recommended ranges of s upply voltage and operating free-air temperature MIN MAX UNIT f(CLK) Clock frequency 60 140 MHz Input clock duty cycle 40% 60% Stabilization time† 10 μs † Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. timing requirements for the 2-line serial interface over recommended ranges of operating free-air temperature and VDDI from 3.3 V to 3.6 V (see Figure 10) MIN MAX UNIT f(SCLK) SCLK frequency 100 kHz t(BUS) Bus free time 4.7 μs tsu(START) START setup time† 4.7 μs th(START) START hold time† 4.0 μs tw(SCLL) SCLK low pulse duration 4.7 μs tw(SCLH) SLCK high pulse duration 4.0 μs tr(SDATA) SDATA input rise time 1000 ns tf(SDATA) SDATA input fall time 300 ns tsu(SDATA) SDATA setup time 250 ns th(SDATA) SDATA hold time 0 ns tsu(STOP) STOP setup time 4 μs † This conforms to I2C specification, version 2.1.

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended ranges of operating free-air temperature (unless otherwisw noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tpd Propagation delay time Test mode/CLK to any output 4 ns tPHL High-to low-level propagation delay time SCLK to SDATA (acknowledge) 500/C0123 ns ten Output enable time Test mode/SDATA to Y-output 85 ns tdis Output disable time Test mode/SDATA to Y-output 35 ns tjit(per) Jitter (period), See Figure 6 100/133 MHz −30 30 ps tjit(cc) Jitter (cycle-to-cycle), See Figure 3 100/133 MHz −30 30 ps tjit(hper) Half-period jitter, See Figure 7 100/133 MHz −75 75 ps 100 MHz/VID on CLK = 0.71 V/C0125 −120 120 0°C to 85°C 100 MHz/VID on CLK = 0.59 V/C0119 −50 160 ps0°C to 85°C 100 MHz/VID on CLK = 0.82 V/C0087 −170 70 ps t Static phase offset See Figure 4a 133 MHz/VID on CLK = 0.71 V/C0087 −50 180 t(∅) Static phase offset, See Figure 4a 100 MHz/VID on CLK = 0.71 V/C0125 −160 80 40°C to 85°C 100 MHz/VID on CLK = 0.59 V/C0119 −90 120 ps−40°C to 85°C 100 MHz/VID on CLK = 0.82 V/C0087 −210 30 ps 133 MHz/VID on CLK = 0.71 V/C0087 −80 150 Dynamic phase offset, SSC on, See Figure 4b and 100 MHz/VID on CLK = 0.71 V/C0125 −190 190 ps td # Dynamic phase offset, SSC on, See Figure 4b and Figure 9 133 MHz/VID on CLK = 0.71 V/C0125 −140 140 ps td(∅)# Dynamic phase offset SSC off See Figure 4b 100 MHz/VID on CLK = 0.71 V/C0125 −160 160 ps Dynamic phase offset, SSC off, See Figure 4b 133 MHz/VID on CLK = 0.71 V/C0125 −130 130 ps tslr(o) Output clock slew rate, terminated with 120Ω/14 pF, See Figures 1 and 8 1 2 V/ns tslr(o) Output clock slew rate, terminated with 120Ω/4 pF, See Figures 1 and 8 1 3 V/ns tsk(o)⏐⏐ Output skew, See Figure 5 75 ps SSC modulation frequency 30 33.3 kHz SSC clock input frequency deviation 0.00 −0.50 % † This time is for a PLL frequency of 100 MHz. ‡ According CK00 spec: 6 x Iref at 50 Ω and Rref = 475 Ω § According CK00 spec: 5 x Iref at 50 Ω and Rref = 475 Ω ¶ According CK00 spec: 7 x Iref at 50 Ω and Rref = 475 Ω # The parameter is assured by design but cannot be 100% production tested. || All differential output pins are terminated with 120 Ω/4 pF

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013

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2-line serial interface slave address A7 A6 A5 A4 A3 A2 A1 R/W 1 1 0 1 0 0 1 0 Writing to the device is accomplished by sequentially sending the device address D2 H, the dummy bytes (command code and the number of bytes), and the data bytes. This sequence is illustrated in the following tables: Start Bit Slave Address R/W Ack Ack Command Code Byte Count = N Ack Data Byte 0 Ack Data Byte 1 Ack Data Byte N Ack Stop 1 bit 1 bit 1 bit 7 bits 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit 8 bits 1 bit 2-line serial interface configuration command bitmap The 2-line serial command bytes are used to control the output clock pairs (Y[0:9], Y[0:9]). The output clock pairs are enabled after power up. During normal operation, the clock pairs can be disabled (set Hi-Z) or enabled (running) by writing the corresponding bit to the data bytes in the following tables: Byte 0: Enable/Disable Register (H = Enable, L = Disable) Byte 1: Enable/Disable Register (H = Enable, L = Disable) BIT PINS INITIAL VALUE DESCRIPTION BIT PINS INITIAL VALUE 7 3, 2 H Y0, Y0 7 29, 30 H Y8, Y8 6 5, 6 H Y1, Y1 6 27, 26 H Y9, Y9 5 10, 9 H Y2, Y2 5 − L Reserved 4 20, 19 H Y3, Y3 4 − L Reserved 3 22, 23 H Y4, Y4 3 − L Reserved 2 46, 47 H Y5, Y5 2 − L Reserved 1 44, 43 H Y6, Y6 1 − L Reserved 0 39, 40 H Y7, Y7 0 − L Reserved

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Figure 4. Static Phase Offset Figure 5. Output Skew

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Figure 8. Input and Output Slew Rates Figure 9. SSC Modulation Profile

0.7 VCC

0.3 VCC

NOTE A: The repeat start condition is supported. If PWRDWN# is asserted SDATA will be set to off-state, high impedance. Figure 10. Propagation Delay Times, tr and tf

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013

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48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°−/hairline 8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: B. All linear dimensions are in millimeters. C. This drawing is subject to change without notice. D. Body dimensions do not include mold protrusion not to exceed 0,15. E. Falls within JEDEC MO-153

www.ti.com 17-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples CDCV850DGG ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCV850 CDCV850DGGG4 ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCV850 CDCV850DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCV850 CDCV850DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCV850 CDCV850IDGG NRND TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCV850-I CDCV850IDGGG4 NRND TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCV850-I CDCV850IDGGR OBSOLETE TSSOP DGG 48 TBD Call TI Call TI -40 to 85 CDCV850-I CDCV850IDGGRG4 OBSOLETE TSSOP DGG 48 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

www.ti.com 17-Apr-2013 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCV850DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 2

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97 0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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