CDCV304PWR.A

CDCV304 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 18

Technical content

Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CDCV304 SCAS643I – SEPTEMBER 2000– REVISED OCTOBER 2017 CDCV304200-MHzGeneral-PurposeClockBuffer,PCI-XCompliant

1 Features

1• General-Purpose and PCI-X 1:4 Clock Buffer

• Operating Frequency – 0 MHz to 200 MHz General-Purpose
• Low Output Skew: <100 ps
• Distributes One Clock Input to One Bank of Four Outputs
• Output Enable Control that Drives Outputs Low when OE is Low
• Operates from Single 3.3-V Supply or 2.5-V Supply
• PCI-X Compliant
• 8-Pin TSSOP Package

2 Description

The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X specifications. The CDCV304 is characterized for operation from –40°C to 85°C for automotive and industrial applications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CDCV304 TSSOP (8) 3.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Functional Block Diagram

SCAS643I – SEPTEMBER 2000– REVISED OCTOBER 2017 www.ti.com Product Folder Links: CDCV304 Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated Table of Contents

9 Mechanical, Packaging, and Orderable

3 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (February 2011) to Revision I Page Changes from Revision G (January 2011) to Revision H Page Changes from Revision F (April 2009) to Revision G Page

• Added ψ JT and ψ JB specs to the Thermal Information Table and changed RθJB and RθJC specs from 65 and 69 °C/W

www.ti.com SCAS643I – SEPTEMBER 2000– REVISED OCTOBER 2017 Product Folder Links: CDCV304 Submit Documentation FeedbackCopyright © 2000–2017, Texas Instruments Incorporated

4 Pin Configuration and Functions

NAME NO. 1Y[0:3] 3, 5, 7, 8 O Buffered output clocks CLKIN 1 I Input reference frequency GND 4 Power Ground OE 2 I Output enable control VDD 6 Power Supply (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) This value is limited to 4.6 V maximum.

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage range, VDD –0.5 4.3 V Input voltage range, VI Output voltage range, VO Input clamp current, IIK (VI < 0 or VI> VDD) –50 50 mA Output clamp current, IOK (VO < 0 or VO > VDD) –50 50 mA Continuous total output current, IO (VO = 0 to VDD) –50 50 mA Package thermal impedance, θJA: PW package 230.5 °C/W Junction temperature, Tj, max 125 °C Storage temperature range Tstg –65 150 °C

SCAS643I – SEPTEMBER 2000– REVISED OCTOBER 2017 www.ti.com Product Folder Links: CDCV304 Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated

5.2 Recommended Operating Conditions

Supply voltage, VDD 2.3 3.6 V Low-level input voltage, VIL 0.3 x VDD V High-level input voltage, VIH 0.7 x VDD V Input voltage, VI 0 VDD V High-level output current, IOH VDD = 2.5 V –12 mA VDD = 3.3 V –24 Low-level output current, IOL VDD = 2.5 V 12 mA VDD = 3.3 V 24 Operating free-air temperature, TA –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.3 Thermal Information

THERMAL METRIC(1) THERMAL AIR FLOW (CFM) CDCV304 UNITPW (TSSOP)

8 PINS

RθJA Junction-to-ambient thermal resistance High K 0 149 °C/W 150 142 250 138 500 132 Low K 230 185 170 150 RθJC(top) Junction-to-case (top) thermal resistance 43.7 RθJB Junction-to-board thermal resistance 102 ψJT Junction-to-top characterization parameter 1.8 ψJB Junction-to-board characterization parameter 100.2 (1) All typical values are with respect to nominal VDD and TA = 25°C.

5.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIK Input voltage VDD = 3 V, II = –18 mA –1.2 V VOH High-level output voltage VDD = 2.3 V, IOH = –8 mA 1.8 V VDD = 2.3 V, IOH = –16 mA 1.5 VDD = min to max, IOH = –1 mA VDD – 0.2 VDD = 3 V, IOH = –24 mA 2 VDD = 3 V, IOH = –12 mA 2.4 VOL Low-level output voltage VDD = 2.3 V, IOL = 8 mA 0.5 V VDD = 2.3 V, IOL = 16 mA 0.7 VDD = min to max, IOL = 1 mA 0.2 VDD = 3 V, IOL = 24 mA 0.8 VDD = 3 V, IOL = 12 mA 0.55 IOH High-level output current VDD = 3 V, VO = 1 V –50 mA VDD = 3.3 V, VO = 1.65 V –55 IOL Low-level output current VDD = 3 V, VO = 2 V 60 mA VDD = 3.3 V, VO = 1.65 V 70

www.ti.com SCAS643I – SEPTEMBER 2000– REVISED OCTOBER 2017 Product Folder Links: CDCV304 Submit Documentation FeedbackCopyright © 2000–2017, Texas Instruments Incorporated Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT II Input current VI = VO or VDD ±5 μA IDD Dynamic current, see Figure 1 f = 67 MHz, VDD = 2.7 V 28 mA f = 67 MHz, VDD = 3.6 V 37 CI Input capacitance VDD = 3.3 V, VI = 0 V or VDD 3 pF CO Output capacitance VDD = 3.3 V, VI = 0 V or VDD 3.2 pF

5.5 Timing Requirements

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fclk Clock frequency 0 200 MHz (1) All typical values are with respect to nominal VDD. (2) The tsk(o) specification is only valid for equal loading of all outputs. 5.6 Switching Characteristics: VDD = 2.5 V ± 10% VDD = 2.5 V ± 10%, CL= 10 pF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH Low-to-high propagation delay See Figure 4 and Figure 5 2 2.9 4.5 ns tPHL High-to-low propagation delay 2 3 4.5 tsk(o) Output skew(2) See Figure 6 50 150 ps tr Output rise slew rate 1.5 2.2 4 V/ns tf Output fall slew rate 1.5 2.2 4 V/ns (1) All typical values are with respect to nominal VDD. (2) The tsk(o) specification is only valid for equal loading of all outputs. (3) This symbol is according to PCI-X terminology. 5.7 Switching Characteristics: VDD = 3.3 V ± 10% VDD = 3.3 V ± 10%, CL= 10 pF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH Low-to-high propagation delay See Figure 4 and Figure 5 1.8 2.4 3 ns tPHL High-to-low propagation delay 1.8 2.5 3 tsk(o) Output skew(2) 50 100 ps tjitter Additive phase jitter from input to output 1Y0 12 kHz to 5 MHz, fout = 30.72 MHz 63 fs rms 12 kHz to 20 MHz, fout = 125 MHz 56 tsk(p) Pulse skew VIH = VDD, VIL = 0 V 150 ps tsk(pr) Process skew 0.2 0.3 ns tsk(pp) Part-to-part skew 0.25 0.4 ns thigh Clock high time, see Figure 7

66 MHz 6

140 MHz 3

tlow Clock low time, see Figure 7 tr Output rise slew rate(3) VO = 0.4 V to 2 V 1.5 2.7 4 V/ns tf Output fall slew rate(3) VO = 2 V to 0.4 V 1.5 2.7 4 V/ns

5.8 Typical Characteristics

Figure 1. Supply Current vs Frequency Figure 2. High-Level Output Voltage vs High-Level Output Figure 3. Low-Level Output Voltage vs Low-Level Output Current

0.4 VDD

0.2 VDD

0.6 VDD

0.5 VDD

0.35 VDD

6 Parameter Measurement Information

Figure 4. Test Load Circuit Figure 5. Voltage Waveforms Propagation Delay (tpd) Measurements Figure 6. Output Skew A. All parameters in Figure 7 are according to PCI-X 1.0 specifications. Figure 7. Clock Waveform

7 Detailed Description

7.1 Functional Block Diagram

7.2 Device Functional Modes

Table 1. Function Table

www.ti.com SCAS643I – SEPTEMBER 2000– REVISED OCTOBER 2017 Product Folder Links: CDCV304 Submit Documentation FeedbackCopyright © 2000–2017, Texas Instruments Incorporated

8 Device and Documentation Support

8.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

8.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

8.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDCV304PW Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 CDCV304PW.A Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 CDCV304PWG4 Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 CDCV304PWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 CDCV304PWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 CDCV304PWRG4 Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 23-May-2025 OTHER QUALIFIED VERSIONS OF CDCV304 :

• Enhanced Product : CDCV304-EP NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCV304PWR TSSOP PW 8 2000 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CDCV304PW PW TSSOP 8 150 530 10.2 3600 3.5 CDCV304PW.A PW TSSOP 8 150 530 10.2 3600 3.5 CDCV304PWG4 PW TSSOP 8 150 530 10.2 3600 3.5 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated