CDCU877 TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 17
Technical content
/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0047/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0065 /C0049/C0046/C0056/C0262/C0086 /C0080/C0072/C0065/C0083/C0069 /C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00681.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications /C0068Spread Spectrum Clock Compatible /C0068Operating Frequency: 10 MHz to 400 MHz /C0068Low Current Consumption: <135 mA /C0068Low Jitter (Cycle-Cycle): ±30 ps /C0068Low Output Skew: 35 ps /C0068Low Period Jitter: ±20 ps /C0068Low Dynamic Phase Offset:: ±15 ps /C0068Low Static Phase Offset:: ±50 ps /C0068Distributes One Differential Clock Input to Ten Differential Outputs /C006852-Ball µBGA (MicroStar Junior BGA, 0,65-mm pitch) and 40-Pin MLF /C0068External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clocks /C0068Single-Ended Input and Single-Ended Output Modes /C0068Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300 /C0068Fail-Safe Inputs
description
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT ). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD ). When OE is low, the clock outputs, except FBOUT/FBOUT , are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD . When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN ) and the clock input pair (CK, CK) within the specified stabilization time. The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from –40°C to 85°C. AVAILABLE OPTIONS TA 52-Ball BGA 40-Pin MLF −40°C to 85°C CDCU877ZQL (Pb-Free) CDCU877RTB −40°C to 85°C CDCU877AZQL (Pb-Free) CDCU877ARTB −40°C to 85°C CDCU877GQL −40°C to 85°C CDCU877AGQL Copyright 2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments.
/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0047/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0065 /C0049/C0046/C0056/C0262/C0086 /C0080/C0072/C0065/C0083/C0069 /C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS688A − JUNE 2003 − REVISED JANUARY 2004
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A B C D E F 321 G H CK NB NB NB NB NB NB MicroStar Junior (GQL) Package (TOP VIEW) J K NB CK AGND AV DD GND GND VDDQ VDDQ VDDQ VDDQ GND GND GND GND OS FBIN VDDQ FBIN OE FBOUT VDDQ FBOUT GND GND NC − No Connection NB − No Ball GND GND VDDQ VDDQ NB VDDQ VDDQ GND GND 40-pin HP-VFQFP-N (6,0 x 6,0 mm Body Size, 0,5 mm Pitch, M0#220, Variation VJJD-2, E2 = D2 = 2,9 mm ± 0,15 mm) Package Pinouts RTB PACKAGE (TOP VIEW) 37 36 35 34 33 11 12 VDDQ FBIN FBIN FBOUT FBOUT V DDQ OE OS VDDQ CK CK VDDQ AGND AV DD VDDQ GND 38 32 13 14 15 16 17Y3 40 39 19 20 Y3 Y1 VDDQ VDDQ VDDQ VDDQ GND
Table 1. Terminal Functions
10 Ground
Table 2. Function Table
1.8 V Nominal L H L H LZ LZ L H On
1.8 V Nominal L L H L LZ
1.8 V Nominal H X L H L H L H On
1.8 V Nominal H X H L H L H L On
1.8 V Nominal X X L L LZ LZ LZ LZ Off
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 1. Logic Diagram (Positive Logic)
/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0047/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0065 /C0049/C0046/C0056/C0262/C0086 /C0080/C0072/C0065/C0083/C0069 /C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed 2. This value is limited to 2.5 V maximum. recommended operating conditions MIN NOM MAX UNIT VDDQ Output supply voltage 1.7 1.8 1.9 V AV DD Supply voltage See Note 1 VDDQ VIL Low-level input voltage (see Note 2)OE, OS 0.35 × VDDQ V VIH High-level input voltage (see Note 2)CK, CK 0.65 × VDDQ V IOH High-level output current (see Figure 2) −9 mA IOL Low-level output current (see Figure 2) 9 mA VIX Input differential-pair cross voltage (VDDQ /2)−0.15 (VDDQ /2)+0.15 V VI Input voltage level −0.3 VDDQ +0.3 V VID Input differential voltage (see Note 2 and Figure 9) DC 0.3 VDDQ +0.4 VVID Input differential voltage (see Note 2 and Figure 9) AC 0.6 VDDQ +0.4 V TA Operating free-air temperature −40 85 °C NOTES: 1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are ensured. 2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK VIH and VIL limits define the dc low and high levels for the logic detect state.
/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0047/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0065 /C0049/C0046/C0056/C0262/C0086 /C0080/C0072/C0065/C0083/C0069 /C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS688A − JUNE 2003 − REVISED JANUARY 2004
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS AV DD , VDDQ MIN TYP MAX UNIT VIK Input (cl inputs) II = 18 mA 1.7 V −1.2 V VOH High-level output voltage IOH = −100 µA 1.7 V to 1.9 V VDDQ − 0.2 VVOH High-level output voltage IOH = −9 mA 1.7 V 1.1 V VOL Low-level output voltage IOL = 100 µA 0.1 VVOL Low-level output voltage IOL = 9 mA 1.7 V 0.6 V IO(DL) Low-level output current, disabled VO(DL) = 100 mV, OE = L 1.7 V 100 µA VOD Differential output voltage (see Note 1) 1.7 V 0.5 V CK, CK 1.9 V ±250 II Input current OE, OS, FBIN, FBIN 1.9 V ±10 µA IDD(LD) Supply current, static (IDDQ + IADD ) CK and CK = L 1.9 V 500 µA IDD Supply current, dynamic (IDDQ + IADD ) (see Note 2 for CPD calculation) CK and CK = 270 MHz, All outputs are open (not connected to a PCB)
1.9 V 135
(see Note 2 for CPD calculation) All outputs are loaded with 2 pF and 120-Ω termination resistor 1.9 V 235 mA C I Input capacitance CK, CK VI = VDD or GND 1.8 V 2 3 pFC I Input capacitance FBIN, FBIN VI = VDD or GND 1.8 V 2 3 pF C I ) Change in input current CK, CK VI = VDD or GND 1.8 V 0.25 pFC I(∆) Change in input current FBIN, FBIN VI = VDD or GND 1.8 V 0.25 pF NOTES: 1. V OD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition. 2. Total IDD = IDDQ + IADD = fCK × CPD × VDDQ , solving for CPD = (IDDQ + IADD )/(fCK × VDDQ ) where fCK is the input frequency, VDDQ is the power supply, and CPD is the power dissipation capacitance. timing requirements over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fCK Clock frequency (operating, see Notes 1 and 2)AV DD , VDD = 1.8 V ±0.1 V 10 400 MHz fCK Clock frequency (application, see Notes 1 and 3)AV DD , VDD = 1.8 V ±0.1 V 160 340 MHz tDC Duty cycle, input clock AV DD , VDD = 1.8 V ±0.1 V 40% 60% tL Stabilization time (see Note 4) AV DD , VDD = 1.8 V ±0.1 V 12 µs NOTES: 1. The PLL must be able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle.
/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0047/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0065 /C0049/C0046/C0056/C0262/C0086 /C0080/C0072/C0065/C0083/C0069 /C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Note 1) AV DD , VDD = 1.8 V ±0.1 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ten Enable time, OE to any Y/Y See Figure 11 8 ns tdis Disable time, OE to any Y/Y See Figure 11 8 ns tjit(cc+)Cycle-to-cycle period jitter (see Note 8)160 MHz to 190 MHz, see Figure 4 0 40 pstjit(cc−) Cycle-to-cycle period jitter (see Note 8)160 MHz to 190 MHz, see Figure 4 0 −40 ps tjit(cc+)Cycle-to-cycle period jitter (see Note 8)190 MHz to 340 MHz, see Figure 4 0 30 pstjit(cc−) Cycle-to-cycle period jitter (see Note 8)190 MHz to 340 MHz, see Figure 4 0 −30 ps t(ϕ) Static phase offset time (see Note 2)See Figure 5 −50 50 ps t(ϕ)dyn Dynamic phase offset time See Figure 10 −15 15 ps tsk(o) Output clock skew See Figure 6 35 ps tjit(per)Period jitter (see Notes 3 and 8)
160 MHz to 190 MHz, see Figure 7 −30 30 ps
tjit(per) Period jitter (see Notes 3 and 8) 190 MHz to 340 MHz, see Figure 7 −20 20 ps
160 MHz to 190 MHz, see Figure 8 −115 115 ps
tjit(hper)Half-period jitter (see Notes 3 and 8)
190 MHz to 250 MHz, see Figure 8 −70 70 ps
tjit(hper) Half-period jitter (see Notes 3 and 8)250 MHz to 300 MHz, see Figure 8 −40 40 ps
300 MHz to 340 MHz, see Figure 8 −60 60 ps
Slew rate, OE See Figure 3 and Figure 9 0.5 V/ns SR Input clock skew rate See Figure 3 and Figure 9 1 2.5 4 V/nsSR Output clock slew rate (see Notes 4 and 5) See Figure 3 and Figure 9 1.5 2.5 3 V/ns VOX Output differential-pair cross voltage See Figure 2, CDCU877 (VDDQ /2) − 0.1 (VDDQ /2) + 0.1 VVOX Output differential-pair cross voltage (see Note 6) See Figure 2, CDCU877A (see Note 7) (0−85°C) (VDDQ /2) − 0.1 (VDDQ /2) + 0.1 V SSC modulation frequency 30 33 kHz SSC clock input frequency deviation 0% −0.5% PLL loop bandwidth 2 MHz NOTES: 1. There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables must be used. 2. Phase static offset time does not include jitter. 3. Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. 4. The output slew rate is determined from the IBIS model into the load shown in Figure 3. 5. To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. 6. Output differential-pair cross voltage specified at the DRAM clock input or the test load. 7. VOX of CDCU877A is on average 30 mV lower than that of CDCU877 for the same application. 8. This parameter is assured by design and characterization.
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 2. Output Load Test Circuit 1 Figure 3. Output Load Test Circuit 2 Figure 4. Cycle-To-Cycle Period Jitter
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 7. Period Jitter Figure 8. Half-Period Jitter
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1 Ohm
Figure 12. Recommended AVDD Filtering NOTES: 9. Place the 2200-pF capacitor close to the PLL.
- Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND
via (farthest from the PLL).
- Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz).
/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0047/C0067/C0068/C0067/C0085/C0056/C0055/C0055/C0065 /C0049/C0046/C0056/C0262/C0086 /C0080/C0072/C0065/C0083/C0069 /C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB), the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report, Quad Flatpack No-Lead Packages, Texas Instruments Literature No. SCBA017. This document is available at www.ti.com. The exposed thermal pad dimensions for this package are shown in the following illustration.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCU877AGQLR ACTIVE VFBGA GQL 52 1000 None Call TI Level-3-235C-168 HR CDCU877AGQLT ACTIVE VFBGA GQL 52 250 None Call TI Level-3-235C-168 HR CDCU877ARTBR ACTIVE QFN RTB 40 2500 None CU SNPB Level-3-235C-168 HR CDCU877ARTBT ACTIVE QFN RTB 40 250 None CU SNPB Level-3-235C-168 HR CDCU877AZQLR ACTIVE VFBGA ZQL 52 1000 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR CDCU877AZQLT ACTIVE VFBGA ZQL 52 250 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR CDCU877GQLR ACTIVE VFBGA GQL 52 1000 None Call TI Level-3-235C-168 HR CDCU877GQLT ACTIVE VFBGA GQL 52 250 None Call TI Level-3-235C-168 HR CDCU877RTBR ACTIVE QFN RTB 40 2500 None CU SNPB Level-3-235C-168 HR CDCU877RTBT ACTIVE QFN RTB 40 250 None CU SNPB Level-3-235C-168 HR CDCU877ZQLR ACTIVE VFBGA ZQL 52 1000 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR CDCU877ZQLT ACTIVE VFBGA ZQL 52 250 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2005 Addendum-Page 1
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated