CDCU877AGQL

CDCU877A TI | Alldatasheet

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1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 Low Static Phase Offset: ps 1.8-V Phase Lock Loop Clock Driver for Distributes One Differential Clock Input to Ten Double Data Rate (DDR II)

Applications

μ BGA MicroStar Junior BGA, 0,65-mm pitch) and 40-Pin MLF Operating Frequency: MHz to 400 MHz External Feedback Pins (FBIN, FBIN are Used Low Current Consumption: <135 mA to Synchronize the Outputs to the Input Low Jitter (Cycle-Cycle): ps Clocks Low Output Skew: ps Meets or Exceeds JESD82-8 PLL Standard for Low Period Jitter: ps PC2-3200/4300 Low Dynamic Phase Offset: ps Fail-Safe Inputs The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK to ten differential pairs of clock outputs (Yn, Yn and to one differential pair of feedback clock outputs (FBOUT, FBOUT The clock outputs are controlled by the input clocks (CK, CK the feedback clocks (FBIN, FBIN the LVCMOS control pins (OE, OS), and the analog power input (AV DD When OE is low, the clock outputs, except FBOUT/ FBOUT are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or V DD When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/ they are free running. When AV DD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN and the clock input pair (CK, CK within the specified stabilization time. The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from C to ORDERING INFORMATION T A 52-BALL BGA (1) 40-Pin MLF CDCU877ZQL CDCU877RHA CDCU877AZQL CDCU877ARHA -40 C to C CDCU877GQL CDCU877RTB CDCU877AGQL CDCU877ARTB (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. MicroStar is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2005 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com A B C D E F 321 G H CK NB NB NB NB NB NB J K NB Y1 Y0 Y5 CK AGND A VDD GND GND GND GND GND GND OS FBIN V DDQ FBIN OE FBOUT VDDQ FBOUT GND GND Y3 Y4 Y4 Y9 Y9 Y8 Y0 Y5GND GND NB VDDQ VDDQ GND GND VDDQVDDQ VDDQ VDDQ VDDQ VDDQ 37 36 35 34 33 1 1 12 V DDQ FBIN FBIN FBOUT FBOUT V DDQ OE OS V DDQ CK CK VDDQ AGND A VDD VDDQ GND 38 32 13 14 15 16 17 Y3Y4 Y4 Y9 Y0 Y0Y5 Y6 Y6 40 39 19 20 Y8Y9Y3 Y1 Y5Y1 VDDQVDDQ VDDQVDDQ GND CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. MicroStar Junior (ZQL) Package (TOP VIEW) NC No Connection NB No Ball RHA/RTB Package (MLF PAckage (TOP VIEW) 40-pin HP-VFQFP-N (6,0 x 6,0 mm Body Size, 0,5 mm Pitch, M0#220, Variation VJJD-2, 2,9 mm 0,15 mm) Package Pinouts Submit Documentation Feedback

www.ti.com CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 TERMINAL FUNCTIONS TERMINAL I/O I Clock input with a (10 k Ω to 100 k Ω pulldown resistor Complementary clock input with a (10 k Ω to 100 k Ω pulldown CK I resistor FBIN I Feedback clock input FBIN I Complementary feedback clock input FBOUT O Feedback clock output FBOUT O Complementary feedback clock output OE I Output enable (asynchronous) OS I Output select (tied to GND or V DD B2, B3, B4, B5, GND C2, C5, H2, H5, Ground J2, J3, J4, D2, D3, D4, E2, 15, 20, 23, V DDQ E5, F2, G2, G3, Logic and output power 28, 31, G4, A2, A1, D1, J1, K3, 11, 14, 16, 19, Y[0:9] O Clock outputs A5, A6, D6, J6, 29, 33, 34, 38, A3, B1, C1, K1, 12, 13, 18, 17, Y[0:9] K2, A4, B6, C6, O Complementary clock outputs 30, 32, 35, 37, K6, FUNCTION TABLE INPUTS OUTPUTS AVDD OE OS CK CK Y Y FBOUT FBOUT PLL GND H X L H L H L H Bypassed/Off GND H X H L H L H L Bypassed/Off GND L H L H L Z L Z L H Bypassed/Off L Z L Z GND L L H L H L Bypassed/Off Active Active 1.8 V Nominal L H L H L Z L Z L H On L Z L Z 1.8 V Nominal L L H L H L On Active Active 1.8 V Nominal H X L H L H L H On 1.8 V Nominal H X H L H L H L On 1.8 V Nominal X X L L L Z L Z L Z L Z Off X X X H H Reserved Submit Documentation Feedback

www.ti.com CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 Figure LOGIC DIAGRAM (POSITIVE LOGIC) Submit Documentation Feedback

www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range V DDQ or AV DD 0.5 2.5 V V I Input voltage range (2) (3) 0.5 V DDQ 0.5 V V O Output voltage range (2) (3) 0.5 V DDQ 0.5 V I IK Input clamp current V I or V I V DDQ mA I OK Output clamp current V O or V O V DDQ mA I O Continuous output current V O to V DDQ mA Continuous current through each V DDQ or GND 100 mA T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) This value is limited to 2.5 V maximum. MIN NOM MAX UNIT Output supply voltage, V DDQ 1.7 1.8 1.9 V V CC Supply Voltage, AV DD (1) V DDQ V V IL Low-level input voltage (2) OE, OS 0.35 x V DDQ V V IH High-level input voltage (2) CK, CK 0.65 x V DDQ V I OH High-level output current (see Figure mA I OL Low-level output current (see Figure mA V IX Input differential-pair cross voltage DDQ /2) 0.15 DDQ /2) 0.15 V V I Input voltage level -0.3 V DDQ 0.3 V DC 0.3 V DDQ 0.4 V Input differential voltage (2) V ID (see Figure AC 0.6 V DDQ 0.4 V T A Operating free-air temperature -40 C (1) The PLL is turned off and bypassed for test purposes when AV DD is grounded. During this test mode, V DDQ remains within the recommended operating conditions and no timing parameters are specified. (2) V ID is the magnitude of the difference between the input level on CK and the input level on CK see Figure for definition. The CK and CK V IH and V IL limits define the dc low and high levels for the logic detect state. Submit Documentation Feedback

www.ti.com Electrical Characteristics Timing Requirements CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 over recommended operating free-air temperature range (unless otherwise noted) AV DD PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT V DDQ V IK Input I I mA 1.7 -1.2 V I OH 100 μ A 1.7 to 1.9 V DDQ 0.2 V OH High-level output voltage V I OH mA 1.7 1.1 I OL 100 μ A 0.1 V OL Low-level output voltage V I OL mA 1.7 0.6 I O(DL) Low-level output current, dissabled V O(DL) 100 mV, OE L 1.7 100 μ A V OD Differential output voltage (1) 1.7 0.5 V CK, CK 1.9 250 I I Input current μ A OE, OS, 1.9 FBIN, FBIN I DD(LD) Supply current, static DDQ I ADD CK and CK L 1.9 500 μ A CK and CK 270 MHz. All outputs are open (not connected 1.9 135 Supply current, dynamic DDQ I ADD to a PCB) I DD mA (see Note (2) for CPD calculation) All outputs are loaded with pF 1.9 235 and 120- Ω termination resistor CK, CK 1.8 C I Input capacitance V I V DD or GND FBIN, FBIN 1.8 pF CK, CK 1.8 0.25 C Δ Change in input current V I V DD or GND FBIN, FBIN 1.8 0.25 (1) V OD is the magnitude of the difference between the true and complimentary outputs. See Figure for a definition. (2) Total I DD I DDQ I ADD f CK C PD V DDQ solving for C PD DDQ I ADD )/(f CK V DDQ where f CK is the input frequency, V DDQ is the power supply, and C PD is the power dissipation capacitance. over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN MAX UNIT Clock frequency (operating) (1) (2) 400 MHz f CK Clock frequency (application) (1) (3) 160 340 MHz AV DD V DD 1.8 V 0.1 V t DC Duty cycle, input clock 40% 60% t L Stabiliztion time (4) μ s (1) The PLL must be able to handle spread spectrum induced skew. (2) Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). (3) Application clock frequency indicates a range over which the PLL must meet all timing parameters. (4) Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Submit Documentation Feedback

www.ti.com Switching Characteristics CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 over recommended operating free-air temperature range (unless otherwise noted) (see (1) AV DD V DD 1.8 V 0.1 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t en Enable time, OE to any Y See Figure ns t dis Disable time, OE to any Y See Figure ns t jit(cc+) Cycle-to-cycle period jitter (2) 160 MHz to 190 MHz, see Figure ps t jit(cc-) -40 t jit(cc+) Cycle-to-cycle period jitter (2) 160 MHz to 340 MHz, see Figure ps t jit(cc-) -30 t ω Static phase offset time (3) See Figure -50 ps t ω )dyn Dynamic phase offset time See Figure -15 ps t sk(o) Output clock skew See Figure ps 160 MHz to 190 MHz, see Figure -30 t jit(per) Period jitter (4) (2) ps 190 MHz to 340 MHz, see Figure -20 160 MHz to 190 MHz, see Figure -115 115 190 MHz to 250 MHz, see Figure -70 t jit(hper) Half-period jitter (4) (2) ps 250 MHz to 300 MHz, see Figure -40 300 MHz to 340 MHz, see Figure -60 Slew rate, OE See Figure and Figure 0.5 SR Input clock slew rate See Figure and Figure 2.5 V/ns Output clock slew rate (5) (6) (no load) See Figure and Figure 1.5 2.5 DDQ /2) DDQ /2) CDCU877, See Figure 0.1 0.1 V OX Output differential-pair cross voltage (7) V CDCU877A (8) See Figure DDQ /2) DDQ /2) 0.1 0.1 SSC modulation frequency kHz SSC clock input frequency deviation -0.5% PLL loop bandwidth MHz (1) There are two different terminations that are used with the following tests. The load/board in Figure is used to measure the input and output differential-pair cross voltage only. The load/board in Figure is used to measure all other tests. For consistency, equal length cables must be used. (2) This parameter is specifieded by design and characterization. (3) Phase static offset time does not include jitter. (4) Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. (5) The output slew rate is determined from the IBIS model with a 120- Ω load only. (6) To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. (7) Output differential-pair cross voltage specified at the DRAM clock input or the test load. (8) V OX of CDCU877A is on average mV lower than that of CDCU877 for the same application. Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION Z□=□60 /c87 L =□2.97” Z□=□60 /c87 L =□2.97” Z□=□120 /c87 C□=□10□pF C□=□10□pF GND GND VDD CU877 VTT VTT SCOPE Note:□VTT =□GND Z□=□60 /c87 L =□2.97” Z□=□60 /c87 L =□2.97” C□=□10□pF C□=□10□pF CU877 R□=□50 /c87 VTT VTT SCOPE Note:□VTT =□GND Z□=□50 /c87 Z□=□50 /c87 R□=□10 /c87 R□=□10 /c87 −V DD/2 −V DD/2 VDD/2 −V DD/2 R□=□50 /c87 tcycle n tcycle n+1 tjit(cc) cycle n cycle n+1=□t − t Yx, FBOUT Yx,□FBOUT CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 Figure Output Load Test Circuit Figure Output Load Test Circuit Figure Cycle-To-Cycle Period Jitter Submit Documentation Feedback

www.ti.com t/c106n+1t/c106n n = N t n1t = N /c106 /c106 /c229 (N□is□the□large□number□of□samples) (N□>□1000□samples) (1) O 1t = t -jit(per) cycle n f (f average□input□frequency□measured□at□CK/O CK (2) CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure Static Phase Offset Figure Output Skew Figure Period Jitter Submit Documentation Feedback

www.ti.com O 1t = t -jit(hper) half period n 2 x f n□=□any□half□cycle (f average□input□frequency□measured□at□CK/O CK (3) Clock□Inputs VID, VOD 80% 20% 80% 20% tr(i) r(o), t and Outputs,□OE tf(i) f(o), t V - V80% 20%slrr =(i/o) tr(i/o) V - V80% 20%slrf =(i/o) tf(i/o) (4) t/c106dyn t/c106dynt/c106dyn t/c106dyn t/c106t/c106 CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure Half-Period Jitter Figure Input and Output Slew Rates Figure 10. Dynamic Phase Offset Submit Documentation Feedback

www.ti.com RECOMMENDED AV DD FILTERING VDDQ GND CARD VIA CARD VIA Bead 0603

4.7 F/c109

0.1 F/c109

2200□pF 0603 A VDD AGND PLL 1 /c87 CDCU877 CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D JUNE 2005 REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 11. Time Delay Between OE and Clock Output (Y, Y Place the 2200-pF capacitor close to the PLL. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND via (farthest from the PLL). Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz). Figure 12. Recommended AV DD Filtering Submit Documentation Feedback

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDCU877ANMKR Active Production NFBGA (NMK) | 52 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ANMKR.A Active Production NFBGA (NMK) | 52 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ANMKT Active Production NFBGA (NMK) | 52 250 | SMALL T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ANMKT.A Active Production NFBGA (NMK) | 52 250 | SMALL T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHAR Active Production VQFN (RHA) | 40 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHAR.A Active Production VQFN (RHA) | 40 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHARG4 Active Production VQFN (RHA) | 40 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHAT Active Production VQFN (RHA) | 40 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHAT.A Active Production VQFN (RHA) | 40 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHATG4.A Active Production VQFN (RHA) | 40 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877RHAR Active Production VQFN (RHA) | 40 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHAR.A Active Production VQFN (RHA) | 40 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHARG4.A Active Production VQFN (RHA) | 40 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHAT Active Production VQFN (RHA) | 40 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHAT.A Active Production VQFN (RHA) | 40 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHATG4 Active Production VQFN (RHA) | 40 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RTBR Active Production VQFN (RHA) | 40 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 1

www.ti.com 23-May-2025 (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCU877ANMKR NFBGA NMK 52 1000 336.6 336.6 28.6 CDCU877ARHAR VQFN RHA 40 2500 356.0 356.0 35.0 CDCU877ARHAT VQFN RHA 40 250 210.0 185.0 35.0 CDCU877RHAR VQFN RHA 40 2500 356.0 356.0 35.0 CDCU877RHAT VQFN RHA 40 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRHA 40 PLASTIC QUAD FLATPACK - NO LEAD6 x 6, 0.5 mm pitch 4225870/A

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 40X 0.3 0.2 2.9 0.1 40X 0.5 0.3

1 MAX

0.05 0.00 36X 0.5 4.5 2X 4.5 (0.1) TYP A 6.1 5.9 B 6.1 5.9 0.3 0.2 0.5 0.3 VQFN - 1 mm max heightRHA0040D PLASTIC QUAD FLATPACK - NO LEAD 4225822/A 03/2020 PIN 1 INDEX AREA 0.08 C SEATING PLANE 10 21 11 20 40 31 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

41 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 2.200 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

40X (0.25) 40X (0.6) ( 0.2) TYP VIA 36X (0.5) (5.8) (5.8) (1.2) TYP ( 2.9) (R0.05) TYP VQFN - 1 mm max heightRHA0040D PLASTIC QUAD FLATPACK - NO LEAD 4225822/A 03/2020 SYMM 11 20 3140 SYMM LAND PATTERN EXAMPLE SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 40X (0.6) 40X (0.25) 36X (0.5) (5.8) (5.8) 4X ( 1.27) (0.735) TYP (0.735) TYP (R0.05) TYP VQFN - 1 mm max heightRHA0040D PLASTIC QUAD FLATPACK - NO LEAD 4225822/A 03/2020 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 41: 76.46% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X SYMM 11 20 3140

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. NanoFree is a trademark of Texas Instruments. PACKAGE OUTLINE 4225135/A 08/2019 www.ti.com NFBGA - 1 mm max height PLASTIC BALL GRID ARRAY NMK0052A A 0.1 C

0.15 C A B

0.05 C B SYMM SYMM 4.6 4.4 7.1 6.9 BALL A1 CORNER 0.25 0.15 SEATING PLANE C 1 2 3 4 5 6 A B C D E F G H J K 5.85 TYP

0.65 TYP

(0.58) TYP (0.63) TYP3.25 TYP BALL TYP 52X Ø0.35 0.25

NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature number SNVA009 (www.ti.com/lit/snva009). EXAMPLE BOARD LAYOUT 4225135/A 08/2019 www.ti.com NFBGA - 1 mm max heightNMK0052A PLASTIC BALL GRID ARRAY SYMM SYMM LAND PATTERN EXAMPLE SCALE: 10X SOLDER MASK DETAILS NOT TO SCALE

0.05 MAX

0.05 MIN

OPENING (Ø0.35) METAL EXPOSED METAL EXPOSED METAL METAL UNDER SOLDER MASK (Ø0.35) SOLDER MASK OPENING (0.65) TYP (0.65) TYP A B C D E F G H J K 1 2 3 4 5 6 NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED 52X (Ø0.35)

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. EXAMPLE STENCIL DESIGN 4225135/A 08/2019 www.ti.com NFBGA - 1 mm max heightNMK0052A PLASTIC BALL GRID ARRAY SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM (0.65) TYP (0.65) TYP A B C D E F G H J K 1 2 3 4 5 6 52X (Ø0.35)

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