CDCU2A877ZQLT

CDCU2A877_V01 TI | Alldatasheet

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1.8-V PHASE LOCK LOOP CLOCK DRIVER 52-Ball mBGA MicroStar Junior BGA, 0,65-mm pitch) 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate DDR II

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FBIN, FBIN are Used to Synchronize the Outputs to the Input Spread Spectrum Clock Compatible Clocks Operating Frequency: 125 MHz to 410 MHz Meets or Exceeds CUA877/CUA878 Application Frequency: 160 MHz to 410 MHz Specification PLL Standard for Low Jitter (Cycle-Cycle): ps PC2-3200/4300/5300/6400 Low Output Skew: ps Fail-Safe Inputs Stabilization Time μ s Distributes One Differential Clock Input to Differential Outputs High-Drive Version of CDCUA877 The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK to differential pairs of clock outputs (Yn, Yn and to one differential pair of feedback clock outputs (FBOUT, FBOUT The clock outputs are controlled by the input clocks (CK, CK the feedback clocks (FBIN, FBIN the LVCMOS control pins (OE, OS), and the analog power input (AV DD When OE is low, the clock outputs, except FBOUT/ FBOUT are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or V DD When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/ they are free running. When AV DD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN and the clock input pair (CK, CK within the specified stabilization time. The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from C to AVAILABLE OPTIONS T A 52-Ball BGA (1) C to C CDCU2A877ZQL (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. MicroStar Junior is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2006 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 Submit Documentation Feedback

www.ti.com CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 Table Terminal Functions NAME BGA MLF I/O I Clock input with a (10 k Ω to 100 k Ω pulldown resistor CK I Complementary clock input with a (10 k Ω to 100 k Ω pulldown resistor FBIN I Feedback clock input FBIN I Complementary feedback clock input FBOUT O Feedback clock output FBOUT O Complementary feedback clock output OE I Output enable (asynchronous) OS I Output select (tied to GND or VDD) GND B2, B3, B4, Ground B5, C2, C5, H2, H5, J2, J3, J4, V DDQ D2, D3, D4, 15, 20, Logic and output power E2, E5, F2, 23, 28, 31, G2, G3, G4, Y[0:9] A2, A1, D1, 38, 39, 11, 14, O Clock outputs J1, K3, A5, A6, 34, 33, 29, 19, D6, J6, Y[0:9] A3, B1, C1, 37, 40, 12, 13, O Complementary clock outputs K1, K2, A4, 35, 32, 30, 18, B6, C6, K6, Table Function Table INPUTS OUTPUTS PLL AV DD OE OS CK CK Y Y FBOUT FBOUT GND H X L H L L H Bypassed/Off GND H X H L H H L Bypassed/Off GND L H L H L Z L Z L H Bypassed/Off GND L L H L LZ LZ H L Bypassed/Off Active Active 1.8 V Nomnal L H L H L Z L Z L H On 1.8 V Nomnal L L H L LZ LZ H L On Active Active 1.8 V Nomnal H X L H L H L H On 1.8 V Nomnal H X H L H L H L On 1.8 V Nomnal X X LH L L Z L Z L Z L Z Off X X X H H Reserved Submit Documentation Feedback

www.ti.com ABSOLUTE MAXIMUM RATINGS CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 Figure Logic Diagram (Positive Logic) over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT V DDQ Supply voltage range 0.5 to 2.5 V A VDD V I Input voltage range (2) (3) 0.5 to V DDQ 0.5 V V O Output voltage range (2) (3) 0.5 to V DDQ 0.5 V I IK Input clamp current, I or V I V DDQ mA I OK Output clamp voltage, O or V O V DDQ mA I O Continuous output current, O to V DDQ mA I DDC Continuous current through each V DDQ or GND 100 mA No airflow 151.9 R θ JA Thermal resistance, junction-to-ambient (4) Airllflow 150 ft/min 146.1 K/W R θ JC Thermal resistance, junction-to-case (4) No airflow 102.4 T stg Storage temperature range to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) This value is limited to 2.5 V maximum. (4) The package thermal impedance is calculated in accordance with JESD51 and JEDEC2S1P (high-k board). Submit Documentation Feedback

www.ti.com RECOMMENDED OPERATING CONDITIONS CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 MIN NOM MAX UNIT V DDQ Output supply voltage 1.7 1.8 1.9 V AV DD Supply voltage (1) V DDQ V IL Low-level input voltage (2) OE, OS,CK, 0.35 V DDQ V CK V IH High-level input voltage (2) OE, OS,CK, 0.65 V DDQ V CK I OH High-level output current (see Figure mA I OL Low-level output current (see Figure mA V IX Input differential-pair cross voltage DDQ /2)-0.15 DDQ /2)+0.15 V V I Input voltage level 0.3 V DDQ +0.3 V DC 0.3 V DDQ +0.4 V V ID Input differential voltage (2) (see Figure AC 0.6 V DDQ +0.4 V T A Operating free-air temperature C (1) The PLL is turned off and bypassed for test purposes when AV DD is grounded. During this test mode, V DDQ remains within the recommended operating conditions and no timing parameters are ensured. (2) V ID is the magnitude of the difference between the input level on CK and the input level on CK see Figure for definition. The CK and CK V IH and V IL limits define the dc low and high levels for the logic detect state. Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS TIMING REQUIREMENTS CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 over recommended operating free-air temperature range AV DD PARAMETERLow-level output voltage TEST CONDITIONS MIN TYP MAX UNIT V DDG V IK Input (cl inputs) I I mA 1.7 V 1.2 V I OH -100 A 1.7 V to VDDQ 1.9 V 0.2 V OH High-level output voltage V I OH mA 1.7 V 1.1 I OL 100 μ A 0.1 V OL Low-level output voltage V I OL mA 1.7 V 0.6 I O(DL) Low-level output current, disabled V O(DL) 100 mV, OE L 1.7 V 100 μ A V OD Differential output voltage (1) 1.7 V 0.6 V CK, CK 1.9 V 250 I I Input current μ A OE, OS, FBIN, FBIN 1.9 V I DD(LD) Supply current, static DDQ I ADD CK and CK L 1.9 V 500 μ A CK and CK 410 MHz, All outputs are open 1.9 V 300 mA (not connected to a PCB) Supply current, dynamic I DDQ I ADD (see (2) I DD for C PD calculation) All outputs are loaded with pF and 120- Ω termination resistor, 1.9 V 325 mA CK and CK 410 MHz CK, CK V I V DD or GND 1.8 V C I Input capacitance pF FBIN, FBIN V I V DD or GND 1.8 V CK, CK V I V DD or GND 1.8 V 0.25 Change in input C Δ pF current FBIN, FBIN V I V DD or GND 1.8 V 0.25 (1) V OD is the magnitude of the difference between the true and complimentary outputs. See Figure for a definition. (2) Total I DD I DDQ I ADD f CK C PD V DDQ solving for C PD DDQ I ADD )/(f CK V DDQ where f CK is the input frequency, V DDQ is the power supply, and C PD is the power dissipation capacitance. over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f CK Clock frequency (operating) (1) (2) AV DD V DD 1.8 V 0.1 V 125 410 MHz f CK Clock frequency (application) (1) (3) AV DD V DD 1.8 V 0.1 V 160 410 MHz t DC Duty cycle, input clock AV DD V DD 1.8 V 0.1 V 40% 60% t L Stabilization time (4) AV DD V DD 1.8 V 0.1 V μ s (1) The PLL must be able to handle spread spectrum induced skew. (2) Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). (3) Application clock frequency indicates a range over which the PLL must meet all timing parameters. (4) Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specified by the static phase offset t φ after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode, and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Submit Documentation Feedback

www.ti.com SWITCHING CHARACTERISTICS CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t en Enable time, OE to any Y See Figure ns t dis Disable time, OE to any Y See Figure ns t jit(cc+) Cycle-to-cycle period jitter (2) 160 MHz to 410 MHz, See Figure ps t jit(cc-) t φ Static phase offset time (3) See Figure ps t φ )dyn Dynamic phase offset time, (4) See Figure ps t sk(o) Output clock skew (4) See Figure ps 160 MHz to 270 MHz, See Figure t jit(per) Period jitter (5) (2) ps 271 MHz to 410 MHz, See Figure 160 MHz to 270 MHz, See Figure t jit(hper) Half-period jitter (5) (2) ps 271 MHz to 410 MHz, See Figure Σ t (su) jit(per) φ )dyn t sk(o) (6) 271 MHz to 410 MHz ps Σ t (h) φ )dyn t sk(o) (6) 271 MHz to 410 MHz ps Slew rate, OE See Figure and Figure 0.5 SR Input clock skew rate See Figure and Figure 2.5 V/ns Output clock slew rate (7) (8) See Figure and Figure 1.5 2.5 V OX Output differential-pair cross voltage (9) See Figure DDQ /2) 0.1 DDQ /2) 0.1 V SSC modulation frequency kHz SSC clock input frequency deviation 0.5% PLL loop bandwidth MHz (1) There are two different terminations that are used with the following tests. The load/board in Figure is used to measure the input and output differential-pair cross voltage only. The load/board in Figure is used to measure all other tests. For consistency, equal length cables must be used. (2) This parameter is assured by design and characterization. (3) Phase static offset time does not include jitter. (4) For full frequency range of 160MHz to 410MHz. (5) Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. (6) In the frequency range of 271 MHz to 410 MHz, the minimum and maximum values of t jit(per) and t φ )dyn and the maximum value for t sk(o) must not exceed the corresponding minimum and maximum values of the 160 MHz to 270 MHz range. In addition, the sum of the specified values for jit(per) φ )dyn and t sk(o) must meet the requirements for the Σ t (su) and the sum of the specified values for φ )dyn and t sk(o) must meet the requirements for the Σ t (h) (7) The output slew rate is determined from the IBIS model into the load shown in Figure (8) To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. (9) Output differential-pair cross voltage specified at the DRAM clock input or the test load. Submit Documentation Feedback

www.ti.com CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 Figure Output Load Test Circuit (Using High-Impedance Probe) Figure Output Load Test Circuit (Using SMA Coaxial Cable) Figure IBIS Model Output Load Submit Documentation Feedback

www.ti.com tc(n) tc(n) tc(n+1) tc(n+1) t( )n t( )n t( )n CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 Figure Cycle-To-Cycle Period Jitter Figure Static Phase Offset Figure Output Skew Submit Documentation Feedback

www.ti.com (n) (n) (half□period)n (half□period)n (half□period)n CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 Figure Period Jitter Figure Half-Period Jitter Figure 10. Input and Output Slew Rates Submit Documentation Feedback

www.ti.com t( ) t( )dyn t( )dyn t( )dyn t( )dyn t( ) CDCU2A877 SCAS827A AUGUST 2006 REVISED JUNE 2007 Figure 11. Dynamic Phase Offset Figure 12. Time Delay Between OE and Clock Output (Y, Y Place the 2200-pF capacitor close to the PLL. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND via (farthest from the PLL). Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz). Figure 13. Recommended AV DD Filtering Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCU2A877ZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 52 1000 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR CDCU2A877ZQLT ACTIVE BGA MI CROSTA R JUNI OR ZQL 52 250 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 22-Nov-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CDCU2A877ZQLR BGA MI CROSTA R JUNI OR CDCU2A877ZQLT BGA MI CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION www.ti.com 21-Apr-2009 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCU2A877ZQLR BGA MICROSTAR JUNIOR ZQL 52 1000 333.2 345.9 28.6 CDCU2A877ZQLT BGA MICROSTAR JUNIOR ZQL 52 250 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 21-Apr-2009 Pack Materials-Page 2

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