CDCS503 TI | Alldatasheet
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Technical content
FEATURES
APPLICATIONS
SSC_SEL 0 SSC_SEL 1 GND V DD OE OUT FS BLOCK DIAGRAM GND OUTIN FS LVCMOS Control Logic OE LV CMOS VDD SSC_SEL 0 SSC_SEL 1 x1□or□x4 /□SSC
DESCRIPTION
www.ti.com SCAS872 MARCH 2009 Clock Buffer/Clock Multiplier With Optional SSC Consumer and Industrial a Family of Easy to use Clock requiring EMI reduction through Spread Generator Devices With Optional SSC Spectrum Clocking and/ or Clock Clock Multiplier With Selectable Output Multiplication Frequency and Selectable SSC SSC Controllable via External Pins 0%, 0.5%, 1%, Center Spread Frequency Multiplication Selectable Between or With One External Control Pin Output Disable via Control Pin Single 3.3V Device Power Supply Wide Temperature Range C to C Low Space Consumption by Pin TSSOP Package The CDCS503 is a spread spectrum capable, LVCMOS Input Clock Buffer with selectable frequency multiplication. It shares major functionality with the CDCS502 but utilizes a LVCMOS input stage instead of the crystal input stage of the CDCS502. Also an Output Enable pin has been added to the CDCS503. The device accepts a 3.3V LVCMOS signal at the input. The input signal is processed by a PLL, whose output frequency is either equal to the input frequency or multiplied by the factor of The PLL is also able to spread the clock signal by 0%, 0.5%, or centered around the output clock frequency with a triangular modulation. By this, the device can generate output frequencies between 8MHz and 108MHz with or without SSC. A separate control pin can be used to enable or disable the output. The CDCS503 operates in 3.3V environment. It is characterized for operation from C to and available in an 8-pin TSSOP package. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SSC_SEL 0 SSC_SEL 1 GND V DD OE OUT FS PACKAGE THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE CDCS503 SCAS872 MARCH 2009 www.ti.com FUNCTION TABLE OE FS SSC_SEL SSC_SEL SSC AMOUNT f OUT IN f OUT at f in MHz x x x x x 3-state 0.00% MHz 0.50% MHz 1.00% MHz 2.00% MHz 0.00% 108 MHz 0.50% 108 MHz 1.00% 108 MHz 2.00% 108 MHz PIN FUNCTIONS SIGNAL PIN TYPE I LVCMOS Clock input OUT O LVCMOS Clock Output SSC_SEL I Spread Selection Pins, internal pull-up OE I Output Enable, internal pull-up FS I Frequency Multiplication Selection, internal pull-up V DD Power 3.3V Power Supply GND Ground Ground over operating free-air temperature range (unless otherwise noted) (1) THERMAL AIRFLOW (CFM) CDCS503PW 8-PIN TSSOP UNIT 150 250 500 High K 149 142 138 132 R θ JA C/W Low K 230 185 170 150 High K R θ JC C/W Low K (1) The package thermal impedance is calculated in accordance with JESD and JEDEC2S2P (high-k board). Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS503
www.ti.com SCAS872 MARCH 2009 over operating free-air temperature range (unless otherwise noted) VALUE UNIT V DD Supply voltage range 0.5 to 4.6 V V IN Input voltage range (1) 0.5 to 4.6 V V out Output voltage range (1) 0.5 to 4.6 V I IN Input current I V I VDD) mA I out Continuous output current mA T ST Storage temperature range to 150 C T J Maximum junction temperature 125 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. MIN NOM MAX UNIT V DD Supply voltage 3.0 3.6 V FS f IN Input frequency MHz FS V IL Low level input voltage LVCMOS 0.3 V DD V V IH High level input voltage LVCMOS 0.7 V DD V V I Input voltage threshold LVCMOS 0.5 V DD V C L Output load test LVCMOS pF I OH OL Output current mA T A Operating free-air temperature -40 C over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f out MHz; FS no SSC IDD Device supply current mA f out MHz; FS SSC FS f OUT Output frequency MHz FS 108 I IH LVCMOS input current V I VDD; VDD 3.6 V µ A I IL LVCMOS input current V I VDD 3.6 V µ A I OH 0.1mA 2.9 V OH LVCMOS high-level output voltage I OH 8mA 2.4 V I OH 12mA 2.2 I OL 0.1mA 0.1 V OL LVCMOS low-level output voltage I OL 8mA 0.5 V I OL 12mA 0.8 I OZ High- impedance-state output current OE Low µ A t JIT(C-C) Cycle to cycle jitter (1) f out 108 MHz; FS 110 ps SSC 1%, 10000 Cycles t r f Rise and fall time (1) 20% 80% 0.75 ns O dc Output duty cycle 45% 55% f MOD Modulation frequency kHz (1) Measured with Test Load, see Figure Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCS503
f -□Input□Frequency□-□MHzi x1□Mode x4□Mode I -□Input□Current□-□mA DD CDCS503 SCAS872 MARCH 2009 www.ti.com Figure IDD vs Input Frequency, VCC 3.3V, SSC 2%, Output Loaded With Test Load Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS503
1□k/c87CDCS503 LVCMOS 1□k/c87 10□pF LVCMOS LVCMOS CDCS503 Typical□Driver Impedance ~□32 /c87 Series Termination ~□18 /c87 Z =□50L /c87 CDCS503 www.ti.com SCAS872 MARCH 2009 The exact implementation of the SSC modulation plays a vital role for the EMI reduction. The CDCS503 uses a triangular modulation scheme implemented in a way that the modulation frequency depends on the VCO frequency of the internal PLL and the spread amount is independent from the VCO frequency. The modulation frequency can be calculated by using one of the below formulas chosen by frequency multiplication mode. FS f mod f IN 708 FS f mod f IN 620 Figure Test Load Figure Load for 50- Ω Board Environment Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCS503
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCS503PWR TSSOP PW 8 2000 356.0 356.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CDCS503PW PW TSSOP 8 150 530 10.2 3600 3.5 CDCS503PW.B PW TSSOP 8 150 530 10.2 3600 3.5 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C TYP6.6 6.2
1.2 MAX
6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8
0.1 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT (5.8)
0.05 MAX
0.05 MIN
8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X
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