CDCS502PWR

CDCS502 TI | Alldatasheet

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SSC _SEL 0 1 8 XOUT SSC _SEL 1 2 7 FSGND 3 6 OUT XIN 4 5 CDCS502 VDD BLOCK DIAGRAM VDD GND OUT XIN Xout SSC_SEL 0 SSC_SEL 1 FS XO Control Logic L V CMOS x1□or□x4 /SSC CDCS502 www.ti.com SCAS868 DECEMBER 2008 Crystal Oscillator Clock Generator with optional SSC Consumer and Industrial a Family of Easy to use Clock requiring Crystal Oscillator with the possibility Generator Devices With Optional SSC of EMI reduction through Spread Spectrum Crystal Oscillator With Integrated Crystal Clocking Capacitors, Selectable Output Frequency and Selectable SSC SSC Controllable via External Pins 0%, 0.5%, 1%, Center Spread Frequency Multiplication Selectable Between or With one External Control Pin Single 3.3V Device Power Supply Wide Temperature Range C to C Low space Consumption by pin TSSOP Package Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DESCRIPTION

SSC _SEL 0 1 8 XOUT SSC _SEL 1 2 7 FSGND 3 6 OUT XIN 4 5 CDCS502 VDD CDCS502 SCAS868 DECEMBER 2008 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The CDCS502 is a spread spectrum capable, fundamental mode crystal oscillator with selectable frequency multiplication. It a built-in load capacitance of 10pF. This oscillator stage accepts crystals from 8MHz to 32MHz with an ESR of up to 180 Ω The stage can be used with crystals with power dissipation of µ W and up. The input signal is processed by a PLL, whose output frequency is either equal to the input frequency or multiplied by the factor of The PLL is also able to spread the clock signal by 0%, 0.5%, or centered around the output clock frequency with an triangular modulation. By this, the device can generate output frequencies between 8MHz and 108MHz with or without SSC from a fundamental mode crystal. In Mode with an SSC amount of 0%, the device works as a standard crystal oscillator and does not make use of the built in PLL. The CDCS502 operates in 3.3V environment. It is characterized for operation from C to It is offered in an Pin TSSOP package. FUNCTION TABLE FS SSC_SEL SSC_SEL SSC Amount f OUT IN f OUT at f in MHz 0.00% MHz (1) 0.50% MHz 1.00% MHz 2.00% MHz 0.00% 108 MHz 0.50% 108 MHz 1.00% 108 MHz 2.00% 108 MHz (1) In this mode the signal from the crystal bypasses the internal PLL for maximum performance. PIN FUNCTIONS SIGNAL PIN TYPE X IN I Crystal Input X OUT O Crystal Output OUT O LVCMOS Clock Output SSC_SEL I Spread Selection Pins, internal pull-up FS I Frequency Multiplication Selection, internal pull-up V DD Power 3.3V Power Supply GND Ground Ground Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): CDCS502

(PW) PACKAGE (1) ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING CONDITIONS RECOMMENDED CRYSTAL SPECIFICATIONS (1) CDCS502 www.ti.com SCAS868 DECEMBER 2008 THERMAL AIR FLOW (CFM) CDCV304PW 8-PIN TSSOP UNIT 150 250 500 R θ JA High K 149 142 138 132 C/W R θ JA Low K 230 185 170 150 C/W R θ JC High K C/W R θ JC High K C/W (1) The package thermal impedance is calculated in accordance with JESD and JEDEC2S2P (high-k board). over operating free-air temperature range (unless otherwise noted) VALUE UNIT V DD Supply voltage range 0.5 to 4.6 V V IN Input voltage range 0.5 to 4.6 V V out Output voltage range 0.5 to 4.6 V I IN Input current I V I VDD) mA I out Continuous output current mA T ST Storage temperature range to 150 C T J Maximum junction temperature 125 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. MIN NOM MAX UNIT V DD Supply voltage 3.0 3.6 V f IN Input Frequency MHz V IL Low level input voltage LVCMOS 0.3 VDD V V IH High level input voltage LVCMOS 0.7 VDD V V I Input Voltage threshold LVCMOS 0.5 VDD V C L Output Test Load LVCMOS pF I OH OL Output Current mA T A Operating free-air temperature C PARAMETER CONDITIONS MIN NOM MAX UNIT FS f X-tal Crystal input frequency range MHz FS ESR Effective series resistance (2) 180 Ω C L On-chip load capacitance at Xin and Xout pF T X-tal Crystal power dissipation µ W (1) For further details on the crystal, see the crystal part in the (2) With pF crystal package parallel capacitance Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCS502

f -□Input□Frequency□-□MHzi I -□Input□Current□-□mA DD x1□Mode x4□Mode CDCS502 SCAS868 DECEMBER 2008 www.ti.com over operating free-air temperature range (unless otherwise noted) PARAMET CONDITIONS MIN TYP MAX UNIT ER f out MHz; FS no SSC IDD Device supply current f out MHz; FS SSC mA f out MHz; FS SSC FS MHz f OUT Output frequency FS 108 MHz I IH LVCMOS input current V I VDD; VDD 3.6 V µ A I IL LVCMOS input current V I VDD 3.6 V µ A I OH 0.1 mA 2.9 LVCMOS high-level output V OH I OH mA 2.4 V voltage I OH mA 2.2 I OL 0.1 mA 0.1 LVCMOS low-level output V OL I OL mA 0.5 V voltage I OL mA 0.8 t jit(CC) Cycle to cycle jitter f out 108 MHz; FS SSC 1%, 100 ps 10000 Cycles t r f Rise and fall time 20% 80% 0.75 ns O dc Output duty cycle PLL active 45% 55% f MOD Modulation frequency kHz Figure IDD vs Input Frequency, VCC 3.3V, SSC Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): CDCS502

www.ti.com SCAS868 DECEMBER 2008 Figure Phase Noise Plot, Mode, SSC, MHz Crystal Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCS502

A CRYSTAL SSC MODULATION PARAMETER MEASUREMENT INFORMATION 10□pF LVCMOS CDCS502 VDD 1□k/c87 1□k/c87 LVCMOS LVCMOS Series□Termination ~18Ω Typical□Driver Impedance ~32Ω CDCS502 Z =□50□WL CDCS502 SCAS868 DECEMBER 2008 www.ti.com The CDCS502 requires a crystal with a frequency between and MHz (27MHz in Mode). The crystal stage is designed with an internal load capacitance of 10pF for crystals with this shunt load capacitance. If a slightly bigger capacity then 10pF is needed, small external capacitors can be used to get to this value. This solution however might influence the power-up behavior of the crystal stage, so using a 10pF load capacitance crystal is highly recommended. For further details on capacitive load calculation, see application report SCAA085 NOTE: Even though the CDCS502 is characterized down to a standard crystal is usually not rated for operation at this low temperature. The exact implementation of the SSC modulation plays a vital role for the EMI reduction. The CDCS502 uses a triangular modulation scheme implemented in a way that the modulation frequency depends on the VCO frequency of the internal PLL and the spread amount is independent from the VCO frequency. The modulation frequency can be calculated by using one of the below formulas chosen by frequency multiplication mode. FS =0: f mod f IN 708 FS =1: f mod f IN 620 Figure Test Load Figure Test Load for 50- Ω Board Environment Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): CDCS502

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDCS502PW Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CS502 CDCS502PW.B Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CS502 CDCS502PWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CS502 CDCS502PWR.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CS502 CDCS502PWRG4.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CS502 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCS502PWR TSSOP PW 8 2000 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CDCS502PW PW TSSOP 8 150 530 10.2 3600 3.5 CDCS502PW.B PW TSSOP 8 150 530 10.2 3600 3.5 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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