CDCR83ADBQG4

CDCR83A_14 TI1 | Alldatasheet

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FEATURES

V DDO GNDO CLK NC CLKB GNDO V DDO MULT0 MULT1 DBQ PACKAGE (TOP VIEW) NC − No internal connection

DESCRIPTION

Applications

a Single 3.3-V Supply and 120 mW at 300 MHz (Typ) Packaged in a Shrink Small-Outline Package (DBQ) Supports Frequency Multipliers: No External Components Required for PLL Supports Independent Channel Clocking Spread Spectrum Clocking Tracking Capability to Reduce EMI Designed for Use With TI's 133-MHz Clock Synthesizers CDC924 and CDC921 Cycle-Cycle Jitter Is Less Than ps at 400 MHz Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement Supports Industrial Temperature Range of C to C The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications. The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLKM SYNCLKN, where SYNCLK BUSCLK/4. The DRCG detects the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. DIRECT RAMBUS, Rambus are trademarks of Rambus Inc. PRODUCTION DATA information is current as of publication date. Copyright 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com Bypass MUX Test MUX B A PLL Phase Aligner PACLK PLLCLK ByPCLK CLK CLKB REFCLK φD SYNCLKNPCLKM MULT0 MULT1 PWRDWNB S0 S1 S2 STOPB CDCR83A SCAS811 AUGUST 2005 User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz with clock references ranging from MHz to 100 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state for board testing. The CDCR83A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions. The CDCR83A is characterized for operation over free-air temperatures of C to FUNCTIONAL BLOCK DIAGRAM FUNCTION TABLE (1) MODE CLK CLKB Normal Phase aligned clock Phase aligned clock B Bypass PLLCLK PLLCLKB Test REFCLK REFCLKB Output test (OE) x Hi-Z Hi-Z Reserved Reserved Reserved Hi-Z Hi-Z (1) X don't care, Hi-Z high impedance

www.ti.com CDCR83A SCAS811 AUGUST 2005 TERMINAL FUNCTIONS TERMINAL I/O NO. CLK O Output clock CLKB O Output clock (complement) GNDC GND for phase aligner GNDI GND for control inputs GNDO 17, GND for clock outputs GNDP GND for PLL MULT0 I PLL multiplier select MULT1 I PLL multiplier select NC Not used PCLKM I Phase detector input PWRDNB I Active low power down REFCLK I Reference clock I Mode control I Mode control I Mode control STOPB I Active low output disable SYNCLKN I Phase detector input V DD C V DD for phase aligner V DD IPD Reference voltage for phase detector inputs and STOPB V DD IR Reference voltage for REFCLK V DD O 16, V DD for clock outputs V DD P V DD for PLL

www.ti.com PLL DIVIDER SELECTION ABSOLUTE MAXIMUM RATINGS DISSIPATION RATINGS CDCR83A SCAS811 AUGUST 2005 Table lists the supported REFCLK and BUSCLK frequencies. Other REFCLK frequencies are permitted, provided that (267 MHz BUSCLK 400 MHz) and (33 MHz REFCLK 100 MHz). Table REFCLK and BUSCLK Frequencies MULT0 MULT1 REFCLK MULTIPLY BUSCLK (1) (MHz) RATIO (MHz) 267 300 400 267 400 356 (1) BUSCLK will be undefined until a valid reference clock is available at REFCLK. After applying REFCLK, the PLL requires stabilization time to achieve phase lock. Table Clock Output Driver States STATE PWRDNB STOPB CLK CLKB Powerdown X GND GND CLK stop V STOP V STOP Normal PACLK/PLLCLK/REFCLK (1) PACLKB/PLLCLKB/REFCLKB (1) Depending on the state of S0, S1, and over operating free-air temperature range (unless otherwise noted) (1) UNIT V DD Supply voltage range (2) 0.5 V to V V O Output voltage range at any output terminal 0.5 V to V DD 0.5 V V I Input voltage rangeat any input terminal 0.5 V to V DD 0.5 V Continuous total power dissipation See Dissipation Rating Table T A Operating free-air temperature range C to C T stg Storage temperature range C to 150 C Lead temperature 1,6 mm (1/16 inch) from case for seconds 260 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the GND terminals. PACKAGE T A C DERATING FACTOR T A C T A C POWER RATING ABOVE T A C (1) POWER RATING POWER RATING DBQ 1400 mW mW/ C 905 mW 740 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

www.ti.com RECOMMENDED OPERATING CONDITIONS TIMING REQUIREMENTS CDCR83A SCAS811 AUGUST 2005 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V DD Supply voltage 3.135 3.3 3.465 V V IH High-level input voltage (CMOS) 0.7 V DD V V IL Low-level input voltage (CMOS) 0.3 V DD V Initial phase error at phase detector inputs 0.5 t c(PD) 0.5 t c(PD) V (required range for phase aligner) V IL REFCLK low-level input voltage 0.3 V DD IR V V IH REFCLK high-level input voltage 0.7 V DD IR V V IL Input signal low voltage (STOPB) 0.3 V DD IPD V V IH Input signal high voltage (STOPB) 0.7 V DD IPD V Input reference voltage for (REFCLK) (VDDIR) 1.235 3.465 V Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD) 1.235 3.465 V I OH High-level output current mA I OL Low-level output current mA T A Operating free-air temperature C MIN MAX UNIT t c(in) Input cycle time ns Input cycle-to-cycle jitter 250 ps Input duty cycle over 10,000 cycles 40% 60% f mod Input frequency modulation, kHz Modulation index, nonlinear maximum 0.5% 0.6% Phase detector input cycle time (PCLKM and SYNCLKN) 100 ns SR Input slew rate V/ns Input duty cycle (PCLKM and SYNCLKN) 25% 75%

www.ti.com ELECTRICAL CHARACTERISTICS CDCR83A SCAS811 AUGUST 2005 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP (2) MAX UNIT V O(STOP) Output voltage during CLK Stop (STOPB See Figure 1.1 V O(X) Output crossing-point voltage See Figure and Figure 1.3 1.8 V V O Output voltage swing See Figure 0.4 0.6 V V IK Input clamp voltage VDD 3.135 I I mA 1.2 V See Figure V OH High-level output voltage V DD min to max, I OH mA V DD 0.1 V V DD 3.135 I OH mA 2.4 See Figure V OL Low-level output voltage V DD min to max, I OH mA 0.1 V V DD 3.135 I OH mA 0.5 V DD 3.135 V O V I OH High-level output current V DD 3.3 V O 1.65 V mA V DD 3.465 V O 3.135 V 14.5 V DD 3.135 V O 1.95 V 61.5 I OL Low-level output current V DD 3.3 V O 1.65 V mA V DD 3.465 V O 0.4 V 25.5 I OZ High-impedance-state output current µ A I OZ(STOP) High-impedance-state output current during Stop V O GND or V DD 100 µ A CLK stop High-impedance-state output current in I OZ(PD) PWRDNB V O GND or V DD 100 µ A power-down state REFCLK, PCLKM, SYNCLKN, STOPB High-level input I IH V DD 3.465 V I V DD µ A current PWRDNB, S0, S1, S2, MULT0, MULT1 REFCLK, PCLKM, SYNCLKN, STOPB Low-level input I IL V DD 3.465 V I µ A current PWRDNB, S0, S1, S2, MULT0, MULT1 High state R I at I O 14.5 mA to 16.5 mA Z O Output impedance Ω Low state R I at I O 14.5 mA to 16.5 mA PWRDNB µ A Reference current VDDIR, VDDIPD V DD 3.465 V PWRDNB 0.5 mA C I Input capacitance V I V DD or GND pF C O Output capacitance V O V DD or GND pF I DD(PD) Supply current in pwoer-down state REFCLK MHz to 100 MHz, 100 µ A PWDNB STOPB I DD(CLKSTOP) Supply current in CLK stop state BUSCLK configured for 400 MHz mA I DD(NORMAL) Supply current in normal state BUSCLK 400 MHz mA (1) V DD refers to any of the following; V DD V DD IPD, V DD IR, V DD V DD and V DD P (2) All typical values are at V DD 3.3 T A

www.ti.com SWITCHING CHARACTERISTICS STATE TRANSITION LATENCY SPECIFICATIONS CDCR83A SCAS811 AUGUST 2005 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT t c(out) Clock output cycle time 2.5 3.75 ns 267 MHz 300 MHz Total cycle jitter over Infinite and stopped t (jitter) See Figure ps or clock cycles phase alignment 356 MHz 400 MHz t (phase) Phase detector phase error for distributed loop Static phase error (2) 100 100 ps t (phase, SSC) PLL output phase error when tracking SSC Dynamic phase error (2) 100 100 ps Output duty cycle over 10,000 cycles See Figure 45% 55% 267 MHz 300 MHz Output cycle-to-cycle duty Infinite and stopped t (DC, err) See Figure ps cycle error phase alignment 356 MHz 400 MHz t r t f Output rise and fall times (measured at 20% 80% of output See Figure 160 400 ps voltage) Δ t Difference between rise and fall times on a single device See Figure 100 ps (20% 80%) f t r (1) All typical values are at V DD 3.3 T A (2) Assured by design TEST PARAMETER FROM TO MIN TYP (1) MAX UNIT CONDITIONS t (powerup) Delay time, PWRDNB to CLK/CLKB out- See Figure put settled (excluding t (DISTLOCK) Powerdown Normal ms Delay time, PWRDNB to internal PLL and clock are on and settled t (VDDpowerup) Delay time, power up to CLK/CLKB output See Figure settled V DD Normal ms Delay time, power up to internal PLL and clock are on and settled t (MULT) MULT0 and MULT1 change to CLK/CLKB Normal Normal See Figure ms output resettled (excluding t (DISTLOCK) t (CLKON) STOPB to CLK/CLKB glitch-free clock See Figure CLK Stop Normal ns edges t (CLKSETL) STOPB to CLK/CLKB output settled to within CLK Stop Normal See Figure cycles ps of the phase before STOPB was disabled t (CLKOFF) STOPB to CLK/CLKB output disabled Normal CLK Stop See Figure ns t (powerdown) Delay time, PWRDNB to the device in the Normal Powerdown See Figure ms power-down mode t (STOP) Maximum time in CLKSTOP (STOPB before reentering normal mode STOPB Normal See Figure 100 µ s (STOPB t (ON) Minimum time in normal mode (STOPB before reentering CLKSTOP Normal CLK Stop See Figure 100 ms (STOPB t (DISTLOCK) Time from when CLK/CLKB output is settled to when the phase error between Unlocked Locked ms SYNCLKN and PCLKM falls within t (phase) (1) All typical values are at V DD 3.3 T A

www.ti.com PARAMETER MEASUREMENT INFORMATION 39 Ω , ± 5% 68 Ω , ± 5% 68 Ω , ± 5% 10 pF 100 pF39 Ω , ± 5% 10 pF RT = 28 Ω RT = 28 Ω CLK CLKB tc(1) tc(2) Cycle-to-cycle jitter = | tc(1) − tc(2)| over 10000 consecutive cycles CLK CLKB tc(3) Cycle-to-cycle jitter = | tc(3) − tc(4)| over 10000 consecutive cycles tc(4) CLK CLKB tpd(1) tc(5) Duty cycle = (tpd(1)/tc(5)) CDCR83A SCAS811 AUGUST 2005 Figure Test Load and Voltage Definitions O(STOP) V O(X) V O V OH V OL Figure Cycle-to-Cycle Jitter Figure Short Term Cycle-to-Cycle Jitter Over Four Cycles Figure Output Duty Cycle

www.ti.com CLK CLKB tpd(2) tc(6) Duty cycle error = tpd(2) − tpd(3) tpd(3) tc(7) CLK CLKB VO(X)+ VO(X), nom VO(X)− 80% tftr 20% VOL VOH PWRDNB CLK/CLKB t(power down) t(power up) MULT0 and/or MULT1 CLK/CLKB t(MULT) CDCR83A SCAS811 AUGUST 2005 PARAMETER MEASUREMENT INFORMATION (continued) Figure Duty Cycle Error (Cycle-to-Cycle) Figure Crossing-Point Voltage Figure Voltage Waveforms Figure PWRDNB Transition Timings Figure MULT Transition Timings

www.ti.com STOPB t(CLKOFF) (see Note A) t(ON) t(STOP) t(CLKSETL) t(CLKON) (see Note A) Clock output settled within 50 ps of the phase before disabled Clock enabled and glitch free Output clock not specified glitches ok CLK/CLKB CDCR83A SCAS811 AUGUST 2005 PARAMETER MEASUREMENT INFORMATION (continued) V ref V O 200 mV Figure 10. STOPB Transition Timings

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples CDCR83ADBQ ACTIVE SSOP DBQ 24 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCR83A CDCR83ADBQG4 ACTIVE SSOP DBQ 24 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCR83A CDCR83ADBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCR83A CDCR83ADBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCR83A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 11-Apr-2013 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCR83ADBQR SSOP DBQ 24 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 2

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