CDCR61A

CDCR61A TI | Alldatasheet

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DIRECT RAMBUS CLOCK GENERATOR – LITE SCAS626 – FEBRUARY 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068400-MHz Differential Clock Source for Direct Rambus Memory Systems for an 800-MHz Data Transfer Rate /C0068Operates From Two (3.3-V and 1.80-V) Power Supplies With 180 mW (Typ) at 400 MHz Total /C0068Packaged in a Thin Shrink Small-Outline Package (PW) /C0068External Crystal Required for Input

description

The Direct Rambus clock generator – lite (DRCG-Lite) is an independent crystal clock generator. It performs clock multiplication using PLL, sourced by an internal crystal oscillator. It provides one differential, high-speed Rambus channel compatible output pair. Also, one single-ended output is available to deliver 1/2 of the crystal frequency. The Rambus channel operates at up to 400 MHz with an option to select 300 MHz as well. The desired crystal is a 18.75-MHz crystal in a series resonance fundamental application. The CDCR61A is characterized for operation over free-air temperatures of 0°C to 85°C. functional block diagram OSC PLL BUSCLK LCLK XTAL XOUT XIN S1 S2 DIV VDDP BUSCLK FREQUENCY SETTINGS S0 M (PLL MULTIPLIER) 0 16 1 or Open 64/3 FUNCTION TABLE VDDP S1 S2 MODE CLK CLKB LCLK ON 0 0 Normal CLK CLKB XIN divided by 2 ON 1 1 Normal CLK CLKB XIN divided by 2 ON 0 1 Test Divided by 2 Divided by 2 XIN divided by 2 ON 1 0 Test Divided by 4 Divided by 4 XIN divided by 2

0 V 0 0 Test XIN XIN (invert) XIN divided by 2

0 V 1 1 Test XIN XIN (invert) XIN divided by 2

0 V 0 1 Test XIN divided by 2 XIN (invert) divided by 2XIN divided by 2

0 V 1 0 Test XIN divided by 4 XIN (invert) divided by 4XIN divided by 2

Copyright  2000, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Direct Rambus and Rambus are trademarks of Rambus Inc. VDDP GNDP XOUT XIN VDDL LCLK GNDL VDD GND CLK CLKB GND V DD PW PACKAGE (TOP VIEW)

DIRECT RAMBUS CLOCK GENERATOR – LITE SCAS626 – FEBRUARY 2000

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NAME NO. I/O DESCRIPTION CLK 13 O Output clock, connect to Rambus channel CLKB 12 O Output clock (complement), connect to Rambus channel GNDP, GNDL, GND 2, 7, 11, 14 Ground LCLK 6 O LVCMOS output, 1/2 of crystal frequency S0, S1, S2 16, 8, 9 I LVTTL level logic select terminal for function selection VDD 10, 15 Power supply, 3.3 V VDDP 1 Power supply for PLL, 3.3 V (0 V for Test mode) VDDL 5 Power supply for LCLK, 1.8 V XIN 4 I Reference crystal input XOUT 3 O Reference crystal feedback absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C ‡ TA = 85°C POWER RATING PW 1400 mW 11 mW/°C 740 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

DIRECT RAMBUS CLOCK GENERATOR – LITE SCAS626 – FEBRUARY 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 3 3.3 3.6 V LCLK supply voltage, VDDL 1.7 1.8 2.1 V Low level input voltage VIL S0 0.35×VDD VLow-level input voltage, VIL S1, S2 0.35×VDD V High level input voltage VIH S0 0.65×VDD VHigh-level input voltage, VIH S1, S2 0.65×VDD V Internalpullup resistance S0 10 55 100 kWInternal pullup resistance S1, S2 90 145 250 kW Low level output current IOL CLK, CLKB 16 mALow-level output current, IOL LCLK 10 mA High level output current IOH CLK, CLKB –16 mAHigh-level output current, IOH LCLK –10 mA Input frequency at crystal input 14.0625 18.75 MHz Input capacitance (CMOS) CI† S0, S1, S2 2.5 pFInput capacitance (CMOS) , C I† XIN, XOUT 20 pF Operating free-air temperature, TA 0 85 °C † Capacitance measured at f = 1 MHz, dc bias = 0.9 V, and VAC < 100 mV timing requirements MIN MAX UNIT Clock cycle time, t(cycle) 2.5 3.7 ns Input slew rate, SR 0.5 4 V/ns State transition latency (VDDX or S0 to CLKs – normal mode), t(STL) 3 ms crystal specifications MIN MAX UNIT Frequency 14.0625 18.75 MHz Frequency tolerance (at 25°C ± 3°C) –15 15 ppm Equivalent resistance (CL = 10 pF) 100 W Temperature drift (–10°C to 75°C) 10 ppm Drive level 0.01 1500 mW Motional inductance 20.7 25.3 mH Insulation resistance 500 M W Spurious attenuation ratio (at frequency ± 500 kHz) 3 dB Overtone spurious 8 dB

DIRECT RAMBUS CLOCK GENERATOR – LITE SCAS626 – FEBRUARY 2000

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † MIN TYP ‡ MAX UNIT VO(X) Differential crossing-point output voltageSee Figures 1 and 7 1.25 1.85 V VO(PP) Peak-to-peak output voltage swing, single ended VOH – VOL , See Figure 1 0.4 0.7 V VIK Input clamp voltage VDD = 3 V, II = –18 mA –1.2 V R I Input resistance XIN, XOUT VDD = 3.3 V, VI = VO >50 kW XOUT VDD = 3.3 V, VO = 2 V 27 mA IIH High-level input currentS0 VDD = 3.6 V, VI = VDD 10 mA S1, S2 VDD = 3.6 V, VI = VDD 10 mA XOUT VDD = 3.3 V, VO = 0 V –5.7 mA IIL Low-level input current S0 VDD = 3.6 V, VI = 0 V –30 –100 mA S1, S2 VDD = 3.6 V, VI = 0 V –10 –50 mA See Figure 1 2.1 VOH High level output voltage CLK, CLKB VDD = min to max, IOH = –1 mA VDD – 0.1 V VVOH High-level output voltage VDD = 3 V, IOH = –16 mA 2.2 V LCLK VDDL = min to max,IOH = – 10 mA VDDL –

0.45 V VDDL

VOL Low level output voltage CLK, CLKB VDD = min to max, IOL = 1 mA 0.1 VVOL Low-level output voltage VDD = 3 V, IOL = 16 mA 0.5 V LCLK VDDL = min to max,IOL = 10 mA 0 0.45 VDD = 3.135 V, VO = 1 V –32 –52 CLK, CLKB VDD = 3.3 V, VO = 1.65 V –51 IOH High level output current VDD = 3.465 V, VO = 3.135 V –14.5 –21 mAIOH High-level output current VDDL = 1.7 V, VO = 0.5 V –11 –26 mA LCLK VDDL = 1.8 V, VO = 0.9 V –28 VDDL = 2.1 V, VO = 1.6 V –24.5 –35 VDD = 3.135 V, VO = 1.95 V 43 61.5 CLK, CLKB VDD = 3.3 V, VO = 1.65 V 65 IOL Low level output current VDD = 3.465 V, VO = 0.4 V 25.5 36 mAIOL Low-level output current VDDL = 1.7 V, VO = 1.2 V 11 27 mA LCLK VDDL = 1.8 V, VO = 0.9 V 30 VDDL = 2.1 V, VO = 0.5 V 28 38 rOH High-level dynamic output resistance§ DIO – 14.5 mA to DIO – 16.5 mA 12 25 40 W rOL Low-level dynamic output resistance§ DIO + 14.5 mA to DIO + 16.5 mA 12 17 40 W C O Output capacitance CLK, CLKB 3 pFC O O utput capacitance LCLK 3 pF † VDD refers to any of the following; VDD , VDDL , and VDDP‡ All typical values are at VDD = 3.3 V, VDDL = 1.8 V, TA = 25°C. § rO = DVO /DIO . This is defined at the output terminals, not at the measurement point of Figure 1.

DIRECT RAMBUS CLOCK GENERATOR – LITE SCAS626 – FEBRUARY 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS † MIN TYP ‡ MAX UNIT IDD Static supply current Outputs high or low (VDDP = 0 V) 6.5 mA IDDL Static supply current (LVCMOS) Outputs high or low (VDDP = 0 V) 50 mA IDD(NORMAL) Supply current in normal state

300 MHz 39 mA

IDD(NORMAL) Supply current in normal state

400 MHz 50 mA

IDDL(NORMAL) Supply current in normal state (LVCMOS) 400 MHz 8 mA † VDD refers to any of the following; VDD , VDDL , and VDDP‡ All typical values are at VDD = 3.3 V, VDDL = 1.8 V, TA = 25°C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT t(cycle) Clock cycle time (CLK, CLKB) 2.5 3.7 ns t j Total jitter over 1, 2, 3, 4, 5, or 6300 MHz See Figure 3 140 pstcj j ,,,,, clock cycles‡ 400 MHz See Figure 3 100 ps tjL Long term jitter

300 MHz

400 MHz

tDC Output duty cycle over 10,000 cycles See Figure 5 45% 55% tDC ERR Output cycle to cycle duty cycle error pstDC,ERR O utput cycle-to-cycle duty cycle error tr, tf Output rise and fall times (measured at 20%-80% of output voltage)# CLK, CLKB See Figure 9, 160 400 ps Dt Difference between rise and fall times on a single device (20%–80%) |tf – tr|# See Figure 9, 100 ps tc(LCLK) Clock cycle time (LCLK) 106.6 142.2 ns t(cj) LCLK cycle jitter§ See Figure 11 –0.2 0.2 ns t(cj10) LCLK 10-cycle jitter§¶ See Figure 11 –1.3 t(cj) 1.3 t(cj) ns tDC Output duty cycle LCLK 40% 60% tr, tf Output rise and fall times (measured at 20%-80% of output voltage) LCLK See Figure 9 1 ns PLL loop bandwidth fmod = 50 kHz –3 dBPLL loop bandw idth fmod = 8 MHz –20 dB † All typical values are at VDD = 3.3 V, TA = 25°C. ‡ Output short-term jitter specification is peak-to-peak (see Figure 9). § LCLK cycle jitter and 10-cycle jitter are defined as the difference between the measured period and the nominal period. ¶ LCLK 10-cycle jitter specification is based on the measured value of LCLK cycle jitter. # VDD = 3.3 V

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39 W , ±5%

68 W , ±5%

board during device characterization. Figure 1. Test Load and Voltage Definitions (VO(STOP) , VO(X), VO , VOH , VOL ) Figure 2. Cycle-to-Cycle Jitter Figure 3. Short-Term Cycle-to-Cycle Jitter over 2, 3, 4, or 6 Cycles Figure 4. Long-Term Jitter

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Figure 9. PLL Frequency Transition Timing Figure 10. LCLK Jitter

DIRECT RAMBUS CLOCK GENERATOR – LITE SCAS626 – FEBRUARY 2000 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040064/E 08/96

14 PIN SHOWN

1,20 MAX A 0,19 4,50 4,30 6,20 6,60 0,30 0,75 0,50 0,25 Gage Plane 0,15 NOM 0,65 M0,10 0°–8° 0,10 PINS ** A MIN A MAX DIM 2,90 3,10 4,90 5,10 6,60 6,404,90 5,10 7,70 7,90 9,60 9,80 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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