CDCM7005RGZR

Texas Instruments

3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

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1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 Thermal□Pad must□be soldered□to□GND STATUS_REF□or PRI_SEC_CLK STATUS_VCXO□or I_REF_CP RESET HOLD or PD VCCY1A Y1BVCC VCCY2A Y2BVCC VCCY3A Y3B PRI_REF REF_SEL NC VCC_CP AVCC CP_OUT AVCC CTRL_LE CTRL_CLK AVCC CTRL_DATA PLL_LOCK GND VCC VCC VCC VCC Y4B Y4A VCC VCC SEC_REF AVCC AVCC VBB VCC VCXO_IN VCC VCC Y0A Y0B VCC VCXO_IN P0022-01 CP_OUTREF_SELPRI_REF GND GND GND GND GND GND GNDSEC_REF GND AVCC AVCC AVCC AVCC AVCC STATUS_ REF□or PRI_SEC_ CLK GND GND GND GND GND VCC STATUS_ VCXOVCXO_IN GND VCC VCC VCC VCC VCC VCC Y0A GND GND GND GND GND VCC Y4B Y0B VCC VCC VCC VCC VCCVCC Y4A PD Y1A Y1B Y2A Y2B Y3A Y3B RESET or HOLD 1 2 3 4 5 6 7 8 A B C D F G H I_REF_CP or PLL_LOCK VBB VCC_CP CTRL_LE CTRL_CLK CTRL_ DATA VCXO_INE CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 3.3-VHIGHPERFORMANCECLOCKSYNCHRONIZERANDJITTERCLEANER Check forSamples: CDCM7005 1FEATURES PIN ASSIGNMENTS (TOP VIEW)• High Performance LVPECL and LVCMOS PLL Clock Synchronizer

Two ReferenceClock Inputs(Primaryand Secondary Clock)forRedundancy Support With Manual or Automatic Selection
Accepts LVCMOS InputFrequenciesUp to200 MHz
VCXO_IN Clock isSynchronized toOne ofthe Two ReferenceClocks
VCXO_IN FrequenciesUp to2.2GHz (LVPECL)
Outputs Can Be a Combination ofLVPECL and LVCMOS (Up toFiveDifferentialLVPECL Outputs or Up to10 LVCMOS Outputs)
Output Frequency isSelectableby x1,/2,/3,/4, /6,/8,/16on Each Output Individually
EfficientJitterCleaningFrom Low PLL Loop Bandwidth
Low Phase Noise PLL Core
Programmable Phase Offset(PRI_REF and SEC_REF toOutputs)
Wide Charge Pump CurrentRange From 200 μA to3 mA
DedicatedCharge Pump Supply (VCC_CP) for Wide Tuning VoltageRange VCOs
PresetsCharge Pump toVCC_CP/2 forFast Center-FrequencySettingofVC(X)O
Analog and DigitalPLL Lock Indication
ProvidesVBB Bias VoltageOutput forSingle- Ended InputSignals(VCXO_IN)
Frequency Hold-OverMode Improves Fail-Safe Operation
Power-Up ControlForces LVPECL Outputs to 3-StateatVCC < 1.5V
SPI ControllableDevice Setting
3.3-VPower Supply
Packaged in64-PinBGA (0,8mm Pitch– ZVA) or 48-PinQFN (RGZ)
IndustrialTemperature Range –40°C to85°C Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications.

DESCRIPTION

The CDCM7005 isa high-performance,low phase noiseand low skew clocksynchronizerthatsynchronizesa VCXO (voltagecontrolledcrystaloscillator)or VCO (voltagecontrolledoscillator)frequencyto one of the two referenceclocks.The programmablepre-dividerM and thefeedback-dividersN and P givea highflexibilitytothe frequencyratioofthereferenceclocktoVC(X)O:

VC(X)O_IN /PRI_REF = (N x P) /M or
VC(X)O_IN /SEC_REF = (N x P) /M VC(X)O_IN clockoperatesup to2.2GHz. Through theselectionofexternalVC(X)O and loopfiltercomponents, thePLL loopbandwidthand damping factorcan be adjusttomeet differentsystemrequirements. The CDCM7005 can lockto one of two referenceclockinputs(PRI_REF and SEC_REF), supportsfrequency hold-overmode and fast-frequency-lockingforfail-safeand increasedsystem redundancy.The outputsof the CDCM7005 areuserdefinableand can be any combinationofup tofiveLVPECL outputsorup to10 LVCMOS outputs.The LVCMOS outputsare arrangedinpairs(Y0A:Y0B,Y1A:Y1B, … ),so thateach pairhas thesame frequency.But each outputcan be separatelyinvertedand disabled.The builtinsynchronizationlatchesensure thatalloutputsaresynchronizedforlowoutputskew. Alldevicesettings,likeoutputssignaling,dividervalue,inputselection,and many more, are programmable by SPI (3-wireserialperipheralinterface).SPI allowsindividuallycontrolofthedevicesettings. The deviceoperatesin3.3-Venvironmentand ischaracterizedforoperationfrom–40°C to85°C.

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Progr.□Delay N PECL INPUT CTRL_LE CTRL_DATA CTRL_CLK VCXO_IN VCXO_IN CP_OUT PLL_LOCK STATUS_VCXO/ STATUS_REF/ PRI_SEC_CLK I_REF_CP RESET or HOLD PD Bias□Generator V 1.3VCC –VBB VCC_CPVCC AVCC GND PRI_REF SEC_REF REF_SEL REF_MUX LVCMOS FB_MUX LV CMOS Y0B Y0A LV CMOS LV PECL LV CMOS Y1B Y1A LV CMOS LV PECL LV CMOS Y2B Y2A LV CMOS LV PECL LV CMOS Y3B Y3A LV CMOS LV PECL LV CMOS Y4B Y4A LV CMOS LV PECL SPI□LOGIC Manual□& Automatic CLK□Select Current Reference Reference Clock Selected□REF□Signal Progr.□Divider N 2 P Divider ÷□3 ÷□4 ÷□6 /8÷□8 ÷□16 ÷□1 ÷□2 ÷□4 ÷□8 90o90o LOCK Charge PumpPFD Y0_MUX HOLD P16-Div freq.□Detect >□2□Mhz freq.□Detect >□2□Mhz Progr.□Delay M Progr.□Divider M□□2 Feedback Clock Y1_MUXY2_MUXY3_MUXY4_MUX CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 FUNCTIONAL BLOCK DIAGRAM Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:CDCM7005

SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com Table1. PIN ASSINGMENT TERMINAL I/O DESCRIPTION NAME BGA QFN D7, E3, 2,5,6, E4,E5, 9,10, E6,E7, 13,15, 3.3-Vsupply.VCC and AV CC shouldalwayshave thesame supplyvoltage.ItisVCC E8,F7, 18,19, Power recommended thatAV CC use itsown supplyfilter.G2, G3, 20,21, G4, G5, 41,44, G6, G7 45;48 B2,B3, B4,B5, B6,B7, B8,C2, ThermalD2, D3,GND pad and Ground GroundD4, D5, pin24D6, E2, F2,F3, F4,F5, C3, C4, 27,30, Analog 3.3-Vanalogpower supply.Thereisno internalconnectionbetween AV CC andAVCC C5, C6, 32,38, Power VCC .Itisrecommended thatAV CC use itsown supplyfilter.C7 39 Thisisthechargepump power supplypinused tohave thesame supplyas theVCC_CP A3 33 Power externalVCO. Itcan be setfrom2.3V to3.6V. LVCMOS input,controllatchenableforserialprogrammableInterface(SPI),with CTRL_LE A5 29 I hysteresis.Unused orfloatinginputsmust be tiedtoproperlogiclevel.A 20kΩ or largerpull−up resistortoVCC isrecommended. LVCMOS input,serialcontrolclockinputforSPI,withhysteresis.Unused or CTRL_CLK A6 28 I floatinginputsmust be tiedtoproperlogiclevel.A 20kΩ orlargerpull−up resistor toVCC isrecommended. LVCMOS input,serialcontroldatainputforSPI,withhysteresis.Unused or CTRL_DATA A7 26 I floatinginputsmust be tiedtoproperlogiclevel.A 20kΩ orlargerpull−up resistor toVCC isrecommended. LVCMOS input,asynchronouspower down (PD) signal.Thispinislowactiveand can be activatedexternalorby thecorrespondingbitintheSPI register(incase of logichigh,theSPI settingisvalid).Switchesthedeviceintopower-down mode. ResetsM- and N-Divider,3-stateschargepump, STATUS_REF, or PD H1 1 I PRI_SEC_CLK pin,STATUS_VCXO orI_REF_CP pin,PLL_LOCK pin,VBB pin and allYx outputs.SetstheSPI registertodefaultvalue;has internal150-kΩ pullupresistor.Itisrecommended toramp up thePD withthesame timeas VCC and AV CC orlater.The ramp up rateofthePD shouldnotbe fasterthantheramp up rateofVCC and AV CC . ThisLVCMOS inputcan be programmed (SPI)toactas HOLD orRESET. RESET isthedefaultfunction.Thispinislowactiveand can be activatedexternalorvia thecorrespondingbitintheSPI register.Incase ofRESET, thechargepump (CP) isswitchedto3-stateand allcounters(N,M, P) areresettozero(theinitialdivider settingsaremaintainedinSPI registers).The LVPECL outputsarestaticlowand highrespectivelyand theLVCMOS outputsareallloworhighifinverted.RESET RESET or isnotedge triggeredand shouldhave a pulsedurationofatleast5 ns.H8 14 IHOLD Incase ofHOLD, theCP isswitchedinto3-statemode only.AfterHOLD is releasedand withthenextvalidreferenceclockcyclethechargepump is switchedback intonormaloperation(CP staysin3-stateas longas no reference clockisvalid).DuringHOLD, theP dividerand alloutputsYx areatnormal operation.Thismode allowsan externalcontrolofthefrequencyhold-overmode. The inputhas an internal150-kΩ pullupresistor. VCXO_IN E1 43 I VCXO LVPECL input VCXO_IN D1 42 I ComplementaryVCXO LVPECL input LVCMOS inputfortheprimaryreferenceclock,withan internal150-kΩ pullupPRI_REF A1 36 I resistorand inputhysteresis. LVCMOS inputforthesecondaryreferenceclock,withan internal150-kΩ pullupSEC_REF B1 37 I resistorand inputhysteresis.

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www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 Table1. PIN ASSINGMENT (continued) TERMINAL I/O DESCRIPTION NAME BGA QFN LVCMOS referenceclockselectioninput.Inthemanual mode theREF_SEL signalselectsone ofthetwo inputclocks: REF_SEL A2 35 I REF_SEL [1]:PRI_REF isselected; REF_SEL [0]:SEC_REF isselected; The inputhas an internal150-kΩ pullupresistor. CP_OUT A4 31 O Charge pump output Biasvoltageoutputtobe used tobiasunused complementaryinputVCXO_IN for VBB C1 40 O singleended signals.The outputofVBB isVCC – 1.3V.The outputcurrentis limitedtoabout1.5mA. Thisoutputcan be programmed (SPI)toprovideeithertheSTATUS_REF or PRI_SEC_CLK information.Thispinissethighifone oftheSTATUS conditionsis valid.STATUS_REF isthedefaultsetting. STATUS_REF or Incase ofSTATUS_REF, theLVCMOS outputprovidestheStatusoftheC8 23 OPRI_SEC_CLK ReferenceClock.Ifa referenceclockwitha frequencyabove 2 MHz isprovidedto PRI_REF orSEC_REF STATUS_REF willbe sethigh. Incase ofPRI_SEC_CLK, theLVCMOS outputindicateswhethertheprimary clock[high]orthesecondaryclock[low]isselected. ThisLVCMOS outputcan be programmed (SPI)toprovideeitherthe STATUS_VCXO informationorserveas currentpathforthechargepump (CP). STATUS_VCXO isthedefaultsetting. Incase ofSTATUS_VCXO, theLVCMOS outputprovidesthestatusoftheVCXOSTATUS_VCXO D8 22 O input(frequenciesabove 2 MHz areinterpretedas validclock;activehigh).orI_REF_CP Incase ofI_REF_CP, itprovidesthecurrentpathfortheexternalreference resistor(12kΩ ±1%) tosupportan accuratechargepump current,optional.Do not use any capacitoracrossthisresistortopreventnoisecouplingviathisnode.If theinternal12 kΩ isselected(defaultsetting),thispincan be leftopen. LVCMOS outputforPLL_LOCK information.ThispinissethighifthePLL isin lock(seefeaturedescription).Thisoutputcan be programmed tobe digitallock detectoranaloglockdetect(seefeaturedescription). The PLL islocked(sethigh),iftherisingedge eitherofPRI_REF orSEC_REF clockand VCXO_IN clockatthephase frequencydetector(PFD) areinsidethe lockdetectwindow fora predeterminednumber ofsuccessiveclockcycles. PLL_LOCK A8 25 I/O The PLL isout-of-lock(setlow),iftherisingedge ofeitherthePRI_REF or SEC_REF) clockand VCXO_IN clockatthePFD areoutsidethelockdetect window orifa certainfrequencyoffsetbetween referencefrequencyand feedback frequency(VCXO) isdetected. Both,thelockdetectwindow and thenumber ofsuccessiveclockcyclesareuser definable(viaSPI). Y0A:Y0B F1,G1, 46,47, The outputsoftheCDCM7005 areuserdefinableand can be any combinationofY1A:Y1B H2, H3, 3,4, up tofiveLVPECL outputsorup to10 LVCMOS outputs.The outputsareY2A:Y2B H4, H5, 7,8, O selectableviaSPI (Word 1,Bit2-6).The power-upsettingisalloutputsareY3A:Y3B H6, H7, 11,12, LVPECL.Y4A:Y4B G8, F8 16,17 Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:CDCM7005

SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) VALUE /UNIT VCC ,AVCC ,VCC_CP Supplyvoltagerange (2) –0.5V to4.6V VI Inputvoltagerange (3) –0.5V toVCC + 0.5V VO Outputvoltagerange (3) –0.5V toVCC + 0.5V OutputcurrentforLVPECL/LVCMOS outputsIOUT ±50 mA(0< VO < VCC ) IIN Inputcurrent(VI< 0,VI> VCC ) ±20 mA Tstg Storagetemperaturerange –65°C to150°C TJ Maximum junctiontemperature 125°C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolute–maximum –ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allsupplyvoltageshave tobe suppliedatthesame time. (3) The inputand outputnegativevoltageratingsmay be exceeded iftheinputand outputclamp-currentratingsareobserved. Package Thermal ResistanceforRGZ (QFN) Package (1)(2) Airflow(lfm) θJA (°C/W) θJC (°C/W) θJP (°C/W) (3) ψJT (°C/W) 0 29.9 22.4 1.5 0.2 150 24.7 0.2 250 23.2 0.2 500 21.5 0.3 (1) The package thermalimpedance iscalculatedinaccordancewithJESD 51 and JEDEC2S2P (high-kboard). (2) ConnectedtoGND withninethermalvias(0,3mm diameter). (3) θJP (junctionpad)isused fortheQFN package,because themain heatflowisfromthejunctiontotheGND pad oftheQFN. Package Thermal ResistanceforZVA (BGA) Package (1) Airflow(m/s) θJA (°C/W) θJC (°C/W) θJB (°C/W) (2) ψJT (°C/W) 0 m/s 53.9 28.3 38.6 0.7 1 m/s 49.8 0.7 2 m/s 48.5 0.8 (1) The package thermalimpedance iscalculatedinaccordancewithJESD 51 and JEDEC2S2P (high-kboard). (2) θJB (junctionboard)isused fortheBGA package,because themain heatflowisfromjunctiontotheboard. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VCC ,AV CC 3 3.3 3.6 Supplyvoltage V VCC_CP 2.3 VCC VIL Low-levelinputvoltageLVCMOS, see (1) 0.3VCC V VIH High-levelinputvoltageLVCMOS, see (1) 0.7VCC V IOH High-leveloutputcurrentLVCMOS (includesallstatuspins) –8 mA IOL Low-leveloutputcurrentLVCMOS (includesallstatuspins) 8 mA VI InputvoltagerangeLVCMOS 0 3.6 V VINPP InputamplitudeLVPECL (VVCXO_IN – V VCXO_IN )(2) 0.5 1.3 V VIC Common-mode inputvoltageLVPECL 1 VCC –0.3 V TA Operatingfree-airtemperature –40 85 °C (1) VILand VIH arerequiredtomaintainac specifications;theactualdevicefunctiontoleratesa smallerinputlevelof1V,ifan ac-couplingto VCC /2isprovided. (2) VINPP minimum and maximum isrequiredtomaintainac specifications;theactualdevicefunctiontoleratesata minimum VINPP of150 mV.

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www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 TIMING REQUIREMENTS overrecommended rangesofsupplyvoltage,loadand operatingfreeairtemperature PARAMETER MIN TYP MAX UNIT PRI_REF/SEC_REF_IN REQUIREMENTS fREF_IN LVCMOS primaryorsecondaryreferenceclockfrequency(1)(2) 0 200 MHz tr/tf Riseand falltimeofPRI_REF orSEC_REF signalsfrom20% to80% ofVCC 4 ns dutyREF DutycycleofPRI_REF orSEC_REF atVCC /2 40% 60% VCXO_IN, VCXO_IN REQUIREMENTS fVCXO_IN VCXO clockfrequency(3) 0 2200 MHz tr/tf Riseand falltime20% to80% ofVINPP at80 MHz to800 MHz (4) 3 ns dutyVCXO DutycycleofVCXO clock 40% 60% SPI/CONTROL REQUIREMENTS (seeFigure14) fCTRL_CLK CTRL_CLK frequency 20 MHz tsu1 CTRL_DATA toCTRL_CLK setuptime 10 ns th2 CTRL_DATA toCTRL_CLK holdtime 10 ns t3 CTRL_CLK highduration 25 ns t4 CTRL_CLK lowduration 25 ns tsu5 CTRL_LE toCTRL_CLK setuptime 10 ns tsu6 CTRL_CLK toCTRL_LE setuptime 10 ns t7 CTRL_LE pulsewidth 20 ns tr/tf Riseand falltimeofCTRL_DATA CTRL_CLK, CTRL_LE from20% to80% ofVCC 4 ns PD, RESET, HOLD, REF_SEL REQUIREMENTS tr /tf Riseand falltimeofthePD, RESET, HOLD, REF_SEL signalfrom20% to80% ofVCC 4 ns (1) AtReferenceClocklessthan2 MHz, thedevicestaysinnormaloperationmode butthefrequencydetectioncircuitryresetsthe STATUS_REF signaltolow.Inthiscase,thestatusoftheSTATUS_REF isno longerrelevant. (2) fREF_IN can be up to250 MHz intypicaloperatingmode (25°C /3.3-VVCC ). (3) IftheFeedback Clock(derivesfromVCXO input)islessthan2 MHz, thedevicestaysinnormaloperationmode butthefrequency detectioncircuitryresetstheSTATUS_VCXO signaland PLL_LOCK signaltolow.Bothstatussignalsareno longerrelevant.This effectstheHOLD-over functionas well,as thePLL_LOCK signalisno longervalid! (4) Use a squarewave forlowerfrequencies(< 80 MHz). DEVICE CHARACTERISTICS overrecommended operatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERALL fVCXO = 245.76MHz, fREF_IN = 30.72MHz, ICC_LVPECL PFD = 240 kHz,ICP = 2 mA, alloutputs 210 260 mA areLVPECL and Div-by-8(load,see Supplycurrent(ICC overfrequencysee Figure13) Figure1 throughFigure4) fVCXO = 245.76MHz, fREF_IN = 30.72MHz,ICC_LVCMOS 120 150 mAPFD = 240 kHz,ICP = 2 mA, Alloutputs areLVCMOS and Div-by-8(load,10 pF) fIN = 0 MHz, VCC = 3.6V,AV CC = 3.6V, ICCPD Power-down current VCC_CP = 3.6V, 100 300 µA VI= 0 V orVCC VO = 0 V orVCC – 0.8V ±40 µAHigh-impedancestateoutputcurrentIOZ forYx outputs VO = 0 V orVCC ±100 µA Voltageon I_REF_CP (externalcurrent 12 kΩ toGND atpinD8 (BGA),pin22VI_REF_CP 1.21 Vpathforaccuratechargepump current)(QFN) VBB Outputreferencevoltage VCC = 3 V – 3.6V;IBB = –0.2mA VCC –1.3 V C O OutputcapacitanceforYx VCC = 3.3V,VO = 0 V orVCC 2 pF InputcapacitanceatPRI_REF and VI= 0 V orVCC ,VI= 0 V orVCC 2.7SEC_REF C I pF InputcapacitanceatCTRL_LE, VI= 0 V orVCC 2CTRL_CLOCK, CTRL_DATA Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:CDCM7005

SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com DEVICE CHARACTERISTICS (continued) overrecommended operatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVCMOS Outputfrequency,see (1),(2),Figure6, Load = 5 pF toGND, 1 kΩ toVCC ,1 kΩfclk 250 MHzand Figure7 toGND VIK LVCMOS inputclamp voltage VCC = 3 V,II= –18 mA –1.2 V LVCMOS inputcurrentforCTRL_LE,II VI= 0 V orVCC ,VCC = 3.6V ±5 µACTRL_CLK, CTRL_DATA LVCMOS inputcurrentforPD, RESET, IIH HOLD, REF_SEL, PRI_REF, VI= VCC ,VCC = 3.6V 5 µA SEC_REF, (see(3)) LVCMOS inputcurrentforPD, RESET, IIL HOLD, REF_SEL, PRI_REF, VI= 0 V,VCC = 3.6V –15 –35 µA SEC_REF, (see(3)) VCC = min tomax, VCC –0.1IOH = –100 μAHigh-leveloutputvoltageforLVCMOSVOH Voutputs VCC = 3 V,IOH = –6 mA 2.4 VCC = 3 V,IOH = –12 mA 2 VCC = min tomax, 0.1IOL = 100 μALow-leveloutputvoltageforLVCMOSVOL Voutputs VCC = 3 V,IOL = 6 mA 0.5 VCC = 3 V,IOL = 12 mA 0.8 IOH High-leveloutputcurrent VCC = 3.3V,VO = 1.65V –30 mA IOL Low-leveloutputcurrent VCC = 3.3V,VO = 1.65V 33 mA VREF_IN = VCC /2,Y = VCC /2,tpho Phase offset(REF_IN toY output)(4) 1.8 nssee Figure11,Load = 10 pF tsk(p) LVCMOS pulseskew,see Figure10 CrosspointtoVCC /2load,see Figure12 150 ps tpd(LH) CrosspointtoVCC /2,PropagationdelayfromVCXO_IN to Load = 10 pF,see Figure12 (PLL 2 2.5 3 nsYx,see Figure10tpd(HL) bypassmode) Alloutputshave thesame dividerratio 55LVCMOS single-endedoutputskew,tsk(o) pssee (5)and Figure10 Outputshave differentdividerratios 70 Dutycycle LVCMOS VCC /2toVCC /2 49% 51% 20% to80% ofswing(loadtslew-rate Outputrise/fallslewrate 2.4 3.5 V/nssee Figure12) LVPECL fclk Outputfrequency,see (6)and Figure5 Load,see Figure13 0 1500 MHz II LVPECL inputcurrent VI= 0 V orVCC ±20 µA VOH LVPECL high-leveloutputvoltage Load,See Figure13 VCC –1.18 VCC –0.81 V VOL LVPECL low-leveloutputvoltage Load,See Figure13 VCC –2 VCC –1.55 V |VOD | Differentialoutputvoltage See Figure9 and load,see Figure13 500 mV VREF_IN = VCC /2tocrosspointofY,tpho Phase offset(REF_IN toY output)(5) –200 100 pssee Figure11 tpd(LH) Propagationdelaytime,VCXO_IN to Crosspoint-to-crosspoint,load 340 490 640 psYx,see Figure10 see Figure13tpd(HL) Crosspoint-to-crosspoint,loadtsk(p) LVPECL pulseskew,see Figure10 10 pssee Figure13 (1) fclkcan be up to400 MHz inthetypicaloperatingmode (25°C /3.3-VVCC ).The totalpower consumptionlimitof700 mW fortheBGA package can be violatedifseveralLVCMOS outputsswitchathighfrequency(seeFigure3 and Figure4). (2) OperatingtheLVCMOS orLVPECL outputabove themaximum frequencywillnotcause a malfunctiontothedevice,buttheoutput signalswingmay no longermeet theoutputspecification. (3) These inputshave an internal150-kΩ pullupresistor. (4) Thisisvalidonlyforthesame frequencyofREF_IN clockand Y outputclock.Itcan be adjustedby theSPI controller(referencedelayM and VCXO delayN). (5) The tsk(o)specificationisonlyvalidforequalloadingofalloutputs. (6) OperatingtheLVCMOS orLVPECL outputabove themaximum frequencywillnotcause a malfunctiontothedevice,buttheoutput signalswingmay no longermeet theoutputspecification.

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www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 DEVICE CHARACTERISTICS (continued) overrecommended operatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Load see Figure13,alloutputshave the 20same dividerratio tsk(o) LVPECL outputskew(5) ps Load see Figure13,outputshave 50differentdividerratios tr /tf Riseand falltime 20% to80% ofVOUTPP ,see Figure9 120 170 220 ps InputcapacitanceatVCXO_IN,C I 1.5 pFVCXO_IN LVCMOS-TO-LVPECL Outputskew between LVCMOS and CrosspointtoVCC /2;load,tsk(P_C) 1.7 2 2.4 nsLVPECL outputs,see (7)and Figure10 see Figure12 and Figure13 PLL ANALOG LOCK IOH High-leveloutputcurrent VCC = 3.6V,VO = 1.8V –110 µA IOL Low-leveloutputcurrent VCC = 3.6V,VO = 1.8V 110 µA High-impedancestateoutputcurrentIOZH LOCK VO = 3.6V (PD issetlow) 45 65 µAforPLL LOCK output(8) High-impedancestateoutputcurrentIOZL LOCK VO = 0 V (PD issetlow) ±5 µAforPLL LOCK output(8) VIT+ Positiveinputthresholdvoltage VCC = min tomax VCC ×0.55 V VIT– Negativeinputthresholdvoltage VCC = min tomax VCC ×0.35 V PHASE DETECTOR fCPmax Maximum chargepump frequency DefaultPFD pulsewidthdelay 100 MHz CHARGE PUMP Charge pump sink/sourcecurrentICP VCP = 0.5VCC_CP ±0.2 ±3 mArange (9) ICP3St Charge pump 3-statecurrent 0.5V < VCP < VCC_CP – 0.5V 10 nA VCP = 0.5VCC_CP ,internalreference 10%resistor,SPI defaultsettings ICPA ICP absoluteaccuracy VCP = 0.5VCC_CP ,externalreference resistor12 kΩ (1%) atI_REF_CP, SPI 5% defaultsettings 0.5V < VCP < VCC_CP – 0.5V,SPIICPM Sink/sourcecurrentmatching 2.5%defaultsettings IVCPM ICP vs VCP matching 0.5V < VCP < VCC_CP – 0.5V 5% (7) The phase ofLVCMOS islagginginreferencetothephase ofLVPECL. (8) Lock outputhas an 80-kΩ pulldownresistor. (9) Definedby SPI settings. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:CDCM7005

50 250 450 650 850 1050 1250 1450 1650 1850 2050 VCXO_IN Input Frequency − MHz VCC = 3.3 V TA = 25°C PDEV − Device Power Consumption − mW All Output Pairs Active (4 div-by-8 / 1 div-by-3) All Output Pairs Active (div-by-1) All Output Pairs Active (div-by-8) One Output Pair Active (div-by-8) G002 No Output Active VCXO_IN Input Frequency − MHz 110 130 150 170 190 210 230 250 50 250 450 650 850 1050 1250 1450 1650 1850 2050 VCC = 3.3 V TA = 25°C ICC − Supply Current − mA All Output Pairs Active (4 div-by-8 / 1 div-by-3) All Output Pairs Active (div-by-1) All Output Pairs Active (div-by-8) D for div-by-2/4/8/16 One Output Pair Active (div-by-8) D For 1 Output Pair D For div-by-3/6 G001 No Output Active CDCM7005 SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com TYPICAL CHARACTERISTICS LVPECL SUPPLY CURRENT vs NUMBER OF ACTIVE OUTPUTS A.Ifdiv-by-2/4/8/16isactivatedforone ormore outputs,'Δ fordiv-by-2/4/8/16'has tobe added toICC ofdiv-by-1.Ifdiv-by-3ordiv-by-6is activated,'Δ fordiv-by-2/4/8/16'and 'Δ fordiv-by3/6'has tobe added toICC ofdiv-by-1. Figure1. LVPECL DEVICE POWER CONSUMPTION vs NUMBER OF ACTIVE OUTPUTS Figure2.

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40 60 80 100 120 140 160 180 200 220 240 260 280 300 Output Frequency − MHz Icc − Supply Current − mA 100 200 300 400 500 600 700 800 900 PDEV − Device Power Consumption − mW for 1 output for 1 output pair no output active one output active div−by−1 one output pair active div−by−1 all outputs active div−by−1 all outputs active div−by−3 for div−by−3/6 VCC = 3.3 V TA = 25/C0053C Load = 10 pF /C0068 /C0068 /C0068 100 150 200 50 100 150 200 250 300 Output Frequency − MHz Icc − Supply Current − mA 100 200 300 400 500 600 700 800 PDEV − Power Device Consumption − mW Vcc = 3.3V load = 5 pF for 1 output for 1 output pair no output active one output active div−by−1 one output pair active div−by−1all outputs active div−by−1 all outputs active div−by−3 for div−by−3/6 TA = 25/C0053C /C0068 /C0068 /C0068 CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 TYPICAL CHARACTERISTICS (continued) LVCMOS SUPPLY CURRENT /DEVICE POWER CONSUMPTION vs NUMBER OF ACTIVE OUTPUTS (Load = 5 pF) B.Itisnotrecommended toexceed power dissipationof700 mW fortheBGA package atTA 85°C. Figure3. LVCMOS SUPPLY CURRENT /DEVICE POWER CONSUMPTION vs NUMBER OF ACTIVE OUTPUTS (Load = 10 pF) B.Itisnotrecommended toexceed power dissipationof700 mW fortheBGA package atTA 85°C. Figure4. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:CDCM7005

f − Frequency − MHz 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 50 100 150 200 250 300 350 400 450 500 LVCMOS Output Swing − V G006 TA = 25°C Load = 5 pF (See Figure 12) VCC = 3 V VCC = 3.6 V VCC = 3.3 V fOut − Output Frequency − MHz 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 50 250 450 650 850 1050 1250 1450 1650 1850 VCC = 3.3 V TA = 25°C Termination = 50 /C0087 to VCC − 2 V VOD − Differential Output Voltage − V G005 CDCM7005 SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL LVPECL OUTPUT VOLTAGE vs OUTPUT FREQUENCY Figure5. LVCMOS OUTPUT SWING vs FREQUENCY Figure6.

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I − Load − mA 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 −5 0 5 10 15 20 25 30 35 VCC = 3.3 V TA = 25°C VBB − Output Reference Voltage − V G008 f − Frequency − MHz 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 50 100 150 200 250 300 350 400 450 500 LVCMOS Output Swing − V G007 VCC = 3 V VCC = 3.6 V VCC = 3.3 V TA = 25°C Load = 10 pF (See Figure 12) CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 TYPICAL CHARACTERISTICS (continued) LVCMOS OUTPUT SWING vs FREQUENCY Figure7. OUTPUT REFERENCE VOLTAGE (VBB) vs LOAD Figure8. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:CDCM7005

80% 20% tr tf VOD VOUTpp T0058-01 CDCM7005 SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure9. LVPECL DifferentialOutput Voltageand Rise/FallTime

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VCXO_IN /VCXO_IN YxA LVPECL LVCMOS YxA/B VCXO_IN /VCXO_IN LVCMOS LVCMOS YxA/B LVPECL LVCMOS tpd(LH) / tpd(HL); tsk(p) = | tpd(HL) − tpd(LH) | LVPECL LVPECL tsk(o)LVPECL tskp_c tpd(LH); tsk(p) = | tpd(HL) − tpd(LH) | tsk(o)LVCMOS CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 PARAMETER MEASUREMENT INFORMATION (continued) A. Outputskew,tsk(o),iscalculatedas thegreaterof: The differencebetween thefastestand theslowesttpd(LH)n(n= 0...4) The differencebetween thefastestand theslowesttpd(HL)n(n= 0...4) B. Pluseskew,tsk(p),iscalculatedas themagnitudeoftheabsolutetimedifferencebetween thehigh-to-low(tpd(HL))and the low-to-high(tpd(LH))propagationdelayswhen a singleswitchinginputcauses one or more outputsto switch, tsk(p)= |tpd(HL)– tpd(LH)|.Pulseskew issometimesreferedtoas pulsewidthdistortionordutycycleskew. Figure10. Output Skew Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:CDCM7005

VT =□VCC – 2V CDCM7005 Driver LVPECL Receiver Z =□50O /c87 50/c8750/c87 Z =□50O /c87 Yx Yx S0079-01 CDCM7005 L VCMOS 1k/c87 1k/c87 10pF T0060-01 VIH VIL VOH VOL VOH VOL REF_IN YxB YxA LVCMOS LVPECL tpho LVPECL 50%□VCC tpho LVCMOS CDCM7005 SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Figure11. Phase Offset Figure12. LVCMOS Output Loading During Device Test Figure13. LVPECL Output Loading During Device Test

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CTRL_DATA CTRL_LE CTRL_CLK tsu5 tsu6 Bit31□(MSB) Bit2 Bit1 Bit0Bit30 tsu1 th2 CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 PARAMETER MEASUREMENT INFORMATION (continued) SPI CONTROL INTERFACE The serialinterfaceof the CDCM7005 isa simpleSPI-compatibleinterfaceforwritingto the registersof the deviceand consistsofthreecontrollines:CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four32-bitwide registers,whichcan be addressedby thetwo LSBs ofa transferredword (bit0 and bit1).Everytransmittedword must have 32 bits,startingwithMSB first.Each word can be writtenseparately.Bit7,8,10,and Bit12 to31 of Word 3 are reservedforfactorytestpurposesand must be filledwithzeros.The transferisinitiatedwiththe fallingedge ofCTRL_LE; as longas CTRL_LE ishigh,no datacan be transferred.DuringCTRL_LE, low data can be written.The data has to be appliedat CTRL_DATA and has to be stablebeforethe risingedge of CTRL_CLK. The transmissionisfinishedby a risingedge ofCTRL_LE. With therisingedge ofCTRL_LE, the separatelytransmittedby thisprocedure.Unused orfloatinginputsmust be tiedtoproperlogiclevel.A 20kΩ or largerpull−up resistortoVCC isrecommended. Figure14. Timing Diagram SPI ControlInterface The SPI serialprotocolaccepts word Write operationonly.There is neithera read,acknowledge,nor a handshake operation. The followingfourwords includetheregistersettingsoftheprogrammablefunctionsoftheCDCM7005. Itcan be modifiedtothecustomerapplicationby changingone or more bits.Itcomes up witha defaultregistersetting afterpower up orifthepower down (PD) controlsignalisapplied.The defaultsettingisshown incolumn fiveof thefollowingwords. Itisrecommended toprogramWord 0,Word 1,Word 2 and Word 3 rightafterpower up and PD becomes HIGH. A lowactivefunctionisshown as [0]and a highactivefunctionisshown as [1]. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:CDCM7005

SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Word 0 PIN AFFECTEDPOWER UPBIT BIT NAME DESCRIPTION/FUNCTION CONDITION BGA QFN

0 C0 RegisterSelection 0

1 C1 RegisterSelection 0

2 M0 ReferenceDividerM ReferenceDividerM Bit0 1

3 M1 ReferenceDividerM Bit1 1

4 M2 ReferenceDividerM Bit2 1

5 M3 ReferenceDividerM Bit3 1

6 M4 ReferenceDividerM Bit4 1

7 M5 ReferenceDividerM Bit5 1

8 M6 ReferenceDividerM Bit6 1

9 M7 ReferenceDividerM Bit7 0

10 M8 ReferenceDividerM Bit8 0

11 M9 ReferenceDividerM Bit9 0

12 N0 VC(X)O DividerN (1) VCXO DividerN Bit0 1

13 N1 VCXO DividerN Bit1 1

14 N2 VCXO DividerN Bit2 1

15 N3 VCXO DividerN Bit3 1

16 N4 VCXO DividerN Bit4 1

17 N5 VCXO DividerN Bit5 1

18 N6 VCXO DividerN Bit6 1

19 N7 VCXO DividerN Bit7 0

20 N8 VCXO DividerN Bit8 0

21 N9 VCXO DividerN Bit9 0

22 N10 VCXO DividerN Bit10 0

23 N11 VCXO DividerN Bit11 0

24 DLYM0 Progr.DelayM ReferencePhase DelayM Bit0 0

25 DLYM1 ReferencePhase DelayM Bit1 0

26 DLYM2 ReferencePhase DelayM Bit2 0

27 DLYN0 Progr.DelayN Feedback Phase DelayN Bit0 0

28 DLYN1 Feedback Phase DelayN Bit1 0

29 DLYN2 Feedback Phase DelayN Bit2 0

30 MANAUT Manual orAutoRef. Manual ReferenceClockSelection[0] 0 A1,B1 36,37 AutomaticReferenceClockSelection[1] 31 REFDEC Freq.Detect ReferenceFrequencyDetectionon [0],off1 0 C8 23 (1) The frequencyappliedtotheDividerN must be smallerthan300 MHz. A sufficientP Dividermust be selectedwiththeFB_MUX to maintainthiscriteria. (2) Ifsettolow,STATUS_REF willbe innormaloperation.Ifsettohigh,STATUS_REF willbe high,even ifno validclockis detected(<2 MHz). Thisisusefulforreferenceinputsfrequencieslessthan2 MHz where thefrequencydetectioncircuitrynormally resetstheSTATUS_REF signaltolow.

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www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 Word 1 PIN AFFECTEDPOWER UPBIT BIT NAME DESCRIPTION/FUNCTION CONDITION BGA QFN

0 C0 RegisterSelection 1

2 OUTSEL0 Output(Yx) ForOutputY0A, Y0B: 1 F1,G1 46,47

SignalingSelectionLVPECL = enabled[1];LVCMOS = enabled[0];

3 OUTSEL1 ForOutputsY1A, Y1B: 1 H2, H3 3,4

LVPECL = enabled[1];LVCMOS = enabled[0];

4 OUTSEL2 ForOutputsY2A, Y2B: 1 H4, H5 7,8

LVPECL = enabled[1];LVCMOS = enabled[0];

5 OUTSEL3 ForOutputsY3A, Y3B: 1 H6, H7 11,12

LVPECL = enabled[1];LVCMOS = enabled[0];

6 OUTSEL4 ForOutputsY4A, Y4B: 1 G8, F8 16,17

LVPECL = enabled[1];LVCMOS = enabled[0];

7 OUT0A0 OutputY0 Mode OutputY0A Mode Bit0 0 F1 46

8 OUT0A1 OutputY0A Mode Bit1 0 F1 46

9 OUT0B0 OutputY0B Mode Bit0 0 G1 47

10 OUT0B1 OutputY0B Mode Bit1 0 G1 47

11 OUT1A0 OutputY1 Mode OutputY1A Mode Bit0 0 H2 3

12 OUT1A1 OutputY1A Mode Bit1 0 H2 3

13 OUT1B0 OutputY1B Mode Bit0 0 H3 4

14 OUT1B1 OutputY1B Mode Bit1 0 H3 4

15 OUT2A0 OutputY2 Mode OutputY2A Mode Bit0 0 H4 7

16 OUT2A1 OutputY2A Mode Bit1 0 H4 7

17 OUT2B0 OutputY2B Mode Bit0 0 H5 8

18 OUT2B1 OutputY2B Mode Bit1 0 H5 8

19 OUT3A0 OutputY3 Mode OutputY3A Mode Bit0 0 H6 11

20 OUT3A1 OutputY3A Mode Bit1 0 H6 11

21 OUT3B0 OutputY3B Mode Bit0 0 H7 12

22 OUT3B1 OutputY3B Mode Bit1 0 H7 12

23 OUT4A0 OutputY4 Mode OutputY4A Mode Bit0 0 G8 16

24 OUT4A1 OutputY4A Mode Bit1 0 G8 16

25 OUT4B0 OutputY4B Mode Bit0 0 F8 17

26 OUT4B1 OutputY4B Mode Bit1 0 F8 17

27 SREF StatusRef. Displaysthestatusofthereferenceclockatthe 0 C8 23 STATUS_REF output[0] Displaystheselectedclock(highforPRI_REF and lowforSEC_REF clock)attheSTATUS_REF output[1]

28 SXOIREF StatusVCXO or SelectsSTATUS_VCXO [0] 0 D8, A8 22,25

I_REF_CP SelectsI_REF_CP [1]whichenableexternal referenceresistorused forchargepump currentand analogPLL lockdetectoutputcurrent.

29 ADLOCK AnalogorDigital SelectsDigitalPLL_LOCK [0] 0 A8 25

Lock SelectsAnalogPLL_LOCK [1] 30 90DIV4 90 degreeshiftdiv- 90 degreeoutputphase shiftindiv-4mode on [1]; 0 Yx Yx 4 off0 31 90DIV8 90 degreeshiftdiv- 90 degreeoutputphase shiftindiv-8mode on [1]; 0 Yx Yx 8 off0 (1) The P 16-Divhas tobe selectedtoobtainthe90 degreephase shift.Ifbit30 orbit31 isset,theDiv-by-16mode isno longeravailable. The outputsareswitchedinpairs.Onlyone bitcan be setata time.Ifbothbitssetto[1]atthesame time,no 90 degreephase shift mode isselected(equaltooff-modesetting). Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:CDCM7005

SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com Word 2 POWER UP PIN AFFECTEDBITBIT DESCRIPTION/FUNCTION CONDITIONAME BGA QFNN

1 C1 RegisterSelection 1

2 CP_DIR CP Direction DeterminesinwhichdirectionCP currentregulates(Reference 0 A4 31

ClockleadstoFeedback Clock– see Figure23) – positiveCP outputcurrent[0]; – negativeCP outputcurrent[1];

3 PRECP Presetchargepump outputvoltagetoVCC_CP/2, on [1],off[0] 0 A4 31

4 CP0 CP Current CP CurrentSettingBit0 0 A4 31

5 CP1 CP CurrentSettingBit1 1 A4 31

6 CP2 CP CurrentSettingBit2 0 A4 31

7 CP3 CP CurrentSettingBit3 1 A4 31

8 PFD0 PFD Pulse PFD PulseWidthPFD Bit0 0 A4 31

Width9 PFD1 PFD PulseWidthPFD Bit1 0 A4 31

10 FBMUX0 FB_MUX Feedback MUX SelectBit0 1

11 FBMUX1 Feedback MUX SelectBit1 0

12 FBMUX2 Feedback MUX SelectBit2 1

13 Y0MUX0 Y0_MUX OutputY0x SelectBit0 1 F1,G1 46,47

14 Y0MUX1 OutputY0x SelectBit1 0 F1,G1 46,47

15 Y0MUX2 OutputY0x SelectBit2 1 F1,G1 46,47

16 Y1MUX0 Y1_MUX OutputY1x SelectBit0 1 H2, H3 3,4

17 Y1MUX1 OutputY1x SelectBit1 0 H2, H3 3,4

18 Y1MUX2 OutputY1x SelectBit2 1 H2, H3 3,4

19 Y2MUX0 Y2_MUX OutputY2x SelectBit0 1 H4, H5 7,8

20 Y2MUX1 OutputY2x SelectBit1 0 H4, H5 7,8

21 Y2MUX2 OutputY2x SelectBit2 1 H4, H5 7,8

22 Y3MUX0 Y3_MUX OutputY3x SelectBit0 1 H6, H7 11,12

23 Y3MUX1 OutputY3x SelectBit1 0 H6, H7 11,12

24 Y3MUX2 OutputY3x SelectBit2 1 H6, H7 11,12

25 Y4MUX0 Y4_MUX OutputY4x SelectBit0 1 G8, F8 16,17

26 Y4MUX1 OutputY4x SelectBit1 0 G8, F8 16,17

27 Y4MUX2 OutputY4x SelectBit2 1 G8, F8 16,17

28 PD Power Down mode on [0],off[1] 1 Yx Yx

29 RESHOL RESET orHOLD Pindefinition:RESET [0]orHOLD [1] 0 H8 14

30 RESET Resetsalldividers[0]-(equaltoRESET pinfunction) 1

31 HOLD 3-statechargepump [0]-(equaltoHOLD pinfunction) 1 A4 31

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www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 Word 3 PIN AFFECTEDBIT POWER UPBIT DESCRIPTION/FUNCTIONNAME CONDITION BGA QFN

0 Registerselection 1

1 Registerselection 1

2 LOCKW 0 Lock Window Lock-detectwindow Bit0 1 A8 25

3 LOCKW 1 Lock-detectwindow Bit1 0 A8 25

4 LOCKC0 Lock Cycles Number ofcoherentlockeventsBit0 0 A8 25

5 LOCKC1 Number ofcoherentlockeventsBit1 1 A8 25

Frequencyoffsetmode onlyforout-of-lockdetection6 FOFF FrequencyOffset 0 A8 25on [1]oroff0

7 RES RESERVED 0 RES RES

8 RES RESERVED 0 RES RES

9 HOLDF HOLD Function Enablesthefrequencyhold-overfunctionon [1],off[0] 0

10 RESERVED 0 RES RES

HOLD functionalwaysactivated[1];(2) Triggeredby analogPLL lockdetectoutputs[0](ifHOLD Trigger11 HOLDTR analogPLL Lock signalissetthenHOLD isactivated; 0Condition ifanalogPLL locksignalisresetthenHOLD isde- activated).

12 RES RESERVED 0 RES RES

13 RES RESERVED 0 RES RES

14 RES RESERVED 0 RES RES

15 RES RESERVED 0 RES RES

16 GTME GeneralTestMode Enable.TestMode isonly 0 enabledifthisbitissetto1.

17 RES RESERVED 0 RES RES

18 RES RESERVED 0 RES RES

19 RES RESERVED 0 RES RES

20 RES RESERVED 0 RES RES

21 RES RESERVED 0 RES RES

22 RES RESERVED 0 RES RES

23 RES RESERVED 0 RES RES

24 RES RESERVED 0 RES RES

25 RES RESERVED 0 RES RES

26 RES RESERVED 0 RES RES

27 RES RESERVED 0 RES RES

28 PFDFC PFD FrequencyControl.Data providedtothePFD 0 D8 22 arefeedthroughtothecorrespondingSTATUS pins(3)

29 RES RESERVED 0 RES RES

30 RES RESERVED 0 RES RES

31 RES RESERVED 0 RES RES

(1) IfFrequencyoffsetmode onlyforout-of-lockdetectionison,theselectedlockdetectwindow isvalidforlockdetect.Independentfrom this,outoflockisvalidifa frequencyoffsetisdetected. (2) HOLD functionalwaysactivatedisrecommended fortestpurposesonly. (3) The maximum frequencyfortheSTATUS_VCXO pinis100 MHz. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:CDCM7005

SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com FUNCTIONAL DESCRIPTION OF THE LOGIC ReferenceDividerM (Word 0)(4) M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Div by Default 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 1 1 4 0 0 0 1 1 1 1 1 1 1 128 Yes 1 1 1 1 1 1 1 1 0 1 1022 1 1 1 1 1 1 1 1 1 0 1023 1 1 1 1 1 1 1 1 1 1 1024 (4) IfthedividervalueisQ, thenthecode willbe thebinaryvalueof(Q–1). VC(X)O Feedback DividerN (Word 0)(1)(2) N11 N10 N0 N8 N7 N6 N5 N4 N3 N2 N1 N0 Div by Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 1 1 1 1 1 1 1 128 Yes 1 1 1 1 1 1 1 1 1 1 0 1 4094 1 1 1 1 1 1 1 1 1 1 1 0 4095 1 1 1 1 1 1 1 1 1 1 1 1 4096 (1) IfthedividervalueisQ, thenthecode willbe thebinaryvalueof(Q–1). (2) The frequencyappliedtotheDividerN must be smallerthan300 MHz. A sufficientP Dividermust be selectedwiththeFB_MUX to maintainthiscriteria.

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www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 Output Mode SelectionforLVCMOS and LVPECL Outputs:Y0A, Y0B, Y1A … Y4B (Word 1)(1) OUTSELx OUTxB1 OUTxB0 LVCMOS OUTxA1 OUTxA0 LVCMOS Default [YxB] [YxA] LVCMOS 0 0 0 Active 0 0 Active 0 0 1 3-state 0 1 3-state 0 1 0 Inverting 1 0 Inverting 0 1 1 Low 1 1 Low OUTSELx OUTxB1 OUTxB0 OUTxA1 OUTxA0 LVCMOS Default [YxA] LVPECL 1 x x x 0 Active Yx 1 x x x 1 3-state (1) IfthedifferentialLVPECL outpute.g.Y0A:Y0B isselected(bit2 ofword 1),thenonlybit7 ofword 1 definestheoutputmode for Y0A:Y0B. The settingsofbit8,bit9,and bit10 ofword 1 arethereforenotrelevanttotheY0A:Y0B. ThisappliesfortheotherLVPECL outputsas well. ReferenceDelay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment (Word 0)(1) DLYM2 /DLYN2 DLYM1 /DLYN1 DLYM0 /DLYN0 Phase Offset Default 0 0 0 0 ps Yes 0 0 1 ±160 ps 0 1 0 ±320 ps 0 1 1 ±480 ps 1 0 0 ±830 ps 1 0 1 ±1130 ps 1 1 0 ±1450 ps 1 1 1 ±1750 ps (1) IfProgr.DelayM isset,allYx outputsarelaggingtothereferenceclockaccordingtothevalueset.IfProgr.IfDelayN isset;allYx outputsareleadingtothereferenceclockaccordingtothevalueset.Above aretypicalvaluesatVCC = 3.3V,Temp = 25°C, PECL- outputrelatetoDiv4mode. PFD Pulse Width Delay (Word 2) PFD1 (1) PFD0 (1) PFD Pulse Width(1)(2) Default(1) 0 0 1.5ns Yes 0 1 3 ns 1 0 4.5ns 1 1 6 ns (1) The PFD pulsewidthdelaygetsaroundthedead zone ofthePFD transferfunctionand reducesphase noiseand referencespurs. (2) TypicalvaluesatV = 3.3VCC ,Temp = 25°C . Lock-DetectWindow (Word 3) LOCKW1 LOCKW0 Phase-OffsetatPFD Input(1) Default 0 0 3.5ns 0 1 8.5ns Yes 1 0 18.5ns 1 1 Frequencyoffset(2) (1) TypicalValuesatVCC = 3.3V,Temp = 25°C. (2) The PLL isout-of-lock(PLL_LOCK setlow)ifa certainfrequencyoffsetbetween referencefrequencyand feedbackfrequency(VCXO) atPFD inputisdetected.The minimum detectablefrequencyoffsetdepends on thedevicesettingand can be calculated: (a) foffsetPDF= fPFD -1/(1/fPFD + PWD) (b) foffsetPFD= detectablefrequencyoffsetatPFD between thereferencefrequency(fREF )and feedbackfrequency(fFB ) (c) fPFD = frequencyatphase-frequencydetectioncircuitry (d) PWD = PFD PulseWidthDelay Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:CDCM7005

SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com Number ofSuccessive Lock Events InsidetheLock DetectWindow (Word 3) LOCKC1 (1) LOCKC0 (1) No. ofSuccessive Lock Events(1) Default(1) 0 0 1 0 1 16 1 0 64 Yes 1 1 256 (1) Thisdoes notapplytoOut-of-Lockcondition. Charge Pump Current(Word 2) CP3 CP2 CP1 CP0 TypicalCharge Pump Current Default 0 0 0 0 0 µA (3-state) 0 0 0 1 200 µA 0 0 1 0 400 µA 0 0 1 1 600 µA 0 1 0 0 800 µA 0 1 0 1 1 mA 0 1 1 0 1.2mA 0 1 1 1 1.4mA 1 0 0 0 1.6mA 1 0 0 1 1.8mA 1 0 1 0 2.0mA Yes 1 0 1 1 2.2mA 1 1 0 0 2.4mA 1 1 0 1 2.6mA 1 1 1 0 2.8mA 1 1 1 1 3 mA FB_MUX Selection(Word 2) FBMUX2 FBMUX1 FBMUX0 SelectedVC(X)O Signalforthe Default Phase Discriminator 0 0 0 Divby 1 0 0 1 Divby 2 0 1 0 Divby 3 0 1 1 Divby 4 1 0 0 Divby 6 1 0 1 Divby 8 Yes 1 1 0 Divby 16(1) 1 1 1 Divby 8 (1) Thisdividersettingdepends on theselectedP-dividermode forthe“Div-by-16”divider.Inthedefaultmode (afterpower up),Div-by-16 isselected.Butifbit30 orbit31 ofword 1 issetto[1],thentheDiv-by-4and 90 degreephase shiftorDiv-by-8and 90 degreephase shiftisselected. Yx_MUX – Output DividerSelectionforY0,Y1,Y2,Y3,Y4 (Word 2) YxMUX2 YxMUX1 YxMUX0 SelectedDividedV(C)XO Signalforthe Default Yx Outputs 0 0 0 Divby 1 0 0 1 Divby 2 0 1 0 Divby 3

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PRI_REF SEC_REF STATUS_REF PRI_SEC_CLK 1 2 1 2 3 4 Internal Reference□Clock Primary□Clock Secondary□Clock Primary□Clock CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 YxMUX2 YxMUX1 YxMUX0 SelectedDividedV(C)XO Signalforthe Default Yx Outputs 0 1 1 Divby 4 1 0 0 Divby 6 1 0 1 Divby 8 allYx 1 1 0 Divby 16(1) 1 1 1 Divby 8 (1) Thisdividersettingdepends on theselectedP-dividermode forthe“Div-by-16”divider.Inthedefaultmode (afterpower up),Div-by-16 isselected.Butifbit30 orbit31 ofword 1 issetto[1],thentheDiv-by-4and 90 degreephase shiftorDiv-by-8and 90 degreephase shiftisselected. FEATURE DESCRIPTION Automatic/ManualReferenceClock Switching The CDCM7005 supportstwo referenceclockinputs,theprimaryclockinput,PRI_REF, and thesecondaryclock input,SEC_REF. The clockscan be selectedmanuallyorautomatically.The respectivemode isselectedby the dedicatedSPI registerbit(Word 0,Bit30). Inthemanual mode, theexternalREF_SEL signalselectsone ofthetwo inputclocks: REF_SEL [1]-> primaryclockisselected REF_SEL [0]-> secondaryclockisselected In the automaticmode, the primaryclockisselectedby defaulteven ifboth clocksare available.In case the primaryclockisnotavailableor fails,thentheinputswitchestothesecondaryclockas longuntiltheprimary clockisback.Figure15 shows theautomaticclockselection. NOTE: PRI_REF isthepreferredclockinput. Figure15. BehaviorofSTATUS_REF and PRI_SEC_CLK Intheautomaticmode, thefrequenciesofbothclocksignalshave tobe similar,butmay differby up to20%. The phase oftheclocksignalcan be any. The clockinputcircuitryisdesigntosuppressglitchesduringswitchingbetween theprimaryand secondaryclock inthemanual and automaticmode. Thisavoidsan undefinedswitchingofthefollowingcircuitries. The phase oftheoutputclockslowlyfollowsthenew inputphase.There willbe no phase-jumpattheoutput. How quickthephase adjustmentisdone depends on theselectedloopparameter,i.e.,ata loopbandwidthof <100 Hz; the phase adjustmentcan takeseveralms. There isno phase build-outfunctionsupported(likein SONET/SDH applications). Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:CDCM7005

t(lockdetect) Selected□REF□at□PFD (clock□fed□through□M□Divider□and□M□Delay) VCXO_IN□at□PFD (clock□fed□through□N□Divider□and□N□Delay) T0063-01 PRI_REF SEC_REF Internal Reference□Clock Yx□Output PRI_SEC_CLK 2 3 4 Primary□Clock Secondary□Clock Primary□Clock CDCM7005 SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com Figure16. Phase Approach ofOutput toNew ReferenceClock PLL Lock forAnalog and DigitalDetect The CDCM7005 supportstwo PLL lockindications:thedigitallocksignalortheanaloglocksignal.Both signals indicatelogichigh-levelatPLL_LOCK ifthePLL locksaccordingtheselectedlockcondition. PLL Lock/Out-of-LockDefinition The PLL islocked(sethigh),ifthe risingedge of the ReferenceClock (PRI_REF or SEC_REF clock)and Feedback Clock (VCXO_IN clock)at the PFD (phase frequencydetect)are insidea predefinedlockdetect window,orifno frequencyoffsetappears,fora pre-definednumber ofsuccessiveclockcycles. The PLL isout-of-lock(setlow),iftherisingedge oftheReferenceClock(PRI_REF or SEC_REF clock)and Feedback Clock(VCXO_IN clock)atthePFD are outsidethepredefinedlockdetectwindow or ifa frequency offsetappears. Both,thelockdetectwindow and thenumber ofsuccessiveclockcyclesareuserdefinable(Word 3,Bit2-6). Figure17. Lock DetectWindow The lockdetectwindow describesthemaximum allowedtimedifferenceforlockdetectbetween therisingedge ofPRI_REF or SEC_REF and VCXO_IN. The timedifferenceisdetectedatthephase frequencydetector.The risingedge of PRI_REF or SEC_REF istakenas reference.The risingedge of VCXO_IN isoutsidethe lock detectwindow ifthereisa phase displacementofmore than+0.5× t(lockdetect)or-0.5x t(lockdetect).

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Power_Down Lock_Out Lock_In 100 A (Lock) /c109 100 A (Out-of-Lock) /c109 80k/c87 5pF C PLL_LOCK Output Lock t V =□0.55□Vhigh CC VCC V =□0.35□Vlow CC Out-of-Lock VOut V =□1/C I tOut /c180 /c180 Example: and□V =□V =□0.55 Vcc□=□1.8V t□=□164 s /c109 /c180 /c179 /c109 CC high out CDCM7005 S0080-01 Power_Down Lock_Out Lock_In 80k/c87 5pF PLL_LOCK Output CDCM7005 Lock t Digital□Lock□Detection V =□0.55□Vhigh CC V =□0.35□Vlow CC Out-of-Lock VOut CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 Digitalvs Analog Lock Figure18 and Figure19 show the circuitforthe digitaland analog lock.The analog lockoperateswithan externalloadcapacitor. When selectingthedigitalPLL lockoption,PLL_LOCK willpossiblyjitterseveraltimesbetween lockand outof lockuntila stablelockisdetected.A singlelow-to-highstepcan be reachedwitha wide lockdetectwindow and highnumber ofsuccessiveclockcycles.PLL_LOCK returnstooutoflockifjustone cycleisoutsidethelock detectwindow ora frequencyoffsetoccurs. Figure18. DigitalLock-Detect When selectingtheanalogPLL Lock option,thehigh-pulsesloadtheexternalcapacitorviatheinternal110-µA currentsourceuntillogichigh-levelisreached.Therefore,more timeisneeded to detectlogichighlevel,but jitteringofPLL_LOCK willbe suppressedincase ofdigitallock.The timePLL_LOCK needs toreturntooutof lockdepends on thelevelofVOut,when thecurrentsourcestartstounloadtheexternalcapacitor. Figure19. Analog Lock-Detect Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:CDCM7005

Reference□Clock VCXO□Clock Y-Output□div4 Y-Output□div4 (90□deg□shift) Y-Output□div8 (90□deg□shift) 90□deg 90□deg Y-Output□div8 90□deg90□deg LVCMOS□Outputs LVPECL Outputs B0058-01 PECL Input VCXO_IN VCXO_IN P Divider ÷□3 ÷□4 ÷□6 /8÷□8 ÷□16 ÷□1 ÷□2 ÷□4 ÷□8 90o90o P16-Div CDCM7005 SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com DifferentialLVPECL Outputs and Single-EndedLVCMOS Outputs The CDCM7005 supportsup to 5 × LVPECL outputsor 10 × LVCMOS/LVTTL outputsor any combinationof these.The single-endedLVCMOS outputsare arrangedinpairswhich mean both outputsof a LVCMOS pair have thesame frequencybutcan separatelybe disabledor inverted.The power up outputarrangementisfive LVPECL (defaultsetting). The LVPECL outputsaredesignedtoterminateintoa 50-Ω loadtoVCC – 2 V. The LVCMOS outputssupports the standardLVCMOS load (see Figure12).The LVPECL and LVCMOS outputscan be enabled (normal operation)ordisabled(3-state). Inaddition,theoutputphase can be shiftedby 90 degreeswhen usingtheadditionaldiv-by-4ordiv-by-8mode oftheP16-Div(seeFigure20).Inthedefaultmode (afterpower up),thediv-by-16mode oftheP16-Divisactive. To change ittoa 90 degreephase shift,bit30 orbit31 ofword 1 has tobe programmed accordingly.The P 16- Divhas tobe selectedviathededicatedYxMUX toobtainthe90 degreephase shift.The outputsareswitchedin pairs.When selectingthe90 degreephase shiftmode, thediv-by-16functionswillno longerbe available.The 90 degreephase shiftedsignalislaggingtothenon-shiftedsignal. Figure20. 90 Degree Phase ShiftOption ofP-Divider The followingdiagramshows theLVCMOS and LVPECL outputsignalwhen 90 degreephase shiftison. Figure21. Output SwitchingDiagram

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www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 Inaddition,theLVCMOS supportsdisabled-to-lowand 180 degreeoutputphase shiftforeach outputindividually. When selectingthe180 degreephase shifttogetherwiththe90 degreephase shift,therespectiveoutputshas a totalphase shiftof270 degree(seeTable2 ). Table2.LVCMOS Phase ShiftOptions Phase P-Divider 180°Phase-Shift P16-Div-Function 0° Any P-Divider No div-by-16 90° P16-Div No div-by-4ordiv-by-8 180° Any P-Divider Yes div-by-16 270° P16-Div Yes div-by-4ordiv-by-8 IftheP16-Divisselectedby theFB_MUX and div-by-4or div-by-8isactive,the90 degree phase shiftedclock willbe synchronizedtoPRI_REF or SEC_REF. Thismeans alloutputsYxx,which are switchedtodiv-by-4or div-by-8,are inphase to PRI_REF or SEC_REF. Allotheroutputsare 90 degree phase shiftedwithleading phase. Frequency Hold-OverMode The HOLD functionisa usefulfeaturewhich helpsthe designerto improvethe system reliability.The HOLD functionholdsthe outputfrequencyincase the inputreferenceclockfailsor isdisrupted.DuringHOLD, the chargepump isswitchedoff(3-state)freezingthelastvalidoutputfrequency.The holdfunctionwillbe released aftera validreferenceclockisback.For properHOLD function,the analogPLL lockdetectmode has to be active. The followingregistersettingsareinvolvedwiththeHOLD function:

Lock DetectWindow (Word 3, Bit2, 3, 6): Definesthe window inns insidethe lockisvalid.The sizeis 3.5ns,8.5ns,18.5ns,ora certainfrequencyoffset.Lock issetifreferenceclockand thefeedbackclockare insidethispredefinedlock-detectwindow fora pre-selectednumber ofsuccessivecyclesor ifno frequency offsetappears.
Out-of-Lock:Definestheout-of-lockcondition:Ifthereferenceclockand thefeedbackclockatthePFD are outsidethepredefinedLock DetectWindow orifa certainfrequencyoffsetoccurs.
Cycle-Slip(Word 3, Bit6): A Frequency offsetoccurs ifa certainfrequencyoffsetbetween reference frequencyand feedbackfrequency(VCXO) at PFD inputisdetected.The minimum detectablefrequency offsetdepends on thedevicesettingand can be calculated: foffsetPDF= fPFD -1/(1/fPFD + PWD) where
foffsetPFD= detectablefrequencyoffsetatPFD between thereferencefrequency(fREF )and feedbackfrequency (fFB )
fPFD = frequencyatphase-frequencydetectioncircuitry
PWD = PFD PulseWidthDelay (1)
Number of Clock Cycles(Word 3, Bit4, 5): Definesthe number of successivePFD cycleswhich have to occurinsidethelockwindow tosetLock detect.Thisappliesnotforout-of-lockcondition.
Hold-Function(Word 3,Bit9):SelectsHOLD function(seemore detailsbelow).
Hold-Trigger(Word 3,Bit11):DefineswhethertheHOLD functionisalwaysactivated(Bit11 = [1])orwhether itisdependenton thestateoftheanalogPLL lockdetectoutput(Bit11 = [0]).Inthelattercase,HOLD is activated,iflockisset(high)and de-activatedifLock isreset(low).
AnalogPLL Lock Detect(Word 1,Bit29):Analoglockoutputchargesordischargesan externalcapacitorwith everyvalidlockcycle.The timeconstantforLock detectcan be setby thevalueofthecapacitor. The CDCM7005 supportstwo typesofHOLD functions,one externalcontrollableHOLD mode and one internal mode, HOLD. WiththeexternalHOLD functionthechargepump can directlybe switchedinto3-state(pinH8 [BGA] orpin14 [QFN] can be programmed forHOLD [Word 2,Bit29]).ThisfunctionisalsoavailableviaSPI register(Word 2, Bit31). Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:CDCM7005

Out-of-Lock? PLL-Lock Output Set? 3-State Charge-Pump Reference Clock Back?

64 PFD

Charge-Pump is switched into 3-State. P-divider and Yx output are at normal operation. The Charge-Pump remains in 3-State until the Reference Clock is back. The 1st valid Reference Clock at the PFD releases the Charge-Pump. The PLL acquire 64 lock cycles to phase align to the input clock. Frequency Hold-Over Function works in combination with the Analog Lock-Detect function only! Start PLL is out-of-lock if the phase difference of Reference Clock and Feedback Clock at PFD are outside the predefined Lock-Detect-Window or if a frequency offset occurs. PLL has to be in LOCK to start HOLD-Function. (The Analog Lock output is not reset by the first Out-of- Lock event. It stays ‘High’ depending on the analog time delay (output C-load). The time delay must be long enough to assure proper HOLD function) (The ‘PLL-Lock Output Set?’ enquiry can be bypassed by setting the HOLDTR bit to [1] (Word 3, Bit 11) CDCM7005 SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com Iflogiclow isappliedto the HOLD pin,the charge pump willbe switchedto 3-state.Afterthe HOLD pinis released,thechargepump isswitchedback intonormaloperationwiththenextvalidreferenceclockcycleat PRI_REF orSEC_REF and thenextvalidfeedbackclockcycleatthePFD. DuringHOLD, theP dividerand all outputsYx areatnormaloperation. HOLD-Over-Function:The PLL has tobe inlocktostarttheHOLD function.Itswitchesthechargepump into3- Statewhen an out-of-lockeventoccurs.Itleavesthe 3-statecharge pump statewhen the referenceclockis back.Then itstartsa lockingsequence of64 cyclesbeforeitgoes back tothebeginningoftheHOLD-over loop. The dedicatedlookingsequence and a digitalphase alignmentenablea fastlock. Figure22. Frequency HOLD-Over Function

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PFD□Pulse Width□Delay PFD□Pulse Width□Delay 0□V VCC PRI_REF□or□SEC_REF Clock□Fed□Through□the M□Divider□and□Delay VCXO_IN□Clock□Fed□Through the□N□Divider□and□Delay Default□State) V (Internal□Signal)(PFD1) V (Internal□Signal)(PFD2) CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 Charge Pump PresettoVCC_CP/2 The presetchargepump toVCC_CP/2 isa usefulfeaturetoquicklysetthecenterfrequencyoftheVC(X)O after powerup orreset.The adequatecontrolvoltagefortheVC(X)O willbe providedtothecharge-pumpoutputby an internalvoltagedividerof1 kΩ/1kΩ toVCC_CP and GND (VCC_CP/2). Thisfeaturehelpstogettheinitialfrequencyaccuracy,i.e.requiredatCPRI (Common PublicRadio Interface)or OBSAI (Open Base StationArchitectureInitiative). The presetchargepump toVCC_CP/2 can be setand resetby SPI register(word2,bit3).Thisfeaturemust be disabledforPLL locking. Charge Pump CurrentDirection The directionof the charge pump (CP) currentpulsecan be changed by the SPI register(word 2, bit2).It determinesin which directionthe CP currentregulates(referenceclock leads to feedback clock).Most applicationsuse thepositiveCP outputcurrent(power-upcondition)because oftheuse ofa passiveloopfilter. The negativeCP currentisusefulwhen usingan activeloopfilterconceptwithinvertingoperationalamplifier. Figure23 shows theinternalPFD signaland thecorrespondingCP current. NOTE: The purposeofthePFD plusewidthdelayistoimprovespurioussuppression. Figure23. Charge Pump CurrentDirection(VCXO and VCO Support) Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:CDCM7005

VCXO Low-Pass□Filter CDCM7005 245.76MHz Gain□=□21.3kHz/V PECL_OUT_B PRI_REF VCXO_IN YnA YnBVCXO_IN CTRL_DATA CTRL_LE CTRL_CLK V_CTRL CP_OUT PLL_LOCK STATUS_REF STATUS_VCXO PECL_OUT SPI VOC VOC R 130/c87 R 82/c87 R 150/c87 R 50/c87 R 82/c87 R 150/c87 R 50/c87 160/c87 R 130/c87 4.7k/c87 100nF

22 F/c109

Phase□Noise□Reference□Circuit□(See□the□EVM) CDCM7005 SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com

APPLICATION INFORMATION

Phase Noise ReferenceCircuit Figure24. TypicalApplicationsDiagram With PassiveLoop Filter

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f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 10 100 1k 100k 10M 1M10k L(f) − dB G009 CDCM7005 in PLL−Closed Loop CDCM7005 EVM REF_IN: AgilentE8257C−61.44MHz VCXO: Toyocom TCO−21 11 245.76MHz CDCM7005 Out is Y0A: 61.44MHz Loop bandwidth ~ 30Hz Date: 30. Mar 2005 Phase-Noise Analyzer E5052A CDCM7005 Ref_Clk LPF VCXO Phase Jitter (rms) − 1kHz − 10MHz LVPECL 61.44MHz (282fs) Input−Clk 61.44MHz (769fs) VXCO 245.76MHz (581fs) LVCMOS 61.44MHz (230fs) CDCM7005 www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 Phase Noise Performance REF_IN PHASE VCXO PHASE Yx PHASE NOISE NOISE NOISE AT 30.72MHz PARAMETER (1) TEST CONDITIONS UNITAT 30.72MHz AT 245.76MHz LVCMOS LVPECL TYP (2) TYP (2) phn10 Phase noiseat10 Hz –109 –75 –104 –100 dBc/Hz phn100 Phase noiseat100 Hz –125 –97 –116 –116 dBc/Hz Y = 30.72MHz; fPFD = 200phn1k Phase noiseat1 kHz –134 –117 –140 –140 dBc/HzkHz,Loop BW = 20 Hz, phn10k Phase noiseat10 kHz Feedback Divider= 8 x 128 –136 –138 –153 –152 dBc/Hz (N x P),fREF_IN = 30.72MHz,phn100k Phase noiseat100 kHz –138 –148 –156 –153 dBc/HzM-Divider= 128,ICP = 2 mA phn1Mk Phase noiseat1 MHz –144 –148 –156 –153 dBc/Hz phn10M Phase noiseat10 MHz –144 –148 –156 –153 dBc/Hz PLL StabilizationTime tstabi PLL stabilizationtime(3) Y = 30.72MHz, fPFD = 200 400 ms kHz,Loop BW = 20 Hz, Feedback Divider= 8 x 128 (N x P),fREF_IN = 30.72MHz, M-Divider= 128,ICP = 2 mA (1) Outputphase noiseisdependenton thenoiseoftheREF_IN clockand VCXO clocknoisefloor.The phase noiseperformanceofthe BGA and theQFN package isequal.The phase noisemeasurements were takenwiththeCDCM7005 EVM and CDCM7005 SPI default settings. (2) The typicalstabilizationtimeisbased on theabove applicationexample.The stabilizationcriterionwas a stablehighlevelof PLL_LOCK. (3) Forfurtherexplanations,as wellas phase noise/jittertestresultsusingvariousVCXOs, see applicationnoteSCAA067 . Figure25. Phase Noise (61.44-MHzREF_IN and 61.44-MHz Output Frequency) Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:CDCM7005

(PLL) 16-Bit DAC 16-Bit DAC DAC5687 FIRFIR DDC DUC RF I I Q Q 14-Bit ADC ADS5423 3.84□MHz VCXO 491.52□MHz 61.44MHz 491.52□MHz122.88□MHz122.88□MHz Duplexer LO1 IF1 LNA /c83 PA FIRFIR ToBB FromBB GC5016 GC5016 THS4509 TRF3750 (PLL) TRF3702 CDCM7005 CDCM7005 SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com In-BandNoise Performance Table3. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT pnin-band In-bandphase noisetestconditions –95 dBc/Hz Y = 900 MHz, fPFD = 400 kHz,Looppnf400 Phase noisefloorat400 kHz fPFD ,in-band –162 dBc/HzBW = 27 kHz,Feedback Divider= 8 x 282noise– 20log(feedbackdiv)(1) (N x P),fREF_IN = 10 MHz; M-Divider= 25,ICP = pnf1 Phase noisefloorat1 Hz fPFD ,in-band –218 dBc/Hz3 mA noise– 20log(feedbackdiv)– 10log(fPFD )(2) (1) The synthesizerphase noisefloorcan be estimatedby measuringthein-bandnoiseattheoutputoftheCDCM7005 and subtracting 20log(FeedbackDivider)N (incase ofCDCM7005 itistheN+P divider).The calculatedphase noisefloorstillbased on thePFD update frequency,intheabove specification,is400 kHz. (2) The in-bandnoisecan alsobe normalizedtoa comparisonfrequencyof1 Hz.The resultingphase noiseflooris:pnfloor= PNmeasured -20log(N+P)-10log(fPFD ) where: pnNfloor= normalizedphase noisefloorindBc/Hz PNmeasured = in-bandphase noisemeasurement indBc/Hz 20log(N+P)= dividerratiooffeedbackloop 10log(fPFD )= PFD updatefrequencyinHz APPLICATION INFORMATION ON THE CLOCK GENERATION FOR INTERPOLATING DACS WITH THE CDCM7005 The CDCM7005, withitsspecifiedphase noiseperformance,isan idealsamplingclockgeneratorforhighspeed ADCs and DACs. The CDCM7005 isespeciallyofinterestforthenew highspeed DACs, whichhave integrated interpolationfilter.Such DACs achievesamplingratesup to500 MSPS. Thishighdataratecan typicallynotbe supportedfrom the digitalsidedrivingthe DAC (e.g.,DUC, digitalup-converter).Therefore,one approach to interfacetheDUC totheDAC istheintegrationofan interpolationfilterwithintheDAC toreducethedatarateat the digitalinputof the DAC. In 3G systems,forexample,a common samplingrateof a highspeed DAC is 491.52 MSPS. With a fourtimes interpolationof the digitaldata,the requiredinputdata rateresultsinto 122.88MSPS, whichcan be supportedeasilyfromthedigitalside.The DUC GC5016, whichsupportsup tofour WCDMA carriers,providesa maximum outputdatarateof150 MSPS. An example isshown inFigure26,where theCDCM7005 suppliestheclocksignalfortheDUC/DDC and ADC/DAC. Figure26. CDCM7005 as a Clock GeneratorforHigh Speed ADCs and DACs

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www.ti.com SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 The generationofthetwo requiredclocksignals(datainputclock,clockforDAC) forsuch an interpolatingDAC can be done in differentways. The recommended way isto use the CDCM7005, which generatesthe fast samplingclockfortheDAC from thedatainputclocksignal.The DAC5687 demands thattheedges ofthetwo inputclocksmust be phase alignedwithin±500 ps forlatchingthedataproperly.Thisphase alignmentiswell achievedwiththeCDCM7005, whichassuresa maximum skew of70 ps ofthedifferentdifferentoutputstoeach other. AC-Coupled InterfacetoADC/DAC AnotheradvantageofthisclocksolutionisthattheADC orDAC can be drivendirectlyinan ac-couplinginterface as shown in Figure27, withan externalterminationin a differentialconfiguration.There is no need fora transformertogeneratea differentialsignalfroma single-endedclocksource. Figure27. DrivingDAC or ADC With PECL Output oftheCDCM7005

REVISION HISTORY

Changes from Original(June 2005)toRevisionA Page Changes from RevisionA (June 2005)toRevisionB Page Changes from RevisionB (October2005)toRevisionC Page Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:CDCM7005

SCAS793E –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com Changes from RevisionC (December 2007)toRevisionD Page

Changed VCC pintextFrom:3.3-Vsupply.Thereisno internalconnectionbetween VCC and AV CC .Itis recommended thatAV CC use itsown supplyfilter.To:3.3-Vsupply.VCC and AV CC shouldalwayshave thesame
Added texttotheCTRL_LE pin-Unused orfloatinginputsmust be tiedtoproperlogiclevel.A 20kΩ orlarger
Added texttotheCTRL_CLK pin-Unused orfloatinginputsmust be tiedtoproperlogiclevel.A 20kΩ orlarger
Added texttotheCTRL_DATA pin-Unused orfloatinginputsmust be tiedtoproperlogiclevel.A 20kΩ orlarger
Added texttothePD pin-Itisrecommended toramp up thePD withthesame timeas VCC and AV CC orlater.The
Added texttotheSPI CONTROL INTERFACE section-Unused orfloatinginputsmust be tiedtoproperlogiclevel.
Added texttotheSPI CONTROL INTERFACE section-Itisrecommended toprogramWord 0,Word 1,Word 2 Changes from RevisionD (August 2009)toRevisionE Page

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www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples CDCM7005RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 CDCM7005 CDCM7005RGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 CDCM7005 CDCM7005RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 CDCM7005 CDCM7005RGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 CDCM7005 CDCM7005ZVA ACTIVE BGA ZVA 64 348 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR -40 to 85 CDCM7005 CDCM7005ZVAR ACTIVE BGA ZVA 64 1000 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR -40 to 85 CDCM7005 CDCM7005ZVAT ACTIVE BGA ZVA 64 250 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR -40 to 85 CDCM7005 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

www.ti.com 11-Apr-2013 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CDCM7005 :

Space: CDCM7005-SP NOTE: Qualified Version Definitions:
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Feb-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCM7005RGZR VQFN RGZ 48 2500 336.6 336.6 28.6 CDCM7005RGZT VQFN RGZ 48 250 336.6 336.6 28.6 CDCM7005ZVAR BGA ZVA 64 1000 336.6 336.6 28.6 CDCM7005ZVAT BGA ZVA 64 250 336.6 336.6 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 8-Feb-2013 Pack Materials-Page 2

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Product Information

CDCM7005RGZR specifications and overview.

Summary

3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

Description

3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

Source title CDCM7005RGZR Datasheet(PDF) - Texas Instruments

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