CDCM6208V2GRGZT

Texas Instruments

CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CDCM6208V2G SNAS682 –MARCH 2016 CDCM6208V2G2:8ClockGenerator,JitterCleanerwithFractionalDividers

1 Features

1• Superior Performance with Low Power: – Low Noise Synthesizer (265 fs-rms Typical Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms Typical Jitter) – 0.5 W Typical Power Consumption – High Channel-to-Channel Isolation and Excellent PSRR – Device Performance Customizable Through Flexible 1.8 V, 2.5 V and 3.3 V Power Supplies, Allowing Mixed Output Voltages

Flexible Frequency Planning: – 4x Integer Down-divided Differential Clock Outputs Supporting LVPECL-like, CML, or LVDS-like Signaling – 4x Fractional or Integer Divided Differential Clock Outputs Supporting HCSL, LVDS-like Signaling, or Eight CMOS Outputs – Fractional Output Divider Achieve 0 ppm to < 1 ppm Frequency Error and Eliminates need for Crystal Oscillators and Other Clock Generators – Output frequencies up to 800 MHz
Two Differential Inputs, XTAL Support, Ability for Smart Switching
SPI, I2C™ , and Pin Programmable
Professional user GUI for Quick Design Turnaround
7 x 7 mm 48-QFN package (RGZ)
-40 °C to 85 °C temperature range

2 Applications

Base Band Clocking (Wireless Infrastructure)
Networking and Data Communications
Keystone C66x Multicore DSP Clocking
Storage Server, Portable Test Equipment,
Medical Imaging, High End A/V

3 Description

The CDCM6208V2G is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V2G also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V2G can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CDCM6208V2G VQFN (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematics

8.9 Single Ended Input Characteristics (PRI_REF,

8.10 Differential Input Characteristics (PRI_REF,

8.12 Single Ended Output Characteristics (STATUS1,

8.15 LVPECL (High-Swing CML) Output

8.17 LVDS (Low-Power CML) Output Characteristics. 14

8.19 Output Skew and Sync to Output Propagation Delay

12.1 Power Rail Sequencing, Power Supply Ramp Rate,

15 Mechanical, Packaging, and Orderable

5 Revision History

March 2016 * Initial release.

VD D_PLL1 R ESETN/PWR PD N SYNC N Y7_ N Y7_ P 42 41 VDD_Y7 Y6_ N Y6_ P VDD_Y6 VDD_Y5 STATUS0 STATUS1/PIN 0 ELF 17 18 19 20 21 22 23 24 Y0_P Y1_N Y1_P VDD _Y0 _Y1 VDD _Y2 _Y3 Y2_P Y2_N VDD _Y0 _Y1 SDI/ SDA/PIN1 SDO /AD 0/PIN2 SCS/AD 1/PIN3 REF _SEL SCL /PIN4 1 1 14 15 16 Y5_ P PRI_REFN Y0_N PRI_REFP SI_MODE 0 Y4_ N Y3_N R EG_C AP VD D_VCO SEC_REFP SEC_REFN Y3_P VDD _Y2 _Y3 Y4_ P VDD_Y4 Y5_ N VD D_PLL2SI_MODE1D VDD DVDD VDD VDD_Y 2_Y3 VDD_Y4 VDD_Y5 VDD_Y6 VDD_Y7 VDD _PRI_REF VDD_SECI_REF VDD_SEC_REF _Y0 _Y1 VDD_PRI_REF CDCM6208V2G www.ti.com SNAS682 –MARCH 2016 Product Folder Links: CDCM6208V2G Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated (1) If Secondary input buffer is disabled (Register 4 Bit 5 = 0), it is possible to connect VDD_SEC_REF to GND.

6 Description (continued)

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k - 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k - 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency. In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k - 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V2G is packaged in a small 48-pin 7 mm x 7 mm QFN package.

7 Pin Configuration and Functions

48 Pin VQFN

NAME NO. PRI_REFP 8 Input Universal Primary Reference Input + PRI_REFN 9 Input Universal Primary Reference Input – VDD_PRI_REF 7 PWR Analog Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to VDD_SEC_REF. SEC_REFP 11 Input Universal Secondary Reference Input + SEC_REFN 12 Input Universal Secondary Reference Input – VDD_SEC_REF 10 PWR Analog Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to VDD_PRI_REF(1).

SNAS682 –MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O TYPE DESCRIPTION NAME NO. REF_SEL 6 Input LVCMOS 50kΩ pull-up Manual Reference Selection MUX for PLL. In SPI or I2C mode the reference selection is also controlled through Register 4 bit 12. REF_SEL = 0 (≤ VIL): selects PRI_REF REF_SEL = 1 (≥ VIH): selects SEC_REF (when Reg 4.12 = 1). See Table 35 for detail. ELF 41 Output Analog External loop filter pin for PLL Y0_P 14 Output Universal Output 0 Positive Terminal Y0_N 15 Output Universal Output 0 Negative Terminal Y1_P 17 Output Universal Output 1 Positive Terminal Y1_N 16 Output Universal Output 1 Negative Terminal VDD_Y0_Y1 (2 pins) 13, 18 PWR Analog Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V or 3.3 V Y2_P 20 Output Universal Output 2 Positive Terminal Y2_N 21 Output Universal Output 2 Negative Terminal Y3_P 23 Output Universal Output 3 Positive Terminal Y3_N 22 Output Universal Output 3 Negative Terminal VDD_Y2_Y3 (2 pins) 19, 24 PWR Analog Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V or 3.3 V Y4_P 26 Output Universal Output 4 Positive Terminal Y4_N 25 Output Universal Output 4 Negative Terminal VDD_Y4 27 PWR Analog Supply pin for output 4 to set between 1.8 V, 2.5 V or 3.3 V Y5_P 29 Output Universal Output 5 Positive Terminal Y5_N 28 Output Universal Output 5 Negative Terminal VDD_Y5 30 PWR Analog Supply pin for output 5 to set between 1.8 V, 2.5 V or 3.3 V Y6_P 32 Output Universal Output 6 Positive Terminal Y6_N 33 Output Universal Output 6 Negative Terminal VDD_Y6 31 PWR Analog Supply pin for output 6 to set between 1.8 V, 2.5 V or 3.3 V Y7_P 35 Output Universal Output 7 Positive Terminal Y7_N 36 Output Universal Output 7 Negative Terminal VDD_Y7 34 PWR Analog Supply pin for output 7 to set between 1.8 V, 2.5 V or 3.3 V VDD_VCO 39 PWR Analog Analog power supply for PLL/VCO; This pin is sensitive to power supply noise; The supply of this pin and the VDD_PLL2 supply pin can be combined as they are both analog and sensitive supplies VDD_PLL1 37 PWR Analog Analog Power Supply Connections VDD_PLL2 38 PWR Analog Analog Power Supply Connections; This pin is sensitive to power supply noise; The supply of VDD_PLL2 and VDD_VCO can be combined as these pins are both power-sensitive, analog supply pins DVDD 48 PWR Analog Digital Power Supply Connections; This is also the reference supply voltage for all control inputs and must match the expected input signal swing of control inputs. GND PAD PWR Analog Power Supply Ground and Thermal Pad STATUS0 46 Output LVCMOS Status pin 0 (see Table 6 for details) STATUS1/PIN0 45 Output/ Input LVCMOS no pull resistor STATUS1: Status pin in SPI/I2C modes. For details see Table 4 for pin modes and Table 6 for status mode. PIN0: Control pin 0 in pin mode. SI_MODE1 47 Input LVCMOS 50kΩ pull-up Serial Interface Mode or Pin mode selection. SI_MODE[1:0]=00: SPI mode; SI_MODE[1:0]=01: I2C mode; SI_MODE[1:0]=10: Pin Mode (No serial programming); SI_MODE[1:0]=11: RESERVED SI_MODE0 1 Input LVCMOS 50kΩ pull-down SDI/SDA/PIN1 2 Input/ Output LVCMOS in Open drain out LVCMOS in no pull resistor SDI: SPI Serial Data Input SDA: I2C Serial Data (Read/Write bi-directional), open drain output; requires a pull- up resistor in I2C mode; PIN1: Control pin 1 in pin mode

www.ti.com SNAS682 –MARCH 2016 Product Folder Links: CDCM6208V2G Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O TYPE DESCRIPTION NAME NO. (2) Note: the device cannot be programmed in I2C while RESETN is held low. SDO/AD0/PIN2 3 Output/ Input LVCMOS out LVCMOS in LVCMOS in no pull resistor SDO: SPI Serial Data AD0: I2C Address Offset Bit 0 input PIN2: Control pin 2 in pin mode SCS/AD1/PIN 3 4 Input LVCMOS no pull resistor SCS: SPI Latch Enable AD1: I2C Address Offset Bit 1 input PIN3: Control pin 3 in pin mode SCL/PIN4 5 Input LVCMOS no pull resistor SCL: SPI/I2C Clock PIN4: Control pin 4 in pin mode RESETN/PWR 44 Input LVCMOS 50kΩ pull-up In SPI/I2C programming mode, external RESETN signal (active low). RESETN = V IL: device in reset (registers values are retained) RESETN = V IH: device active. The device can be programmed via SPI while RESETN is held low (this is useful to avoid any false output frequencies at power up). (2) In Pin mode this pin controls device core and I/O supply voltage setting. 0 = 1.8 V, 1 = 2.5/3.3 V for the device core and I/O power supply voltage. In pin mode, it is not possible to mix and match the supplies. All supplies should either be 1.8 V or 2.5/3.3 REG_CAP 40 Output Analog Regulator Capacitor; connect a 10 µF cap with ESR below 1 Ω to GND at frequencies above 100 kHz PDN 43 Input LVCMOS 50kΩ pull-up Power Down Active low. When PDN = VIH is normal operation. When PDN = VIL, the device is disabled and current consumption minimized. Exiting power down resets the entire device and defaults all registers. It is recommended to connect a capacitor to GND to hold the device in power-down until the digital and PLL related power supplies are stable. See section on power down in the application section. SYNCN 42 Input LVCMOS 50kΩ pull-up Active low. Device outputs are synchronized on a low-to-high transition on the SYNCN pin. SYNCN held low disables all outputs.

SNAS682 –MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute— maximum— rated conditions for extended periods may affect device reliability.

8 Specifications

8.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX UNIT Supply Voltage Range, VDD_PRI, VDD_SEC, VDD_Yx_Yy, VDD_PLL[2:1], DVDD -0.5 4.6 V Input Voltage Range CMOS control inputs, VIN -0.5 4.6 and V DVDD+ 0.5 V Input Voltage Range PRI/SEC inputs 4.6 and VVDDPRI.SEC+ 0.5 V Output Voltage Range, VOUT -0.5 VYxYy+ 0.5 V Input Current, IIN 20 mA Output Current, IOUT 50 mA Junction Temperature, TJ 125 °C Storage temperature range, Tstg -65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500

www.ti.com SNAS682 –MARCH 2016 Product Folder Links: CDCM6208V2G Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated (1) For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating. For slower power up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD, VDD_PLLx, and VDD_PRI/SEC reach at least 1.45V supply voltage. See application section on mixing power supplies and particularly Figure 57 for details.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD_PLL1 VDD_PRI, ΔVDD/Δt VDD power-up ramp time (0 to 3.3 V) PDN left open, all VDD tight together PDN low-high is delayed (1) 50 < tPDN ms TA Ambient Temperature -40 85 °C SDA and SCL in I 2 C MODE (SI_MODE[1:0] = 01) VI Input Voltage DVDD = 1.8 V –0.5 2.45 V DVDD = 3.3 V –0.5 3.965 V dR Data Rate 100 400 kbps VIH High-level input voltage 0.7 x DVDD V VIL Low-level input voltage 0.3 x DVDD V CBUS_I2C Total capacitive load for each bus line 400 pF (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (3) Connected to GND with 36 thermal vias (0.3 mm diameter). (4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.4 Thermal Information, Airflow = 0 LFM(1) (2) (3) (4)

THERMAL METRIC(1) CDCM6208 UNITRGZ

48 PINS VQFN

RθJA Junction-to-ambient thermal resistance 30.27 °C/W RθJC(top) Junction-to-case (top) thermal resistance 16.58 RθJB Junction-to-board thermal resistance 6.83 ψJT Junction-to-top characterization parameter 0.23 ψJB Junction-to-board characterization parameter 6.8 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.06

SNAS682 –MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (3) Connected to GND with 36 thermal vias (0.3 mm diameter). (4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.5 Thermal Information, Airflow = 150 LFM(1) (2) (3) (4)

THERMAL METRIC(1) CDCM6208 UNITRGZ

48 PINS

RθJA Junction-to-ambient thermal resistance 21.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 6.61 ψJT Junction-to-top characterization parameter 0.37 ψJB Junction-to-board characterization parameter RθJC(bot) Junction-to-case (bottom) thermal resistance 1.06 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (3) Connected to GND with 36 thermal vias (0.3 mm diameter). (4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.6 Thermal Information, Airflow = 250 LFM(1) (2) (3) (4)

THERMAL METRIC(1) CDCM6208 UNITRGZ RθJA Junction-to-ambient thermal resistance 19.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 6.6 ψJT Junction-to-top characterization parameter 0.45 ψJB Junction-to-board characterization parameter RθJC(bot) Junction-to-case (bottom) thermal resistance 1.06 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (3) Connected to GND with 36 thermal vias (0.3 mm diameter). (4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.7 Thermal Information, Airflow = 500 LFM(1) (2) (3) (4)

THERMAL METRIC(1) CDCM6208 UNITRGZ RθJA Junction-to-ambient thermal resistance 17.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 6.58 ψJT Junction-to-top characterization parameter 0.58 ψJB Junction-to-board characterization parameter RθJC(bot) Junction-to-case (bottom) thermal resistance 1.05

8.8 Single Ended Input Characteristics

(SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN, PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Input High Voltage 0.8 x DVDD V VIL Input Low Voltage 0.2 x DVDD V IIH Input High Current DVDD = 3.465V, VIH = 3.465 V (pull-up resistor excluded) 30 µA IIL Input Low Current DVDD = 3.465V, VIL= 0 V -30 µA ΔV/ΔT PDN, RESETN, SYNCN, REF_SEL Input Edge Rate 20% - 80% 0.75 V/ns minPulse PDN, RESETN, SYNCN low pulse to trigger proper device reset 10 ns C IN Input Capacitance 2.25 pF RESETN, PWR, SYNCN, PDN, REF_SEL, SI_MODE[1:0]: R Input Pullup and Pulldown Resistor 35 50 65 kΩ SDA and SCL in I 2 C Mode (SI_MODE[1:0]=01) VHYS_I2C Input hysteresis DVDD = 1.8 V 0.1 VDVDD V DVDD = 2.5/3.3 V 0.05 VDVDD V IH High-level input current VI = DVDD –5 5 µA VOL Output Low Voltage IOL= 3mA 0.2 x DVDD V CIN Input Capacitance terminal 5 pF

8.9 Single Ended Input Characteristics (PRI_REF, SEC_REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fIN Reference and Bypass Input Frequency VDD_PRI/SEC = 1.8 V 0.008 200 MHz VDD_PRI/SEC = 3.3 V 0.008 250 MHz VIH Input High Voltage 0.8 x VDD_PRI/V DD_SEC V VIL Input Low Voltage 0.2 x VDD_PRI/V DD_SEC V VHYST Input hysteresis 20 65 150 mV IIH Input High Current VDD_PRI/VDD_SEC = 3.465 V, VIH = 3.465 V 30 µA IIL Input Low Current VDD_PRI/VDD_SEC = 3.465 V, VIL = 0 V -30 µA ΔV/ΔT Reference Input Edge Rate 20% - 80% 0.75 V/ns IDC SE Reference Input Duty Cycle f PRI ≤ 200MHz 40% 60% 200 ≤ fPRI ≤ 250 MHz 43% 60% CIN Input Capacitance 2.25 pF

8.10 Differential Input Characteristics (PRI_REF, SEC_REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fIN Reference and Bypass Input Frequency 0.008 250 MHz VI Differential Input Voltage Swing, Peak-to- Peak VDD_PRI/SEC = 2.5/3.3 V 0.2 1.6 VPP VDD_PRI/SEC = 1.8 V 0.2 1 VPP VICM Input Common Mode Voltage CML input signaling, R4[7:6] = 00 VDD_PRI/V DD_SEC- 0.4 VDD_PRI/V DD_SEC- 0.1 V VICM Input Common Mode Voltage LVDS, VDD_PRI/SEC = 1.8/2.5/3.3 V, R4.0 = d.c. 0.8 1.2 1.5 V VHYST Input hysteresis LVDS (Q4[7:6,4:3] = 01) 15 65 mVpp CML (Q4[7:6,4:3] = 00) 20 85 mVpp IIH Input High Current VDD_PRI/SEC = 3.465 V, VIH = 3.465 V 30 µA IIL Input Low Current VDD_PRI/SEC = 3.465V, VIL = 0 V -30 µA ΔV/ΔT Reference Input Edge Rate 20% - 80% 0.75 V/ns IDCDIFF Reference Input Duty Cycle 30% 70% CIN Input Capacitance 2.7 pF (1) Verified with crystals specified for a load capacitance of CL=8pF, the pcb related capacitive load was estimated to be 2.3pF, and completed with a load capacitors of 4pF on each crystal terminal connected to GND. XTALs tested: NX3225GA 10MHz EXS00A- CG02813 CRG, NX3225GA 19.44MHz EXS00A-CG02810 CRG, NX3225GA 25MHz EXS00A-CG02811 CRG, and NX3225GA 30.72MHz EXS00A-CG02812 CRG. (2) For 30.73 MHz to 50 MHz, it is recommended to verify sufficient negative resistance and initial frequency accuracy with the crystal vendor. The 50 MHz use case was verified with a NX3225GA 50MHz EXS00A-CG02814 CRG. To meet a minimum frequency error, the best choice of the XTAL was one with CL = 7pF instead of CL = 8pF. (3) With NX3225GA_10M the measured remaining negative resistance on the EVM is 6430 Ω (43 x margin) (4) With NX3225GA_25M the measured remaining negative resistance on the EVM is 1740 Ω (25 x margin) (5) With NX3225GA_50M the measured remaining negative resistance on the EVM is 350 Ω (11 x margin) (6) Maximum drive level measured was 145 µW; XTAL should at least tolerate 200 µW

8.11 Crystal Input Characteristics (SEC_REF)

PARAMETER MIN TYP MAX UNIT MODE OF OSCILLATION FUNDAMENTAL Frequency See note (1) 10 30.72 MHz See note (2) 30.73 50 MHz Equivalent Series Resistance (ESR)

10 MHz 150(3)

Ω25 MHz 70(4)

50 MHz 30(5)

pF1.8 V SEC_REFN 5.5 7.25 8.5 3.3 V SEC_REFN 6.5 7.34 8.5 Drive Level See note (6) 200 µW

8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)

TA = –40°C to 85°C (Output load capacitance 10 pF unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Output High Voltage Status 1, Status 0, and SDO only; SDA is open drain and relies on external pullup for high output; IOH = 1 mA 0.8 x DVDD V VOL Output Low Voltage IOL = 1 mA 0.2 x DVDD V Vslew Output slew rate 30% - 70% 0.5 V/ns IOZH 3-stat Output High Current DVDD = 3.465 V, VIH = 3.465 V 5 µA IOZL 3-stat Output Low Current DVDD = 3.465 V, VIL = 0 V -5 µA tLOS Status Loss of Signal Detection Time LOS_REFfvco 1 2 1/f PFD tLOCK Status PLL Lock Detection Time Detect lock 2304 1/f PFD Detect unlock 512

8.13 PLL Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fVCO VCO Frequency Range 2.39 2.55 GHz KVCO VCO Gain

2.39 GHz 178

MHz/V2.50 GHz 204

2.55 GHz 213

fPFD PFD Input Frequency 0.008 100 MHz ICP-L High Impedance Mode Charge Pump Leakage ±700 nA fFOM Estimated PLL Figure of Merit (FOM) Measured in-band phase noise at the VCO output minus 20log(N- divider) at the flat region –224 dBc/Hz tSTARTUP Startup time (see Figure 41 ) Power supply ramp time of 1ms from 0 V to 1.7 V, final frequency accuracy of 10 ppm, fPFD = 25 MHz, CPDN_to_GND = 22nF w/ PRI input signal 12.8 ms w/ NDK 25 MHz crystal 12.85 ms

SNAS682 –MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of a multiple 1 over 220, the actual output frequency error is 0. Note: In LVCMOS Mode, positive and negative outputs are in phase.

8.14 LVCMOS Output Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT-F Output Frequency Fract Out divVDD_Yx_Yy = 2.5/3.3 V 0.78 250 MHzInteger out divVDD_Yx_Yy = 2.5/3.3 V 1.55 250 Int or frac out divVDD_Yx_Yy = 1.8 V 0.78/1.5 200 fACC-F Output Frequency Error (1) Fractional Output Divider –1 1 ppm VOH Output High Voltage (normal mode) VDD_Yx = min to max, IOH = -1 mA 0.8 x VDD_Yx_Yy V VOL Output Low Voltage(normal mode) VDD_Yx = min to max, IOL = 100 µA 0.2 x VDD_Yx_Yy V VOH Output High Voltage (slow mode) VDD_Yx = min to max, IOH = -100 µA 0.7 x VDD_Yx_Yy V VOL Output Low Voltage(slow mode) VDD_Yx = min to max, IOL = 100 µA 0.3 x VDD_Yx_Yy V IOH Output High Current V OUT = VDD_Yx_Yy/2 Normal mode –50 -8 mA Slow mode –45 -5 mA IOL Output Low Current V OUT = VDD_Yx_Yy/2 Normal mode 10 55 mA Slow mode 5 40 mA tSLEW-RATE-N Output Rise/Fall Slew Rate (normal mode) 20% to 80%, VDD_Yx_Yy = 2.5/3.3 V, CL = 5 pF 5.37 V/ns Output Rise/Fall Slew Rate (normal mode) 20% to 80%, VDD_Yx_Yy = 1.8 V, CL = 5 pF 2.62 V/ns tSLEW-RATE-S Output Rise/Fall Slew Rate (slow mode) 20% to 80%, VDD_Yx_Yy = 2.5/3.3 V, CL = 5 pF 4.17 V/ns Output Rise/Fall Slew Rate (slow mode) 20% to 80%, VDD_Yx_Yy = 1.8 V, CL = 5 pF 1.46 V/ns PN-floor Phase Noise Floor fOUT = 122.88 MHz –159.5 –154 dBc/Hz ODC Output Duty Cycle Not in bypass mode 45% 55% ROUT Output Impedance V OUT = VDD_Yx/2 Normal mode Slow mode 130 Ω

8.15 LVPECL (High-Swing CML) Output Characteristics

V, 3.135 V to 3.465 V, TA = –40°C TO 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT-I Output frequency Integer Output Divider 1.55 800 MHz VCM-DC Output DC coupled common mode voltage DC coupled with 50 Ω external termination to VDD_Yx_Yy VDD_Yx Yy – 0.4 V |VOD| Differential output voltage 100 Ω diff load AC coupling (See Figure 11), fOUT ≤ 250 MHz VDD_Yx_Yy ≤ 1.89 V 0.45 0.75 1.12 V VDD_Yx_Yy ≥ 2.375 V 0.6 0.8 1.12 V 100 Ω diff load AC coupling (See Figure 11), fOUT ≥ 250 MHz VDD_Yx_Yy ≤ 1.89 V 0.73 V VDD_Yx_Yy ≥ 2.375 V 0.55 0.75 1.12 V VOUT Differential output peak-to-peak voltage 2 x |VOD| V tR/tF Output rise/fall time ±200 mV around crossing point 109 217 ps 20% to 80% VOD 211 ps tslew Output rise/fall slew rate 3.7 5.1 7.3 V/ns PN-floor Phase noise floor VDD_Yx_Yy = 3.3 V (See Figure 53) –161.4 –155.8 dBc/Hz ODC Output duty cycle Not in bypass mode 47.5% 52.5% ROUT Output impedance measured from pin to VDD_Yx_Yy 50 Ω

8.16 CML Output Characteristics

TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT-I Output frequency Integer Output Divider 1.55 800 MHz VCM-AC Output AC coupled common mode voltage AC coupled with 50 Ω receiver termination VDD_Yx_Yy – 0.46 V VCM-DC Output DC coupled common mode voltage DC coupled with 50 Ω on-chip termination to VDD_Yx_Yy VDD_Yx_Yy – 0.2 V |VOD| Differential output voltage 100 Ω diff load AC coupling, (See Figure 11) 0.3 0.45 0.58 V VOUT Differential output peak-to-peak voltage 2 x |VOD| V tR/tF Output rise/fall time 20% to 80% VDDYx = 1.8 V 100 151 300 ps VDDYx = 2.5 V/3.3 V 100 143 200 ps PN-floor Phase noise floor at > 5 Hz offset fOUT = 122.88 MHz VDD_Yx_Yy = 1.8 V –161.2 –155.8 dBc/Hz VDD_Yx_Yy = 3.3 V –161.2 –153.8 dBc/Hz ODC Output duty cycle Not in bypass mode 47.5% 52.5% ROUT Output impedance measured from pin to VDD_Yx_Yy 50 Ω

SNAS682 –MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of a multiple of 1 over 220, the actual output frequency error is 0.

8.17 LVDS (Low-Power CML) Output Characteristics

3.465V, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT-I Output frequency Integer output divider 1.55 400 MHz fOUT-F Fractional output divider 0.78 400 MHz fACC-F Output frequency error (1) Fractional output divider -1 1 ppm VCM-AC Output AC coupled common mode voltage AC coupled with 50 Ω receiver termination VDD_Yx_Yy – 0.76 V VCM-DC Output DC coupled common mode voltage DC coupled with 50 Ω on-chip termination to VDD_Yx_Yy VDD_Yx_Yy – 0.13 V |VOD| Differential output voltage 100 Ω diff load AC coupling, (See Figure 11) 0.247 0.34 0.454 V VOUT Differential output peak-to- peak voltage 2 x |VOD| V tR/tF Output rise/fall time ±100mV around crossing point 300 ps PN-floor Phase noise floor fOUT= 122.88 MHz VDD_Yx = 1.8 V –159.3 –154.5 dBc/Hz VDD_Yx = 2.5/3.3 V –159.1 –154.9 dBc/Hz ODC Output duty cycle Not in bypass mode Y[3:0] 47.5% 52.5% Y[7:4] 45% 55% ROUT Output impedance Measured from pin to VDD_Yx_Yy 167 Ω (1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of A 1/220 multiple, the actual output frequency error is 0.

8.18 HCSL Output Characteristics

TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT-I Output frequency Integer Output Divider 1.55 400 MHz fOUT-F Fractional Output Divider 0.78 400 MHz fACC-F Output Frequency Error (1) Fractional Output Divider -1 1 ppm VCM Output Common Mode Voltage VDD_Yx_Yy = 1.8 V 0.2 0.33 0.55 V |VOD| Differential Output Voltage VDD_Yx_Yy = 1.8 V 0.4 0.65 1.0 V VOUT Differential Output Peak-to-peak Voltage VDD_Yx_Yy = 2.5/3.3 V 1.0 2.1 V VDD_Yx_Yy = 1.8 V 2 x|VOD| V tR/tF Output Rise/Fall Time Measured from VDIFF= –100 mV to VDIFF = +100mV, VDD_Yx_Yy = 2.5/3.3 V 100 167 250 ps Measured from VDIFF= –100 mV to VDIFF= +100 mV, VDD_Yx_Yy = 1.8 V 120 192 295 PN-floor Phase Noise Floor fOUT = 122.88 MHz VDD_Yx_Yy = 1.8 V –158.8 –153 dBc/Hz VDD_Yx = 2.5/3.3 V –157.6 –153 dBc/Hz ODC Output Duty Cycle Not in bypass mode 45% 55%

www.ti.com SNAS682 –MARCH 2016 Product Folder Links: CDCM6208V2G Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated (1) SYNC is toggled 10,000 times for each device. Test is repeated over process voltage and temperature (PVT).

8.19 Output Skew and Sync to Output Propagation Delay Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPD-PS Propagation delay SYNCN↑ to output toggling high f VCO = 2.5 GHz PS_A = 4 9 10.5 11 1/fPS_A PS_A = 5 9 10.2 11 1/fPS_A PS_A = 6 9 10.0 11 1/fPS_A ΔtPD-PS Part-to-Part Propagation delay variation SYNCN↑ to output toggling high(1) Fixed supply voltage, temp, and device setting(1) 0 1 1/f PS_A OUTPUT SKEW – ALL OUTPUTS USE IDENTICAL OUTPUT SIGNALING, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4 tSK,LVDS Skew between Y[7:4] LVDS Y[7:4] = LVDS 40 ps tSK,LVDS Skew between Y[3:0] LVDS Y[3:0] = LVDS 40 ps tSK,LVDS Skew between Y[7:0] LVDS Y[7:0] = LVDS 80 ps tSK,CML Skew between Y[3:0] CML Y[3:0] = CML 40 ps tSK,PECL Skew between Y[3:0] PECL Y[3:0] = LVPECL 40 ps tSK,HCSL Skew between Y[7:4] HCSL Y[7:4] = HCSL 40 ps tSK,SE Skew between Y[7:4] CMOS Y[7:4] = CMOS 50 ps OUTPUT SKEW - MIXED SIGNAL OUTPUT CONFIGURATION, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4 tSK,CMOS-LVDS Skew between Y[7:4] LVDS and CMOS mixed Y[4] = CMOS, Y[7:5] = LVDS 2.5 ns tSK,CMOS-PECL Skew between Y[7:0] CMOS and LVPECL mixed Y[7:4] = CMOS, Y[3:0] = LVPECL 2.5 ns tSK,PECL-LVDS Skew between Y[3:0] LVPECL and LVDS mixed Y[0] = LVPECL, Y[3:1] = LVDS 120 ps tSK,PECL-CML Skew between Y[3:0] LVPECL and CML mixed Y[0] = LVPECL, Y[3:1] = CML 40 ps tSK,LVDS-PECL Skew between Y[7:0] LVDS and LVPECL mixed Y[7:4] = LVDS, Y[3:0] = LVPECL 180 ps tSK,LVDS-HCSL Skew between Y[7:4] LVDS and HCSL mixed Y[4] = LVDS, Y[7:5] = HCSL 250 ps OUTPUT SKEW - USING FRACTIONAL OUTPUT DIVISION; PS_A = PS_B = 6, OutDiv = 3.125 tSK,DIFF, frac Skew between Y[7:4] LVDS using all fractional divider with the same divider setting Y[7:4] = LVDS 200 ps

8.20 Device Individual Block Current Consumption

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.8 V, 2.5 V, or 3.3 V, TA = –40°C to 85°C, Output Types = LVPECL/CML/LVDS/LVCMOS/HCSL BLOCK CONDITION TYPICAL CURRENT CONSUMPTION (mA) Core CDCM6208V2G Core, active mode, PS_A = PS_B = 4 75 Output Buffer CML output, AC coupled w/ 100 Ω diff load 24.25 LVPECL, AC coupled w/ 100 Ω diff load 40 LVCMOS output, transient, 'C L' load, 'f' MHz output frequency, 'V' output swing 1.8 + V x f OUT x (C L+ 12 x 10 -12) x 10 3 LVDS output, AC coupled w/ 100 Ω diff load 19.7 HCSL output, 50 Ω load to GND on each output pin 31 Output Divide Circuitry Integer Divider Bypass (Divide = 1) 3 Integer Divide Enabled, Divide > 1 8 Fractional Divider Enabled 12 additional current when PS_A differs from PS_B 15 Total Device, CDCM6208V2G Device Settings (V2) 1. PRI input enabled, set to LVDS mode 2. SEC input XTAL 3. Input bypass off, PRI only sent to PLL 4. Reference clock 30.72 MHz 5. PRI input divider set to 1 6. Reference input divider set to 1 7. Charge Pump Current = 2.5 mA 8. VCO Frequency = 3.072 GHz 9. PS_A = PS_B divider ration = 4 10. Feedback divider ratio = 25 11. Output divider ratio = 5 12. Fractional divider pre-divider = 2 13. Fractional divider core input frequency = 384 MHz 15. CML outputs selected for CH0-3 (153.6 MHz) LVDS outputs selected for CH4-7 (100 MHz, 66.66 MHz,

125 MHz, 50 MHz)

(excl. I termination_resistors) (1.8 V: 251 mA

2.5 V: 254 mA

3.3 V: 257 mA)

(incl. I termination_resistors) (1.8 V: 310 mA

2.5 V: 313 mA

3.3 V: 316 mA)

Total Device, CDCM6208V2G Power Down (PDN = '0') 0.35 Helpful Note: The CDCM6208V2G User GUI does an excellent job estimating the total device current consumption based on the actual device configuration. Therefore, it is recommended to use the GUI to estimate device power consumption.

8.21 Worst Case Current Consumption

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 3.45 V, TA = T-40°C to 85°C, Output Types = maximum swing, all blocks including duty cycle correction and fractional divider enabled and operating at maximum operation BLOCK CONDITION CURRENT CONSUMPTION TYP / MAX Total Device, CDCM6208V2G All conditions over PVT, AC coupled outputs with all outputs terminated, device configuration: Device Settings (V2) 1. PRI input enabled, set to LVDS mode 2. SEC input XTAL 3. Input bypass off, PRI only sent to PLL 4. Reference clock 30.72 MHz 5. PRI input divider set to 1 6. Reference input divider set to 1 7. Charge Pump Current = 2.5 mA 8. VCO Frequency = 3.072 GHz 9. PS_A = PS_B divider ration = 4 10. Feedback divider ratio = 25 11. Output divider ratio = 5 12. Fractional divider pre-divider = 2 13. Fractional divider core input frequency = 384 MHz 15. CML outputs selected for CH0-3 (153.6 MHz) LVDS outputs selected for CH4-7 (100MHz, 66.66 MHz, 125 MHz, 50 MHz)

1.8 V: 310 mA / +21% (excl term)

3.3 V: 318 mA / +21% (excl term)

characteristics for standard mode and fast mode transfer.

8.22 I2C TIMING(1)

Figure 1. CDCM6208V2G SPI Port Timing

8.23 SPI Timing Requirements

Figure 2. I2C Timing Diagram

8.24 Typical Characteristics

Figure 3. Fractional Divider Bit Selection Impact on Jitter Figure 4. Fractional Divider Input Frequency Impact on Jitter Figure 5. Fractional Divider Bit Selection Impact on TJ Figure 6. Fractional Divider Bit Selection Impact on TJ Figure 7. PSRR (in dBc and DJ [ps]) Over Frequency [Hz] and Output Signal Format

(spur/20) -12 p-p CLK 2 x 10Deterministic Jitter (ps ) = x 10 x f/c112 CDCM6208V2G www.ti.com SNAS682 –MARCH 2016 Product Folder Links: CDCM6208V2G Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated

8.24.1 Fractional Output Divider Jitter Performance

The fractional output divider jitter performance is a function of the fraction output divider input frequency as well as actual fractional divide setting itself. To minimize the fractional output jitter, it is recommended to use the least number of fractional bits and the highest input frequency possible into the divider. As observable in Figure 3, the largest jitter contribution occurs when only one fractional divider bit is selected, and especially when the bits in the middle range of the fractional divider are selected. Tested using a LeCroy 40 Gbps RealTime scope over a time window of 200 ms. The RJ impact on TJ is estimated for a BERT 10(–12) – 1. This measurement result is overly pessimistic, as it does not bandwidth limit the high-frequencies. In a real system, the SERDES TX will BW limit the jitter through its PLL roll-off above the TX PLL bandwidth of typically bit rate divided by 10.

8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency

See Figure 7 for reference. Many system designs become increasingly more sensitive to power supply noise rejection. In order to simplify design and cost, the CDCM6208V2G has built in internal voltage regulation, improving the power supply noise rejection over designs with no regulators. As a result, the following output rejection is achieved: The DJ due to PSRR can be estimated using Equation 1: (1) Example: Therefore, if 100 mV noise with a frequency of 10 kHz were observed at the output supply, the according output jitter for a 122.88 MHz output signal with LVDS signaling could be estimated with DJ = 0.7ps.

9 Parameter Measurement Information

9.1 Characterization Test Setup

This section describes the characterization test setup of each block in the CDCM6208V2G. Figure 8. LVCMOS Output AC Configuration During Device Test (VOH, VOL, tSLEW) Figure 9. LVCMOS Output DC Configuration During Device Test Figure 10. LVCMOS Output AC Configuration During Device Phase Noise Test

Figure 24. Differential and Single Ended Output Skew and Propagation Delay

10 Detailed Description

10.1 Overview

VCO that operates from 2.39 GHz to 2.55 GHz. supports simply switching or can be configured as Smart MUX and supports glitchless input switching. output MUX. A total of 2 output MUXes are available. components and supports bandwidths from a few Hz up to 400kHz.

10.2 Functional Block Diagram

Figure 25. High-Level Block Diagram of CDCM6208V2G

10.3 Feature Description

Table 1. Synthesizer Mode (Loop filter BW >250 kHz) Table 2. Jitter Cleaner Mode (Loop filter BW < 1 kHz)

Less than -80 dBc spurious from PFD/reference clocks at 122.88 MHz output frequency in the Nyquist range.
Less than -68 dBc spurious from output channel-to-channel coupling on the victim output at differential signaling level operated at 122.88 MHz output frequency in the Nyquist range. Device outputs: The Device outputs offer multiple signaling formats: high-swing CML (LVPECL like), normal-swing CML (CML), low-swing CML (LVDS like), HCSL, and LVCMOS signaling.

Table 3. Device Outputs programming. I2C offers 4 distinct addresses to support up to 4 devices on the same programming lines.

Figure 26. Typical Use Case: CDCM6208V2G Example in Wireless Infrastructure Baseband Application

10.4 Device Functional Modes

10.4.1 Control Pins Definition

loop filter, "JC" denotes PLL bandwidths of ≤ 1 kHz and "Synth" denotes PLL bandwidths of ≥ 100 kHz.

(1) The functionality of the status 0 and status 1 pins in SPI and I2C mode is programmable. primary and secondary input stage power supply must be always connected. For all pin modes, STATUS0 outputs the PLL_LOCK signal and STATUS1 the LOSS OF REFERENCE. for LVDS signaling (Type = LVDS) are supply agnostic, and therefore can be powered from 2.5 V/3.3 V or 1.8 V regardless of the supply select setting of pin number 44. Table 4. Pre-Configured Settings of CDCM6208V2G Accessible by PIN4:0 (2)

00 I/O SPI

01 I/O I2C

11 RESERVED

3333 HCSL

9773 LVDS

Table 4. Pre-Configured Settings of CDCM6208V2G Accessible by PIN4:0 (2) (continued)

9874 LVDS

0468 LVDS X Disable

415 LVDS

1195 LVDS

10.4.2 Loop Filter Recommendations for Pin Modes

either design their own optimized loop filter, or use the suggested loop filter in the Table 5. Table 5. CDCM6208V2G Loop Filter Recommendation for Pin Mode

Table 5. CDCM6208V2G Loop Filter Recommendation for Pin Mode (continued) (1) The reverse logic between the register Q21.2 and the external output signal on STATUS0 or STATUS1.

10.4.3 Status Pins Definition

pin and which can also be read in the register space. Table 6. CDCM6208V2G Status Pin Definition List regardless of the actual input signal status on PRI_IN.

goes out of lock or the selected reference clock signal is lost.

10.4.4 PLL Lock Detect

10.4.5 Interface and Control

The host (DSP, Microcontroller, FPGA, etc) configures and monitors the CDCM6208V2G via the SPI or I2C port. appropriately to generate the necessary clock outputs out of the device. Figure 27. CDCM6208V2G Interface and Control Block to write to a read only bit will not change the state of the bit).

10.4.5.1 Register File Reference Convention

Figure 28. CDCM6208V2G Register Reference Format

10.4.5.2 SPI - Serial Peripheral Interface

to/from the device. The SPI interface consists of four signal pins. The device SPI address is 0000. Table 7. Serial Port Signals in SPI Mode Figure 29. CDCM6208V2G SPI Message Format

10.4.5.2.1 Configuring the PLL

Filter, Feedback Divider, Prescaler Divider, and Output Dividers. feedback divider, and PS_A the prescaler divider A. Equation 4. (Use PS_B in for outputs 2, 3, 6, and 7).

SNAS682 –MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated When the output frequency plan calls for the use of some output dividers as fractional values, the following steps are needed to calculate the closest achievable frequencies for those using fractional output dividers and the frequency errors (difference between the desired frequency and the closest achievable frequency).

Based on system needs, decide the frequencies that need to have best possible jitter performance.
Once decided, these frequencies need to be placed on integer output dividers.
Then a frequency plan for these frequencies with strict jitter requirements can be worked out using the common divisor algorithm.
Once the integer divider plans are worked out, the PLL settings (including VCO frequency, feedback divider, input divider and prescaler divider) can be worked out to map the input frequency to the frequency out of the prescaler divider.
Then calculate the fractional divider values (whose values must be greater than 2) that are needed to support the output frequencies that are not part of the common frequency plan from the common divisor algorithm already worked out.
For each fractional divider value, try to represent the fractional portion in a 20 bit binary scheme, where the first fractional bit is represented as 0.5, the second fractional bit is represented as 0.25, third fractional bit is represented as 0.125 and so on. Continue this process until the entire 20 bit fractional binary word is exhausted.
Once exhausted, the fraction can be calculated as a cumulative sum of the fractional bit x fractional value of the fractional bit. Once this is done, the closest achievable output frequency can be calculated with the mathematical function of the frequency out of the prescaler divider divided by the achievable fractional divider.
The frequency error can then be calculated as the difference between the desired frequency and the closest achievable frequency.

10.5 Programming

10.5.1 Writing to the CDCM6208V2G

To initiate a SPI data transfer, the host asserts the SCS (serial chip select) pin low. The first rising edge of the clock signal (SCL) transfers the bit presented on the SDI pin of the CDCM6208V2G. This bit signals if a read (first bit high) or a write (first bit low) will transpire. The SPI port shifts data to the CDCM6208V2G with each rising edge of SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the target register in the register file. The 16 bits that follow are the data payload. If the host sends an incomplete message, (i.e. the host de-asserts the SCS pin high prior to a complete message transmission), then the CDCM6208V2G aborts the transfer, and device makes no changes to the register file or the hardware. Figure 31 shows the format of a write transaction on the CDCM6208V2G SPI port. The host signals the CDCM6208V2G of the completed transfer and disables the SPI port by de-asserting the SCS pin high.

10.5.2 Reading from the CDCM6208V2G

CDCM6208V2G that the transfer is complete by de-asserting the SCS pin high.

10.5.3 Block Write/Read Operation

incrementing the address pointer (provided the SCS pin remains active low for all sequences). Figure 31. CDCM6208V2G SPI Port Message Sequencing

10.5.4 I2C Serial Interface

at the SDA and SCL inputs to provide receiver input hysteresis for increased noise robustness. Communication through I2C is not possible while RESETN is held low.

SNAS682 –MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Programming (continued) In an I2C bus system, the CDCM6208V2G acts as a slave device and is connected to the serial bus (data bus SDA and clock bus SCL). The SDA port is bidirectional and uses an open drain driver to permit multiple devices to be connected to the same serial bus. The CDCM6208V2G allows up to four unique CDCM6208V2G slave devices to occupy the I2C bus in addition to any other I2C slave device with a different I2C address. These slave devices are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a matching slave address responds to subsequent I2C commands. The device slave address is 10101xx (the two LSBs are determined by the AD1 and AD0 pins). The five MSBs are hard-wired, while the two LSBs are set through pins on device powerup. Figure 32. During the data transfer through the I2C port interface, one clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. The start data transfer condition is characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are always initiated by the master. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit and bytes are sent MSB first. The acknowledge bit (A) or non-acknowledge bit (A) is the 9thbit attached to any 8-bit data byte and is always generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A = 1). A = 0 is done by pulling the SDA line low during the 9thclock pulse and A = 1 is done by leaving the SDA line high during the 9thclock pulse. The I2C master initiates the data transfer by asserting a start condition which initiates a response from all slave devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line (consisting of the 7-bit slave address (MSB first) and an R/W bit), the device whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data transfer with the master. The CDCM6208V2G slave address bytes are given in below table. After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop condition to end data transfer during the 10 thclock pulse following the acknowledge bit for the last data byte from the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low during the 9thclock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the slave knows the data transfer is finished and enters the idle mode. The master then takes the data line low during the low period before the 10 thclock pulse, and high during the 10 thclock pulse to assert a stop condition.

10.6 Register Maps

the PLL and dividers, and Register 5 - 20 configures the 8 different outputs. Figure 35. Device Register Map

Table 10. Register 0

0 RESERVED This bit is tied to zero statically, and it is recommended to set to 0

Table 11. Register 1 Table 12. Register 2

Table 13. Register 3

12 ST1_SEL_REFCLK

11 ST1_LOR_EN

10 ST1_PLLLOCK_EN

9 ST0_SEL_REFCLK

8 ST0_LOR_EN

7 ST0_PLLLOCK_EN

6 RSTN Device Reset

5 SYNCN Output Divider

4 ENCAL PLL/VCO

should be updated after power-up to reflect the true VDD_SEC supply voltage used. should be updated after power-up to reflect the true VDD_PRI supply voltage used. Table 14. Register 4 delay and waveform reshaping.

13 SMUX_MODE_SEL

12 SMUX_REF_SEL

0). See Table 6 for details.

5 EN_SEC_CLK

2 EN_PRI_CLK

1 SEC_SUPPLY (1) Secondary Input

0 PRI_SUPPLY (2) Primary Input

(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter. Table 15. Register 5

15 RESERVED This bit must be set to 0

14 RESERVED This bit must be set to 0

13 RESERVED This bit must be set to 0

12 RESERVED This bit must be set to 0

11 RESERVED This bit must be set to 0

10 RESERVED This bit must be set to 0

9 RESERVED This bit must be set to 0

0 SUPPLY_CH0_1 (1) Output Channels 0

Table 16. Register 6

8 RESERVED This bit must be set to 0

(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter. Table 17. Register 7

0 SUPPLY_CH2_3 (1) Output Channels 2

Table 18. Register 8

(1) It is ok to power up the device with a 2.5 V / 3.3 V supply while this bit is set to 0 and to update this bit thereafter. Table 19. Register 9

9 EN_FRACDIV_CH4

8 LVCMOS_SLEW_CH4

7 EN_LVCMOS_N_CH4

6 EN_LVCMOS_P_CH4

5 RESERVED This bit must be set to 0

0 SUPPLY_CH4 (1)

Table 20. Register 10 Table 21. Register 11

(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter. Table 22. Register 12

9 EN_FRACDIV_CH5

8 LVCMOS_SLEW_CH5

7 EN_LVCMOS_N_CH5

6 EN_LVCMOS_P_CH5

0 SUPPLY_CH5 (1)

Table 23. Register 13 Table 24. Register 14

(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter. Table 25. Register 15

9 EN_FRACDIV_CH6

8 LVCMOS_SLEW_CH6

7 EN_LVCMOS_N_CH6

6 EN_LVCMOS_P_CH6

0 SUPPLY_CH6 (1)

Table 26. Register 16 Table 27. Register 17

(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter. Table 28. Register 18

9 EN_FRACDIV_CH7 Output channel 7 fractional divider enable: 0 → Disable, 1 →

8 LVCMOS_SLEW_CH7 Output channel 7 LVCMOS output slew: 0 → Normal, 1 → Slow

7 EN_LVCMOS_N_CH7

6 EN_LVCMOS_P_CH7 Output channel 7 positive-side LVCMOS enable: 0 → Disable, 1 →

Table 29. Register 19 Table 30. Register 20

Table 31. Register 21 (Read Only)

15 RESERVED This bit will read a 0

14 RESERVED This bit will read a 0

13 RESERVED This bit will read a 0

12 RESERVED This bit will read a 0

11 RESERVED This bit will read a 0

10 RESERVED This bit will read a 0

9 RESERVED This bit will read a 0

8 RESERVED This bit will read a 0

7 RESERVED This bit will read a 0

6 RESERVED This bit will read a 0

5 RESERVED This bit will read a 0

4 RESERVED This bit will read a 0

3 RESERVED This bit will read a 0

2 PLL_UNLOCK

1 LOS_REF

0 SEL_REF

Table 32. Register 40 (Read Only)

15 RESERVED Ignore

14 RESERVED Ignore

13 RESERVED Ignore

12 RESERVED Ignore

11 RESERVED Ignore

10 RESERVED Ignore

9 RESERVED Ignore

8 RESERVED Ignore

7 RESERVED Ignore

6 RESERVED Ignore

Table 33. Default Register Setting For SPI/I2C Modes

validate and test their design implementation to confirm system functionality.

11.1 Application Information

clocks from an on-chip oscillator which can be buffered through integer or fractional output dividers.

11.2 Typical Applications

Figure 36. Typical Application Circuit Figure 37. Typical Application Circuit

11.2.1 Design Requirements

11.2.1.1 Device Block-level Description

The CDCM6208V2G includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a universal input interface, a phase frequency detector (PFD), charge pump, partially integrated loop filter, and a feedback divider. Completing the CDCM6208V2G device are the combination of integer and fractional output dividers, and universal output buffers. The PLL is powered by on-chip low dropout (LDO), linear voltage regulators and the regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs provide isolation of the PLL from any noise in the external power supply rail with a PSNR of better than -50 dB at all frequencies. The regulator capacitor pin REG_CAP should be connected to ground by a 10 µF capacitor with low ESR (e.g. below 1 Ω ESR) to ensure stability.

11.2.1.2 Device Configuration Control

Figure 39 illustrates the relationships between device states, the control pins, device initialization and configuration, and device operational modes. In pin mode, the state of the control pins determines the configuration of the device for all device states. In programming mode, the device registers are initialized to their default state and the host can update the configuration by writing to the device registers. A system may transition a device from pin mode to host connected mode by changing the state of the SI_MODE pins and then triggering a device reset (either via the RESETN pin or via setting the RESETN bit in the device registers). In reset, the device disables the outputs so that unwanted sporadic activity associated with device initialization does not appear on the device outputs.

11.2.1.3 Configuring the RESETN Pin

Figure 38 shows two typical applications examples of the RESETN pin. Figure 38. RESETN/PWR Pin Configurations before the host controller output signal is valid. capacitor, then the device effectively ignores the state of the RESETN pin. resistor is not installed, the pin is internally pulled high.

11.2.1.4 Preventing False Output Frequencies in SPI/I2C Mode at Startup:

Some systems require a custom configuration and cannot tolerate any output to start up with a wrong frequency. calibrates automatically after RESET becomes released and starts out with the desired output frequency. space to disable outputs until the write operation is complete. Figure 40. Reset Pin Control During Register Loading

11.2.1.5 Power Down

than 1 mA from the entire device.

11.2.1.6 Device Power Up Timing:

Table 34. Initialization Routine

Table 34. Initialization Routine (continued) 100 MHz) to 8 sec (8 kHz PFD). can range from 640 µs (fPFD= 100 MHz) to 8 sec (fPFD= 8kHz). range from 1280 µs (fPFD= 100 MHz) to 16 sec (f PFD= 8 KHz). Figure 41. Powerup Time

Figure 42. XTAL Startup Using NX3225GA 25 MHz (Step 2)

Figure 43. PLL Lock Behavior (Step 6)

11.2.1.7 Input Mux and Smart Input Mux

The Smart Input MUX supports auto-switching and manual-switching using control pin (and through register). are suppressed at the MUX output. Table 35. Input Mux Selection

0 X X Auto Select Priority is given to Primary

0 Primary input input select through

0 Primary or Auto (see Table 4)

1 Secondary or Auto (see Table 4)

Tie REF_SEL pin always high
For primary clock input testing, use R4[13:12] = 10
For secondary clock input testing, set R4[13:12] = 11.
For the auto-mux setting in the final product shipment, set R3[13:12]=01 or 00

program R4[13:12] = 11, and select primary or secondary input by toggling REF_SEL low or high.

(PRI_REF divided by R and SEC_REF) need to be similar; however, they can vary by up to 20%. timing diagram of an auto-switch at the input MUX is shown in Figure 44. Figure 44. Smart Input MUX Auto-Switch Mode Timing Diagram

11.2.1.8 Universal INPUT Buffer (PRI_REF, SEC_REF)

characteristics of the crystal that can be used. Both inputs incorporate hysteresis.

11.2.1.9 VCO Calibration

Normal Operation- When the CDCM6208V2G is in normal (operational) mode, the state of both the power

down pin (PDN) and reset pin (RESETN) is high.

Entering the reset state – If the user wishes to restore all device defaults and initiate a VCO calibration

removing and restoring device power. Pulling either of these pins low places the device in the reset state. Holding either pin low holds the device in reset.

Exiting the reset state – The device calibrates the VCO either by exiting the device reset state or through

power is applied and/or the system restores the state of the PDN or RESETN pins from the low to high state.

www.ti.com SNAS682 –MARCH 2016 Product Folder Links: CDCM6208V2G Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated 4. Device stabilization – After exiting the reset state as described in Step 3, the device monitors internal voltages and starts a reset timer. Only after internal voltages are at the correct level and the reset time has expired will the device initiate a VCO calibration. This ensures that the device power supplies and phase locked loops have stabilized prior to calibrating the VCO. 5. VCO Calibration – The CDCM6208V2G calibrates the VCO. During the calibration routine, the device holds all outputs in reset so that the CDCM6208V2G generates no spurious clock signals.

11.2.1.10 Reference Divider (R)

The reference (R) divider is a continuous 4-b counter (1 – 16) that is present on the primary input before the Smart Input MUX. It is operational in the frequency range of 8 kHz to 250 MHz. The output of the R divider sets the input frequency for the Smart MUX, and the auto switch capability of the Smart MUX can then be employed as long as the secondary input frequency is no more than ± 20% different from the output of the R divider.

11.2.1.11 Input Divider (M)

The input (M) divider is a continuous 14-b counter (1 – 16384) that is present after the Smart Input MUX. It is operational in the frequency range of 8 kHz to 250 MHz. The output of the M divider sets the PFD frequency to the PLL and should be in the range of 8 kHz to 100 MHz.

11.2.1.12 Feedback Divider (N)

The feedback (N) divider is made up of cascaded 8-b counter divider (1 – 256) followed by a 10-b counter divider (1 – 1024) that are present on the feedback path of the PLL. It is operational in the frequency range of 8 kHz to 800 MHz. The output of the N divider sets the PFD frequency to the PLL and should be in the range of 8 kHz to 100 MHz. The frequency out of the first divider is required to be less than or equal to 200 MHz to ensure proper operation.

11.2.1.13 Prescaler Dividers (PS_A, PS_B)

The prescaler (PS) dividers are fed by the output of the VCO and are distributed to the output dividers (PS_A to the dividers for Outputs 0, 1, 4, and 5 and PS_B to the dividers for Outputs 2, 3, 6, and 7. PS_A also completes the PLL as it also drives the input of the Feedback Divider (N).

11.2.1.14 Phase Frequency Detector (PFD)

The PFD takes inputs from the Smart Input MUX output and the feedback divider output and produces an output that is dependent on the phase and frequency difference between the two inputs. The allowable range of frequencies at the inputs of the PFD is from 8 kHz to 100 MHz.

11.2.1.15 Charge Pump (CP)

The charge pump is controlled by the PFD which dictates either to pump up or down in order to charge or discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then converted to a voltage that drives the control voltage node of the internal VCO through the loop filter. The range of the charge pump current is from 500 µA to 4 mA.

11.2.1.16 Programmable Loop Filter

The on-chip PLL supports a partially internal and partially external loop filter configuration for all PLL loop bandwidths where the passive external components C1, C2, and R2 are connected to the ELF pin as shown in Figure 45 to achieve PLL loop bandwidths from 400 kHz down to 10 Hz.

Figure 45. CDCM6208V2G PLL Loop Filter Topology

11.2.1.16.1 Loop Filter Component Selection

loop filter is device internal with R3 and C3 register selectable.

11.2.1.16.2 Device Output Signaling

freely between 1.8 V and 3.3 V. nearly the same output swing and performance at much lower power consumption. receiver should connected using AC coupling. See reference schematic Figure 63 for a circuit example. freely between 1.8 V and 3.3 V. HCSL is referenced to GND, and requires external 50 Ω termination to GND. See reference schematic for an example. selected through register programming. Each differential output port can drive one or two CMOS output signals.

11.2.1.16.3 Integer Output Divider (IO)

Table 36. Integer Output Divider (IO)

11.2.1.16.4 Fractional Output Divider (FOD)

unrelated frequencies. The fractional output divider architecture is shown in Figure 46. Figure 46. Fractional Output Divider Principle Architecture

1.0 ≤ ƒracDIV ≤ 1.9375
2.0 ≤ ƒracDIV ≤ 3.875
4.0 ≤ ƒracDIV ≤ 5.875
254.0 ≤ ƒracDIV ≤ 255.875
256.0 ≤ ƒracDIV ≤ 256.99999 The CDCM6208V2G user GUI comprehends the fractional divider limitations; therefore, using the GUI to comprehend frequency planning is recommended.

divider enable bit, which engages the higher performing integer divider.

11.2.1.16.5 Output Synchronization

SYNC pin assertion. For one particular device configuration, the uncertainty of the delay is ±1 PS_A clock cycles. For one particular device and one particular configuration, the delay uncertainty is one PS_A clock cycle. uncertainty due to sync remains ±2 clock cycles. Figure 47. SYNCN to Output Delay Uncertainty

11.2.1.16.6 Output MUX on Y4 and Y5

bypassing of the PLL in order to output the primary or secondary input signal directly.

11.2.1.16.7 Staggered CLK Output Powerup for Power Sequencing of a DSP

Digital control: Initiating a configuration of all registers so that all outputs are disabled, and then turning on

outputs one by one through serial interface after each DSP rail becomes powered up accordingly.

Output Power supply domain control: An even easier scheme might be to connect the clock output power

output will remain disabled until the DSP rails ramps up as well. Figure 48 shows the turn-on behavior. Figure 48. Sequencing the Output Turn-on Through Sequencing the Output Supplies. Output Y2 Powers Up While Output Y0 is Already Running.

11.2.2 Detailed Design Procedure

11.2.2.1 Jitter Considerations in SERDES Systems

jitter with a 20 dB/dec or even steeper roll-off. Figure 49. Serial Link Jitter Budget Explanation

11.2.2.2 Jitter Considerations in ADC and DAC Systems

frequency band, and also have maximum spur level requirements to achieve maximum noise floor sensitivity. Figure 51. IF = 60 MHz Fclk = 122.88 MHz Baseline (Lab Clk Generator) ADC: ADS62P48-49 Figure 52. IF = 60 MHz Fclk = 122.88 MHz CDCM6208V2G driving ADC

other outputs running at different integer frequencies. otherwise SFDR and SNR suffer due to crosstalk between the two pre-divider frequencies. Figure 53. DAC Driven by Lab Source and CDCM6208V2G in Comparison (Performance Identical)

156.25 MHZ

11.2.3 Application Performance Plots

11.2.3.1 Typical Device Jitter

Figure 54. Typical Device Output Phase Noise and Jitter Figure 55. Typical Device Output Phase Noise and Jitter Figure 56. Phase Noise Plot for Jitter Cleaning Mode (blue) and Synthesizer Mode (green)

12 Power Supply Recommendations

12.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains

calibration further using the PDN input. Slow power-up supply ramp: No particular power supply sequence is required for the CDCM6208V2G. PLL by either toggling PDN or RESET high-low-high. Figure 57. PDN Delay When Using Slow Ramping Power Supplies (Supply Ramp > 50 ms)

12.1.1 Fast Power-up Supply Ramp

SNAS682 –MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains (continued)

12.1.2 Delaying VDD_Yx_Yy to Protect DSP IOs

DSPs and other highly integrated processors sometimes do not permit any clock signal to be present until the DSP power supply for the corresponding IO is also present. The CDCM6208V2G allows to either sequence output clock signals by writing to the corresponding output enable bit through SPI/I2C, or alternatively it is possible to connect the DSP IO supply and the CDCM6208V2G output supply together, in which case the CDCM6208V2G output will not turn on until the DSP supply is also valid. This second implementation avoids SPI/I2C programming.

13 Layout

13.1 Layout Guidelines

connection to the ground plane is essential.

13.2 Layout Example

Figure 58 shows a layout optimized for good thermal performance and a good power supply connection as well. The 7×7 filled via pattern facilitates both considerations. Figure 58. Recommended PCB layout of CDCM6208

Place all 0.1uF bypass caps as close as possible to device pins.

13.2.1 Reference Schematic

Figure 60. Schematic Page 1

49.9 R_SEC_PUP

Figure 61. Schematic Page 2

2 C50

run all IO from one single supply at 1.8V, 2.5V, or 3.3V. Figure 62. Schematic Page 3

series resistor between 0 and 33 ohms to improve ringing. Figure 63. Schematic Page 4

14 Device and Documentation Support

14.1 Documentation Support

14.1.1 Related Documentation

Hardware Design Guide for KeyStone Devices SPRABI2 for the SRIO interface.

14.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

14.3 Trademarks

KeyStone, E2E are trademarks of Texas Instruments. I2C is a trademark of NXP B.V. Corporation. All other trademarks are the property of their respective owners.

14.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

14.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 31-Mar-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CDCM6208V2GRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CM6208V2G CDCM6208V2GRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CM6208V2G (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 31-Mar-2016 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 31-Mar-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCM6208V2GRGZR VQFN RGZ 48 2500 367.0 367.0 38.0 CDCM6208V2GRGZT VQFN RGZ 48 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 31-Mar-2016 Pack Materials-Page 2

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Product Information

CDCM6208V2GRGZT specifications and overview.

Summary

CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

Description

CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

Source title CDCM6208V2GRGZT Datasheet(PDF) - Texas Instruments

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