CDCM61001RHBT

CDCM61001 TI | Alldatasheet

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www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 One Output, Integrated VCO, Low-Jitter Clock Generator Chip Enable and Device Reset Control Pins Available One Single-Ended/Crystal Reference Input Including 24.8832 MHz, MHz, and 3.3-V Core and I/O Power Supply 26.5625 MHz Industrial Temperature Range: C to +85 C Input Frequency Range: 21.875 MHz to 5-mm 5-mm, 32-pin, QFN (RHB) Package 28.47 MHz ESD Protection Exceeds kV (HBM) On-Chip VCO Operates in Frequency Range of 1.75 GHz to 2.05 GHz Output Available: Low Jitter Clock Driver for High-End Datacom SONET, Ethernet, Fibre Pin-Selectable Between LVPECL, LVDS, or Channel, Serial ATA, and HDTV 2-LVCMOS; Operates at 3.3 V Cost-Effective High-Frequency Crystal LVCMOS Bypass Output Available Oscillator Replacement Output Frequency Selectable by /1, /2, /3, /4, /6, from the Output Divider Supports Common LVPECL/LVDS Output Frequencies: The CDCM61001 is a highly versatile, low-jitter 62.5 MHz, 74.25 MHz, MHz, 77.76 MHz, frequency synthesizer that can generate low-jitter 100 MHz, 106.25 MHz, 125 MHz, 150 MHz, clock outputs, selectable between low-voltage 155.52 MHz, 156.25 MHz, 159.375 MHz, positive emitter coupled logic (LVPECL), low-voltage 187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz, differential signaling (LVDS), or low-voltage 311.04 MHz, 312.5 MHz, 622.08 MHz, complementary metal oxide semiconductor 625 MHz (LVCMOS) outputs, from a low-frequency crystal or LVCMOS input for a variety of wireline and data Supports Common LVCMOS Output communication applications. The CDCM61001 Frequencies: 62.5 MHz, 74.25 MHz, MHz, 77.76 MHz, configured solely through control pins. The overall 100 MHz, 106.25 MHz, 125 MHz, 150 MHz, output random jitter performance is less than 1ps, 155.52 MHz, 156.25 MHz, 159.375 MHz, RMS (from kHz to MHz), making this device a 187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz perfect choice for use in demanding SONET, Ethernet, Fibre Channel, and SAN. The Output Frequency Range: 43.75 MHz to CDCM61001 is available in a small, 32-pin, 5-mm 683.264 MHz (See Table 5-mm QFN package. Internal PLL Loop Bandwidth: 400 kHz High-Performance PLL Core: Phase Noise typically at 146 dBc/Hz at 5-MHz Offset for 625-MHz LVPECL Output Random Jitter typically at 0.509 ps, RMS (10 kHz to MHz) for 625-MHz LVPECL Output Output Duty Cycle Corrected to 50% 5%) Divider Programming Using Control Pins: Two Pins for Prescaler/Feedback Divider Three Pins for Output Divider Two Pins for Output Select space space Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DESCRIPTION, CONTINUED f =IN Output□Divider Feedback□Divider( (fOUT (1) PFD Charge□Pump Loop□Filter Feedback Divider Prescaler Output□Divider CE LVPECL/ LVCMOS/ LVDS OS[1...0] 2 3 RSTN Crystal/ LVCMOS VCO 3.3□V CDCM61001 Output Driver LVCMOS CDCM61001 SCAS869B FEBRUARY 2009 REVISED JULY 2009 www.ti.com The CDCM61001 is a high-performance, low phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with one universal output buffer that can be configured to be LVPECL, LVDS, or LVCMOS compatible. The universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading in order to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the 1.75 GHz to 2.05 GHz range. The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal or a low-noise LVCMOS input. The output has an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividered are turned off. The output frequency OUT is proportional to the frequency of the input clock IN The feedback divider, output divider, and VCO frequency set f OUT with respect to f IN For a configuration setting for common wireline and datacom applications, refer to Table For other applications, use Equation to calculate the exact crystal oscillator frequency required for the desired output. The output divider can be chosen from or through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from and and and or and respectively, also through the use of control pins. Figure shows a high-level block diagram of the CDCM61001. The device operates in a 3.3-V supply environment and is characterized for operation from C to +85 Figure CDCM61001 Block Diagram Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

(1) CDCM61001 www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) T A PACKAGED DEVICES (2) CDCM61001RHBT 32-pin QFN (RHB) package, small tape and reel C to +85 C CDCM61001RHBR 32-pin QFN (RHB) package, tape and reel (1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or refer to our web site at www.ti.com (2) These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material contentcan be accessed at www.ti.com/leadfree. GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including bromine (Br), or antimony (Sb) above 0.1%of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree. Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes. Over operating free-air temperature range (unless otherwise noted). PARAMETER VALUE UNIT V CC_OUT V CC_PLL1 V CC_PLL2 Supply voltage range (2) 0.5 to 4.6 V V CC_VCO V CC_IN V IN Input voltage range (3) 0.5 to CC_IN 0.5) V V OUT Output voltage range (3) 0.5 to CC_OUT 0.5) V I IN Input current mA I OUT Output current mA T STG Storage temperature range to +150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All supply voltages must be supplied simultaneously. (3) Input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

(1) (2) CDCM61001 SCAS869B FEBRUARY 2009 REVISED JULY 2009 www.ti.com Over operating free-air temperature range (unless otherwise noted). PARAMETER MIN NOM MAX UNIT V CC_OUT Output supply voltage 3.0 3.30 3.60 V V CC_PLL1 PLL supply voltage 3.0 3.30 3.60 V V CC_PLL2 PLL supply voltage 3.0 3.30 3.60 V V CC_VCO On-chip VCO supply voltage 3.0 3.30 3.60 V V CC_IN Input supply voltage 3.0 3.30 3.60 V T A Ambient temperature +85 C VALUE TEST VIAS PARAMETER CONDITIONS ON PAD UNIT θ JA Thermal resistance, junction-to-ambient LFM C/W θ JP (3) Thermal resistance, junction-to-pad C/W (1) The package thermal resistance is calculated in accordance with JESD and JEDEC 2S2P (high-K board). (2) Connected to GND with nine thermal vias (0.3-mm diameter). (3) θ JP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN package. Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 At V CC V to 3.6 T A C to +85 unless otherwise noted. CDCM61001 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVCMOS Input Characteristics f IN Reference input frequency 21.875 28.47 MHz V IH Input high voltage 0.6V CC V V IL Input low voltage 0.4V CC V I IH Input high current V CC 3.6 V IL V 200 µ A I IL Input low current V CC V IH 3.6 V 200 µ A Δ Δ T Reference input edge rate 20% to 80% 0.75 V/ns DutyREF Reference input duty cycle LVCMOS Output Characteristics (1) (See Figure and Figure f OSC_OUT Bypass output frequency 21.875 28.47 MHz f OUT Output frequency 43.75 250 MHz V CC V OH Output high voltage V CC min to max, I OH 100 µ A V 0.5 V OL Output low voltage V CC min to max, I OL 100 µ A 0.3 V ps, t RJIT RMS phase jitter 250 MHz (10 kHz to MHz) 0.85 RMS t SLEW-RATE Output rise/fall slew rate 20% to 80% 2.4 V/ns ODC Output duty cycle I CC Device current, LVCMOS f IN MHz, f OUT 250 MHz, C L pF 110 mA LVCMOS LVPECL Output Characteristics (2) (See Figure and Figure f OUT Output frequency 43.75 683.264 MHz V CC V CC V OH Output high voltage V 1.18 0.73 V CC V OL Output low voltage V CC V 1.55 OD Differential output voltage 0.6 1.23 V ps, t RJIT RMS phase jitter 625 MHz (10 kHz to MHz) 0.77 RMS t R F Output rise/fall time 20% to 80% 175 ps ODC Output duty cycle I CC Device current, LVPECL f IN MHz, f OUT 625 MHz 100 115 mA LVPECL LVDS Output Characteristics (3) (See Figure and Figure f OUT Output frequency 43.75 683.264 MHz OD Differential output voltage 0.247 0.454 V Δ V OD V DD magnitude change mV V OS Common-mode voltage 1.125 1.375 V Δ V OS V OS magnitude change mV ps, t RJIT RMS phase jitter 625 MHz (10 kHz to MHz) 0.73 RMS t R F Output rise/fall time 20% to 80% 255 ps ODC Output duty cycle I CC LVDS Device current, LVDS f IN MHz, f OUT 625 MHz 105 mA (1) Figure and Figure show dc and ac test setups, respectively. Jitter measurements made using 25-MHz quartz crystal in. (2) Figure and Figure show dc and ac test setups, respectively. Jitter measurements made using 25-MHz quartz crystal in. (3) Figure and Figure show dc and ac test setups, respectively. Jitter measurements made using 25-MHz quartz crystal in. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

www.ti.com Over operating free-air temperature range (unless otherwise noted). CDCM61001 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 250-MHz LVCMOS Output (1) (see Figure phn 100 Phase noise at 100-Hz offset dBc/Hz phn Phase noise at 1-kHz offset 110 dBc/Hz phn 10k Phase noise at 10-kHz offset 117 dBc/Hz phn 100k Phase noise at 100-kHz offset 120 dBc/Hz phn Phase noise at 1-MHz offset 135 dBc/Hz phn 10M Phase noise at 10-MHz offset 148 dBc/Hz phn 20M Phase noise at 20-MHz offset 148 dBc/Hz t RJIT RMS phase jitter from kHz to MHz 544 fs, RMS t PJIT Total period jitter 27.4 ps, PP Start-up time, power supply ramp time of ms, t STARTUP 2.25 ms final frequency accuracy of ppm 625-MHz LVPECL Output (2) (see Figure phn 100 Phase noise at 100-Hz offset dBc/Hz phn Phase noise at 1-kHz offset 101 dBc/Hz phn 10k Phase noise at 10-kHz offset 109 dBc/Hz phn 100k Phase noise at 100-kHz offset 112 dBc/Hz phn Phase noise at 1-MHz offset 129 dBc/Hz phn 10M Phase noise at 10-MHz offset 146 dBc/Hz phn 20M Phase noise at 20-MHz offset 146 dBc/Hz t RJIT RMS phase jitter from kHz to MHz 509 fs, RMS t PJIT Total period jitter 26.9 ps, PP Start-up time, power supply ramp time of ms, t STARTUP 2.25 ms final frequency accuracy of ppm 625-MHz LVDS Output (3) (see Figure phn 100 Phase noise at 100-Hz offset dBc/Hz phn Phase noise at 1-kHz offset 102 dBc/Hz phn 10k Phase noise at 10-kHz offset 109 dBc/Hz phn 100k Phase noise at 100-kHz offset 112 dBc/Hz phn Phase noise at 1-MHz offset 129 dBc/Hz phn 10M Phase noise at 10-MHz offset 146 dBc/Hz phn 20M Phase noise at 20-MHz offset 146 dBc/Hz t RJIT RMS phase jitter from kHz to MHz 510 fs, RMS t PJIT Total period jitter ps, PP Start-up time, power supply ramp time of ms, t STARTUP 2.25 ms final frequency accuracy of ppm (1) Figure shows test setup and uses 25-MHz quartz crystal in, V CC 3.3 T A +25 C L pF. (2) Figure shows test setup and uses 25-MHz quartz crystal in, V CC 3.3 T A +25 (3) Figure shows test setup and uses 25-MHz quartz crystal in, V CC 3.3 T A +25 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 TYPICAL OUTPUT JITTER CHARACTERISTICS (1) OUTPUT LVCMOS OUTPUT LVPECL OUTPUT LVDS OUTPUT FREQUENCY (MHz) INPUT (MHz) t RJIT (fs, RMS) t PJIT (ps PP t RJIT (fs, RMS) t PJIT (ps PP t RJIT (fs, RMS) t PJIT (ps PP 62.5 592 32.9 611 20.7 667 28.4 518 27.5 533 19.4 572 25.7 77.76 24.8832 506 29.2 526 20.9 567 26.9 100 507 24.5 510 20.7 533 26.5 106.25 26.5625 535 23.5 524 20.2 553 26.5 125 557 39.6 556 21.4 570 27.1 150 518 38.4 493 18.9 515 26.2 155.52 24.8832 498 36.9 486 19.8 502 26.7 156.25 510 37.7 503 20.7 518 26.5 159.375 26.5625 535 37.4 510 19.9 534 26.3 187.5 506 32.8 506 20.3 509 25.5 200 491 23.3 492 499 34.9 212.5 26.5625 520 47.8 509 30.8 530 37.3 250 544 27.4 541 21.4 550 27.5 311.04 24.8832 481 20.5 496 24.7 312.5 501 20.8 508 25.8 622.08 24.8832 492 27.2 500 27.2 625 515 26.9 509 (1) Figure Figure and Figure show LVCMOS, LVPECL, and LVDS test setups (respectively) using appropriate quartz crystal in, V CC 3.3 T A +25 CRYSTAL CHARACTERISTICS PARAMETER MINIMUM TYPICAL MAXIMUM UNIT Mode of oscillation Fundamental MHz Frequency 21.875 28.47 MHz Equivalent series resistance (ESR) Ω On-chip load capacitance pF Drive level 0.1 mW Maximum shunt capacitance pF Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

V _OUT CC V _VCO CC NC V _PLL2 CC PR0 NC NC CDCM61001 32 31 30 29 28 27 26 25 Thermal□Pad (must□be□soldered□to□ground) 10 11 12 13 14 15 16 OUTN OUTP CE OS1 NC OS0 NC RSTN NC OD0 NC OD1 NC OD2 PR1 OSC_OUT GND1 XIN V _INCC REG_CAP1 V _PLL1 CC REG_CAP2 CDCM61001 SCAS869B FEBRUARY 2009 REVISED JULY 2009 www.ti.com RHB PACKAGE QFN-32 (TOP VIEW) PIN FUNCTIONS TERMINAL NAME PAD NO. TYPE DIRECTION (1) VCC_OUT Power 3.3-V supply for the output buffer VCC_PLL1 Power 3.3-V supply for the PLL circuitry VCC_PLL2 Power 3.3-V supply for the PLL circuitry VCC_VCO Power 3.3-V supply for the internal VCO VCC_IN Power 3.3-V supply for the input buffers GND1 Ground Additional ground for device. (GND1 shorted on-chip to GND) GND Pad Ground Ground is on thermal pad. See Thermal Management XIN Input Parallel resonant crystal/LVCMOS input OUTP, Output Differential output pair or two single-ended outputs OUTN OSC_OUT Output Bypass LVCMOS output Capacitor for internal regulator (connect to a 10- µ F Y5V capacitor to REG_CAP1 Output GND) Capacitor for internal regulator (connect to a 10- µ F Y5V capacitor to REG_CAP2 Output GND) PR1, PR0 26, Input Pullup Prescaler and Feedback divider control pins (see Table OD2, OD1, 15, 14, Input Pullup Output divider control pins (see Table OD0 OS1, OS0 10, Input Pullup Output type select control pin (see Table CE Input Pullup Chip enable control pin (see Table RSTN Input Pullup Device reset (active low) (see Table 24, NC 27, 28, 29, No connection 30, 31, (1) Pullup and Pulldown refer to internal input resistors. See Table Pin Characteristics for typical values. Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 Table PIN CHARACTERISTICS SYMBOL PARAMETER MIN TYP MAX UNIT C IN Input capacitance pF R PULLUP Input pullup resistor 150 k Ω R PULLDOWN Input pulldown resistor 150 k Ω Figure RHB Package Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

224 A/c109

21.875□MHz to□28□.47□MHz XO LVCMOS Loop□Filter 400□kHz /c18415 /c18420 /c18424 /c18425 Feedback Divider /c1841 /c1842 /c1843 /c1844 /c1846 /c1848 Output Divider /c1845 /c1844 /c1843 Prescaler Divider FB_MUX DIV_MUX VCO 1.75□GHz to□2.05□GHz PR1 XIN CE GND1 RSTN OUTP OUTN OSC_OUT OD2 OD1 OD0 OS1 OS0 PR0 REG_CAP1 REG_CAP2 LVCMOS LVPECL LVDS LVCMOS LVCMOS CDCM61001 VCC_IN VCC_PLL1 VCC_PLL2 VCC_VDDVCC_VCO VCC_OUT CDCM61001 SCAS869B FEBRUARY 2009 REVISED JULY 2009 www.ti.com FUNCTIONAL BLOCK DIAGRAM Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 Table Common Configuration VCO OUTPUT PRESCALER FEEDBACK FREQUENCY OUTPUT FREQUENCY INPUT (MHz) DIVIDER DIVIDER (MHz) DIVIDER (MHz) APPLICATION 2000 62.5 GigE 24.75 1980 74.25 HDTV 1800 SATA 24.8832 1866.24 77.76 SONET 1800 100 PCI Express 26.5625 1912.5 106.25 Fibre Channel 2000 125 GigE 1800 150 SATA 24.8832 1866.24 155.52 SONET 1875 156.25 GigE 26.5625 1912.5 159.375 10-G Fibre Channel 1875 187.5 GigE 1800 200 PCI Express 26.5625 1912.5 212.5 4-G Fibre Channel 2000 250 GigE 24.8832 1866.24 311.04 SONET 1875 312.5 XGMII 24.8832 1866.24 622.08 SONET 1875 625 GigE Table Generic Configuration OUTPUT INPUT FREQUENCY PRESCALER FEEDBACK VCO FREQUENCY FREQUENCY RANGE (MHz) DIVIDER DIVIDER RANGE (MHz) OUTPUT DIVIDER RANGE (MHz) 21.875 to 25.62 1750 to 2050 54.6875 to 64.05 21.875 to 25.62 1750 to 2050 72.92 to 85.4 21.875 to 25.62 1750 to 2050 109.375 to 128.1 21.875 to 25.62 1750 to 2050 145.84 to 170.8 21.875 to 25.62 1750 to 2050 218.75 to 256.2 21.875 to 25.62 1750 to 2050 437.5 to 512.4 23.33 to 27.33 1750 to 2050 72.906 to 85.408 23.33 to 27.33 1750 to 2050 97.21 to 113.875 23.33 to 27.33 1750 to 2050 145.812 to 170.816 23.33 to 27.33 1750 to 2050 194.42 to 227.75 23.33 to 27.33 1750 to 2050 291.624 to 341.632 23.33 to 27.33 1750 to 2050 583.248 to 683.264 23.33 to 27.33 1750 to 2050 43.75 to 51.25 23.33 to 27.33 1750 to 2050 58.33 to 68.33 23.33 to 27.33 1750 to 2050 87.5 to 102.5 23.33 to 27.33 1750 to 2050 116.66 to 136.66 23.33 to 27.33 1750 to 2050 175 to 205 23.33 to 27.33 1750 to 2050 350 to 410 24.305 to 28.47 1750 to 2050 72.915 to 85.41 24.305 to 28.47 1750 to 2050 97.22 to 113.88 Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

www.ti.com Table Generic Configuration (continued) OUTPUT INPUT FREQUENCY PRESCALER FEEDBACK VCO FREQUENCY FREQUENCY RANGE (MHz) DIVIDER DIVIDER RANGE (MHz) OUTPUT DIVIDER RANGE (MHz) 24.305 to 28.47 1750 to 2050 145.83 to 170.82 24.305 to 28.47 1750 to 2050 194.44 to 227.76 24.305 to 28.47 1750 to 2050 291.66 to 341.64 24.305 to 28.47 1750 to 2050 583.32 to 683.28 Table Programmable Prescaler and Feedback Divider Settings CONTROL INPUTS PFD FREQUENCY PRESCALER FEEDBACK PR1 PR0 DIVIDER DIVIDER MINIMUM MAXIMUM 24.305 28.47 23.33 27.33 23.33 27.33 21.875 25.62 Table Programmable Output Divider CONTROL INPUTS OD2 OD1 OD0 OUTPUT DIVIDER Reserved Reserved Table Programmable Output Type CONTROL INPUTS OS1 OS0 OUTPUT TYPE LVCMOS, OSC_OUT Off LVDS, OSC_OUT Off LVPECL, OSC_OUT Off LVPECL, OSC_OUT On Table Output Enable CONTROL INPUT OPERATING CE CONDITION OUTPUT Power Down Hi-Z Normal Active Table Reset CONTROL INPUT OPERATING RSTN CONDITION OUTPUT Device Reset Hi-Z PLL Recalibration Hi-Z Normal Active Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

Supply□Current□(mA) 0 200 400 600 800 Output□Frequency□(MHz) Output-divide-by-8 Output-divide-by-6 Output-divide-by-4 Output-divide-by-3 Output-divide-by-2 Output-divide-by-1 110 105 100 Supply□Current□(mA) 0 200 400 600 800 Output□Frequency□(MHz) Output-divide-by-8 Output-divide-by-6 Output-divide-by-4 Output-divide-by-3 Output-divide-by-2 Output-divide-by-1 CDCM61001 www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 Over operating free-air temperature range (unless otherwise noted). TYPICAL CURRENT CONSUMPTION FOR LVPECL OUTPUT vs OUTPUT FREQUENCY Figure TYPICAL CURRENT CONSUMPTION FOR LVDS OUTPUT vs OUTPUT FREQUENCY Figure Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

Supply□Current□(mA) 0 50 100 150 200 250 300 Output□Frequency□(MHz) Output-divide-by-8 Output-divide-by-6 Output-divide-by-4 Output-divide-by-3 Output-divide-by-2 0.77 0.76 0.75 0.74 0.73 0.72 0.71 0.70 Differential□Output□Voltage,□V (V) OD 0 100 200 300 400 500 600 700 Output□Frequency□(MHz) CDCM61001 SCAS869B FEBRUARY 2009 REVISED JULY 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating free-air temperature range (unless otherwise noted). TYPICAL CURRENT CONSUMPTION FOR LVCMOS OUTPUT WITH 5-pF LOAD vs OUTPUT FREQUENCY Figure TYPICAL LVPECL DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT FREQUENCY Figure Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

0.42 0.40 0.38 0.36 0.34 0.32 0.30 Differential□Output□Voltage,□V (V) DO 0 100 200 300 400 500 600 700 Output□Frequency□(MHz) 3.30 3.25 3.20 3.15 3.10 3.05 3.00 Output□Voltage,□V (V) OUT 50 100 150 200 250 Output□Frequency□(MHz) CDCM61001 www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 TYPICAL CHARACTERISTICS (continued) Over operating free-air temperature range (unless otherwise noted). TYPICAL LVDS DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT FREQUENCY Figure TYPICAL LVCMOS OUTPUT VOLTAGE WITH 5-pF LOAD vs OUTPUT FREQUENCY Figure Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

5□pF L VCMOS L VCMOS Phase□Noise Analyzer L VPECL Oscilloscope 50 /c8750 /c87 VCC 2V/c45 L VPECL 150 /c87 50 /c87 Phase□Noise Analyzer 150 /c87 CDCM61001 SCAS869B FEBRUARY 2009 REVISED JULY 2009 www.ti.com This section describes the function of each block for the CDCM61001. Figure through Figure illustrate how the device should be set up for a variety of output configurations. Figure LVCMOS Output Loading During Device Test Figure 10. LVCMOS AC Configuration During Device Test Figure 11. LVPECL DC Configuration During Device Test Figure 12. LVPECL AC Configuration During Device Test Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

L VDS 100 /c87 Oscilloscope L VDS Phase□Noise Analyzer 50 /c87 Yx Yx VOL VOH VOD 0□V 80% 20% t r tf VOUTpp CDCM61001 www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 Figure 13. LVDS DC Configuration During Device Test Figure 14. LVDS AC Configuration During Device Test Figure 15. Output Voltage and Rise/Fall Times Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

(PLL) Configuring the PLL Crystal Input Interface CDCM6100110□pF XIN CDCM61001 SCAS869B FEBRUARY 2009 REVISED JULY 2009 www.ti.com The CDCM61001 includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a crystal input interface, which can also accept an LVCMOS signal, a phase frequency detector (PFD), a charge pump, an on-chip loop filter, and prescaler and feedback dividers. Completing the CDCM61001 device are the output divider and universal output buffer. The PLL is powered by on-chip, low-dropout (LDO) linear voltage regulators. The regulated supply network is partitioned such that the sensitive analog supplies are powered from separate LDOs rather than the digital supplies which use a separate LDO regulator. These LDOs provide isolation for the PLL from any noise in the external power-supply rail. The REG_CAP1 and REG_CAP2 pins should each be connected to ground by 10- µ F capacitors to ensure stability. The CDCM61001 permits PLL configurations to accommodate the various input and output frequencies listed in Table and Table These configurations are accomplished by setting the prescaler divider, feedback divider and output divider. The various dividers are managed by setting the device control pins as shown in Table and Table For each control pin that must be set to a '1', it is recommended to use an external onboard 10-k Ω resistor to the chip supply. The recommended oscillation mode for the input crystal is fundamental mode, with a parallel resonance circuit configuration for the crystal. Crystal load capacitance refers to all capacitances in the oscillator feedback loop. It is equal to the amount of capacitance seen between the terminals of the crystal in the circuit. For parallel resonant mode circuits, the correct load capacitance is necessary to ensure the oscillation of the crystal within the expected parameters. The CDCM61001 implements an input crystal oscillator circuit architecture that requires the input crystal to interface with one terminal while its other terminal is tied to ground. In this crystal interface, it is important to account for all sources of capacitance when calculating the correct value for the discrete capacitor component, C L for a given design. The CDCM61001 has been characterized with 20-pF parallel resonant crystals. The input crystal oscillator stage in the CDCM61001 is designed to minimize the capacitance required to be added for the 24.8832-MHz, 25-MHz, or 26.5625-MHz crystals to resonate at the correct frequency. The capacitor values shown in Figure were determined using the 20-pF parallel resonant crystals at 24.8832 MHz, MHz, or 26.5625 MHz and checked for minimal ppm error measured at the OSC_OUT pin. This error value can also be calculated from the discrete capacitor component, C L required on the XIN pin if the input capacitance on the XIN pin is known (10 pF maximum), in order to match the 20-pF rating. However, it is recommended to use a 10-pF parallel resonant crystal to drive the CDCM61001 and in this case, no additional external capacitors are needed to tune the crystal frequency. Table lists several recommended crystals and the respective manufacturer of each. Figure 16. Crystal Input Interface Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

CDCM610010.1 F/c109 XINL VCMOS Phase Frequency Detector (PFD) Charge Pump (CP) On-Chip PLL Loop Filter 15□k/c87 20□k/c87473.5□pF Charge□Pump Output VCO□Control Prescaler Divider and Feedback Divider CDCM61001 www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 Table Recommended Crystal Manufacturers MANUFACTURER PART NUMBER Ecliptek ECCM1B Epson-Toyocom TSX-5032 Abracon ABM3 Alternately, the CDCM61001 can be operated with an external LVCMOS reference input applied to the XIN pin, which has internal biasing. Figure shows the recommended method to interface an LVCMOS signal with the CDCM61001 through an ac coupling capacitor. Figure 17. LVCMOS Input Interface The PFD takes inputs from the input interface and the feedback divider and produces an output that depends on the phase and frequency differences between the two inputs. The allowable range of frequencies at the PFD inputs is 21.875 MHz to 28.47 MHz. The charge pump is controlled by the PFD, which dictates either to pump up or down in order to charge or discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then converted to a voltage that drives the control voltage node of the internal VCO through the on-chip loop filter. The charge pump current is preset to 224 µ A and cannot be changed. Figure shows the on-chip active loop filter topology implemented in the device. This design corresponds to a PLL bandwidth of 400 kHz for a PFD in the range of 21.875 MHz to 28.47 MHz, and a charge pump current of 224 µ Figure 18. On-Chip PLL Loop Filter Topology The VCO output is routed to the prescaler divider and then to the feedback divider. The prescaler divider and feedback divider are set in tandem with each other, according to the control pin settings given in Table The allowable combinations of the two dividers ensure that the VCO frequency and the PFD frequency are within the specified limits. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

www.ti.com The CDCM61001 includes an on-chip, LC oscillator-based VCO with low phase noise covering a frequency range of 1.75 GHz to 2.05 GHz. The VCO must be calibrated to ensure proper operation over the valid device operating conditions. VCO calibration is controlled by a divided-down reference clock input. This calibration requires that the PLL be set up properly to lock the PLL loop and that the reference clock input be present. During the first device initialization after power-up, which occurs after the Power On Reset is released (2.64 V or lower, over valid device operating conditions) or a device reset with the RSTN pin, a VCO calibration sequence is initiated after 16384 Reference Input Clock Cycles. The VCO calibration then takes about µ s over the allowable range of the reference clock input. The VCO calibration can also be reinitiated with a pulse on the RSTN pin at any time after POR is released on power-up; the RSTN pulse must be at least 100 ns wide. The output from the prescaler divider is also routed to the output divider. The output divider can be set with control pins according to Table The output buffer can be set to LVPECL or LVDS or LVCMOS, according to Table OSC_OUT is an LVCMOS output that can be used in test mode to monitor proper loading of the input crystal in order to achieve the necessary crystal frequency with the least error. The output buffer is disabled during VCO calibration and is enabled only after calibration is complete. The output buffer on the CDCM61001 can also be disabled, along with other sections of the device, using the CE pin according to Table Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

t =REF fREF Power□Supply□(V) Time□(s) 2.27□V 2.64□V tpul tpuh trsu tdelay tVCO_CAL tPLL_LOCK Power□up Reference Startup Delay VCO□Calibration PLL□Lock CDCM61001 www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 The CDCM61001 startup time can be estimated based on the parameters defined in Table and graphically shown in Figure Table 10. Start-up Time Dependencies FORMULA/METHOD OF PARAMETER DEFINITION t REF Reference clock period frequency in seconds. Power-supply rise time to low limit of Power Time required for power t pul Power-up time (low limit) On Reset (POR) trip point supply to ramp to 2.27 V Power supply rise time to high limit of POR Time required for power t puh Power-up time (high limit) trip point supply to ramp to 2.64 V After POR releases, the Colpits oscillator is 500 µ s best-case and 800 µ s enabled. This start-up time is required for the worst-case (for a crystal t rsu Reference start-up time oscillator to generate the requisite signal input). levels for the delay block to be clocked by s (for an LVCMOS input). the reference input. Internal delay time generated from the t delay Delay time reference clock. This delay provides time for t delay 16384 t ref the reference oscillator to stabilize. VCO Calibration Time generated from the reference clock. This process selects the t VCO_CAL VCO calibration time t VCO_CAL 550 t ref operating point for the VCO based on the PLL settings. Based on the 400-kHz loop Time required for PLL to lock within ppm t PLL_LOCK PLL lock time bandwidth, the PLL settles in of f REF τ or 12.5 µ Figure 19. Start-up Time Dependencies Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

www.ti.com The CDCM61001 start-up time limits, t MAX and t MIN can be calculated as follows: t MAX t puh t rsu t delay t VCO_CAL t PLL_LOCK t MIN t pul t rsu t delay t VCO_CAL t PLL_LOCK As a result of the different possible configurations of the CDCM61001, Table is intended to provide enough information on the estimated current consumption of the device. Unless otherwise noted, V CC 3.3 V and T A +25 Table 11. Estimated Block Power Consumption EXTERNAL RESISTOR POWER CURRENT CONSUMPTION IN-DEVICE POWER DISSIPATION DISSIPATION BLOCK CONDITION (mA) (mW) (mW) Entire device, Output off, no termination 214.5 core current resistors LVPECL output, active mode 42.4 LVCMOS output pair, static 4.5 14.85 LVCMOS output pair, Output buffer transient, L load, 'f' MHz V f OUT L V f OUT L output frequency LVDS output, active mode Divide enabled, divide 16.5 Divide enabled, divide Divide circuitry Divide enabled, divide 49.5 Divide enabled, divide From Table the current consumption can be calculated for any configuration. For example, the current for the entire device with one LVPECL output in active mode can be calculated by adding up the following blocks: core current, LVPECL output buffer current, and the divide circuitry current. The overall in-device power consumption can also be calculated by summing the in-device power dissipated in each of these blocks. As an example scenario, let us consider the use case of a crystal input frequency of MHz and device output frequency of 312.5 MHz in LVPECL mode. For this case, the typical overall power dissipation can be calculated as: 3.3 V (65 10) mA 340.2 mW Because the LVPECL output has external resistors and the power dissipated by these resistors is mW, the typical overall in-device power dissipation is: 343.5 mW mW 290.2 mW When the LVPECL output is active, the average voltage is approximately 1.9 V on each output as calculated from the LVPECL V OH and V OL specifications. Therefore, the power dissipated in each emitter resistor is approximately (1.9 /150 Ω mW. When the LVCMOS output is active and drives a load capacitance, C L the overall LVCMOS output current consumption is the sum of a static pre-driver current and a dynamic switching current (which is a function of the output frequency and the load capacitance). Let us consider another use case of a crystal input frequency of 26.5625 MHz and device output frequency of 212.5 MHz in LVCMOS mode and driving a 5-pF load capacitance. For this case, the typical overall power dissipation can be calculated as: 3.3 V (65 21.4) mA 334.62 mW Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

0,3□mm (typ) 0,7□mm (typ) 3,0□mm (min) Power-Supply Filtering CDCM61001 www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 Power consumption of the CDCM61001 can be high enough to require attention to thermal management. For reliability and performance reasons, the die temperature should be limited to a maximum of +125 That is, as an estimate, T A (ambient temperature) plus device power consumption times θ JA should not exceed +125 The device package has an exposed pad that provides the primary heat removal path as well as an electrical grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure Figure 20. Recommended PCB Layout for CDCM61001 PLL-based frequency synthesizers are very sensitive to noise on the power supply, which can dramatically increase the jitter of the PLL. This characteristic is especially true for analog-based PLLs. Thus, it is essential to reduce noise from the system power supply, especially when jitter/phase noise is very critical to applications. A PLL would have attenuated jitter as a result of power-supply noise at frequencies beyond the PLL bandwidth because of attenuation by the loop response. Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use these bypass capacitors, they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It is recommended to add as many high-frequency (for example, 0.1- µ bypass capacitors as there are supply pins in the package. The CDCM61001 power-supply requirements can be grouped into two sets: the analog supply line and the output/input supply line. The analog supply line consists of the following power-supply pins on the CDCM61001: VCC_PLL1, VCC_PLL2, and VCC_VCO. These pins can be shorted together. The output/input supply line consists of the VCC_OUT and the VCC_IN power-supply pins on the CDCM61001. These pins can be shorted together. Inserting a ferrite bead between the analog supply line and the output/input supply line isolates the high-frequency switching noises generated by the device input and output, preventing them from leaking into the sensitive analog supply line. Choosing an appropriate ferrite bead with very low dc resistance is important because it is imperative to provide adequate isolation between the sensitive analog supply line and the other board supply lines, and to maintain a voltage at the analog power-supply pins of the CDCM61001 that is greater than the minimum voltage required for proper operation. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

C 0.1 /c109F□(x2) C

10 F/c109

C C

0.1 F□(x3)/c109

Ferrite□Bead Output Termination LVPECL Termination CDCM61001 L VPECL 82 /c8782 /c87 130 /c87 130 /c87 CDCM61001 L VPECL 50 /c8750 /c87150 /c87150 /c87 VBB CDCM61001 SCAS869B FEBRUARY 2009 REVISED JULY 2009 www.ti.com Figure shows a general recommendation for decoupling the power supply. Figure 21. Recommended Power-Supply Decoupling The CDCM61001 is a 3.3-V clock driver with the following output options: LVPECL, LVDS, or LVCMOS. The CDCM61001 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL is Ω to CC but this dc voltage is not readily available on most PCBs. Thus, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (dc) and ac-coupled cases, as shown in Figure and Figure It is recommended to place all resistive components close to either the driver end or the receiver end. If the supply voltage of the driver and receiver are different, ac-coupling is required. Figure 22. LVPECL Output DC Termination Figure 23. LVPECL Output AC Termination Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

R =□22 /c87S CDCM61001 www.ti.com SCAS869B FEBRUARY 2009 REVISED JULY 2009 The proper LVDS termination for signal integrity over two Ω lines is 100 Ω between the outputs on the receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs, as shown in Figure and Figure It is recommended to place all resistive components close to either the driver end or the receiver end. If the supply voltage of the driver and the receiver are different, ac-coupling is required. Figure 24. LVDS Output DC Termination Figure 25. LVDS Output AC Termination Series termination is a common technique used to maintain the signal integrity for LVCMOS drivers, if connected to a receiver with a high-impedance input with a pull-up or pulldown resistor. For series termination, a series resistor S is placed close to the driver, as shown in Figure The sum of the driver impedance and R S should be close to the transmission line impedance, which is usually Ω Because the LVCMOS driver in the CDCM61001 has an impedance of Ω R S is recommended to be Ω to maintain proper signal integrity. Figure 26. LVCMOS Output Termination Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCM61001

www.ti.com Because the LVPECL common-mode voltage is different from the HCSL common-mode voltage, ac-coupled termination is used. The 150- Ω resistor ensures proper biasing of the CDCM61001 LVPECL output stage, while the 471- Ω and 56- Ω resistor network biases the HCSL receiver input stage, as shown in Figure Figure 27. LVPECL to HCSL Interface space Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May, 2009) to Revision B Page Added sentence about parallel resonant crystal to last paragraph of Crystal Input Interface section Updated Figure Revised text in LVCMOS Termination section Updated Figure Changes from Original (February, 2009) to Revision A Page Added Interfacing Between LVPECL and HCSL section Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s): CDCM61001

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCM61001RHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCM61001RHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2009 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2009 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCM61001RHBR QFN RHB 32 3000 346.0 346.0 29.0 CDCM61001RHBT QFN RHB 32 250 190.5 212.7 31.8 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2009 Pack Materials-Page 2

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Summary

One Output, Integrated VCO, Low-Jitter Clock Generator

Description