CDCM1804RGERG4

CDCM1804_17 TI1 | Alldatasheet

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FEATURES

VSS(1) V DD1 V DD1 VDD3 EN VDDPECL IN IN VDDPECL VBB 24 23 22 21 20 19 7 8 9 10 11 12 V DD0 V DD0 VSS VDD2 VDD2 RGE PACKAGE (TOP VIEW) (1) Thermal pad must be connected to VSS. P0024-01

DESCRIPTION

(1) Thermal pad must be connected to VSS. P0025-01 V DD1 V DD1 VDD3 EN VDDPECL IN IN VDDPECL VBB V DD0 V DD0 VSS VDD2 VDD2 VSS(1) RTH PACKAGE (TOP VIEW) CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER The CDCM1804 is characterized for operation from C to Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and For use in single-ended driver applications, the CDCM1804 also provides a VBB output terminal that One LVCMOS Single-Ended Output can be directly connected to the unused input as a Programmable Output Divider for Two common-mode voltage reference. LVPECL Outputs and LVCMOS Output Low-Output Skew ps (Typical) for Clock-Distribution

Applications

Outputs; 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise V CC Range V 3.6 V Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS Differential Input Stage for Wide Common-Mode Range Provides VBB Bias Voltage Output for Single-Ended Input Signals Receiver Input Threshold mV 24-Terminal QFN Package mm mm) Accepts Any Differential Signaling: LVDS, HSTL, CML, VML, SSTL-2, and Single-Ended: LVTTL/LVCMOS The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with mini- mum skew for clock distribution. The CDCM1804 is specifically designed for driving 50- Ω transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS output Y3. This output is delayed by 1.6 ns over the three LVPECL output stages to minimize noise impact during signal tran- sitions. The CDCM1804 has three control terminals, S0, S1, and S2, to select different output mode settings. The S[2:0] terminals are 3-level inputs and therefore allow up to combinations. Additionally, an enable terminal (EN) is provided to disable or enable all outputs simultaneously. The EN terminal is a 3-level input as well and extends the number of settings to 54. See Table for details. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2003 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com Control VBB LVPECL LVPECL LVPECL Y3LVCMOS Div 1 Div 2 Div 4 Div 8 Div 16 Bias Generator VDD − 1.3 V (Imax < 1.5 mA) IN IN ENS0 B0059-01 CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 FUNCTIONAL BLOCK DIAGRAM

www.ti.com CONTROL TERMINAL SETTINGS CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 TERMINAL FUNCTIONS TERMINAL I/O NO. EN I ENABLE: Enables or disables all outputs simultaneously. The EN terminal offers three (with 60-k Ω pullup) different configurations: tied to GND (logic 0), external 60-k Ω pulldown resistor (pull to V DD /2), or left floating (logic 1); EN outputs on according to S[2:0] settings EN V DD /2: outputs on according to S[2:0] settings EN outputs Y[3:0] off (high impedance) See Table for details. IN, IN I (differential) Differential input clock: Input stage is sensitive and has a wide common-mode range. Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS, CML, HSTL). Because the input is high-impedance, it is recommended to terminate the PCB transmission line before the input (e.g., with 100 Ω across input). Input can also be driven by single-ended signal if the complementary input is tied to VBB. A more-advanced scheme for single-ended signals is given in the Application Information section near the end of this document. The inputs employ an ESD structure protecting the inputs in case of an input voltage exceeding the rails by more than ~0.7 Reverse biasing of the IC through these inputs is possible and must be prevented by limiting the input voltage V DD S[2:0] 18, 19, I Select mode of operation: Defines the output configuration of Y[3:0]. Each terminal (with 60-k Ω pullup) offers three different configurations: tied to GND (logic 0), external 60-k Ω pulldown resistor (pull to V DD /2), or left floating (logic 1); see Table for details. VBB O Bias voltage output to be used to bias unused complementary input IN for single-ended input signals. The output voltage of VBB is V DD 1.3 When driving a load, the output current drive is limited to about 1.5 mA. V SS Supply Device ground V DD PECL Supply Supply voltage LVPECL input internal logic V DD [2:0] 11, 14, Supply LVPECL output supply voltage for output Y[2:0]. Each output can be disabled by pulling 17, 20, the corresponding V DD x to GND. CAUTION: In this mode, no voltage from outside may be forced, because internal diodes could be forced in forward direction. Thus, it is recommended to disconnect the output. V DD Supply Supply voltage LVCMOS output. The LVCMOS output can be disabled by pulling V DD to GND. CAUTION: In this mode, no voltage from outside may be forced because internal diodes could be forced in a forward direction. Thus, it is recommended to leave unconnected, tied to GND, or terminated into GND. Y[2:0] 15, O (LVPECL) LVPECL clock outputs. These outputs provide low-skew copies of IN or down-divided Y[2:0] 10, 16, copies of clock IN based on selected mode of operation S[2:0]. If an output is unused, the output can simply be left open to save power and minimize noise impact to the remaining outputs. O LVCMOS clock output. This output provides copy of IN or down-divided copy of clock IN based on selected mode of operation S[2:0]. Also, this output can be disabled when V DD becomes tied to GND. The CDCM1804 has three control terminals (S0, S1, and S2) and an enable terminal (EN) to select different output mode settings. All four inputs (S0, S1, S2, and EN) are 3-level inputs offering different combinations. In addition, the EN input allows the disabling of all outputs and forcing them into a high-z (or 3-state) output state when pulled to GND. Each control input incorporates a 60-k Ω pullup resistor. Thus, it is easy to choose the input setting by designing a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero. Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to V DD /2, the installed resistor must be a 60-k Ω pulldown to GND with a 10% tolerance or better.

www.ti.com RS0 = 0 Ω EN CDCM1804 RS1 = 60 kΩ REN = Open Setting for Mode 13: EN = 1 S2 = VDD/2 S1 = VDD/2 S0 = 0 RS2 = 60 kΩ S0084-01 CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 Figure Control Terminal Setting for Example Table Selection Mode Table LVPECL (1) LVCMOS MODE EN x x x Off (high-z) Off (high-z) V DD Off (high-z) Off (high-z) Off (high-z) V DD Off (high-z) V DD V DD Off (high-z) V DD Off (high-z) Off (high-z) V DD V DD V DD V DD V DD Off (high-z) V DD V DD V DD V DD V DD V DD V DD V DD V DD V DD Off (high-z) V DD V DD V DD Off (high-z) V DD V DD V DD (1) The LVPECL outputs are open-emitter stages. Thus, if you leave the unused LVPECL outputs Y0, Y1, or unconnected, then the current consumption is minimized and noise impact to remaining outputs is neglectable. Also, each output can be individually disabled by connecting the corresponding V DD input to GND.

www.ti.com ABSOLUTE MAXIMUM RATINGS CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 Table Selection Mode Table (continued) LVPECL (1) LVCMOS MODE EN V DD Off (high-z) V DD V DD V DD V DD V DD V DD V DD V DD V DD Off (high-z) Off (high-z) V DD V DD Off (high-z) V DD Off (high-z) V DD V DD Off (high-z) V DD Off (high-z) V DD V DD Off (high-z) Off (high-z) V DD V DD V DD V DD V DD V DD V DD V DD V DD V DD V DD V DD Off (high-z) V DD V DD V DD Off (high-z) V DD V DD Off (high-z) V DD V DD V DD Off (high-z) V DD V DD V DD Off (high-z) Off (high-z) V DD V DD Off (high-z) V DD V DD V DD Off (high-z) V DD V DD V DD Rsv V DD V DD Reserved Reserved Reserved Reserved Rsv V DD N/A Low Low Low V DD V DD V DD over operating free-air temperature (unless otherwise noted) (1) V DD Supply voltage 0.3 V to 3.8 V V I Input voltage 0.2 V to DD 0.2 V O Output voltage 0.2 V to DD 0.2 Differential short-circuit current, Yn, Yn I OSD Continuous Electrostatic discharge (HBM 1.5 k Ω 100 pF), ESD >2000 V Moisture level 24-terminal QFN package (solder reflow temperature of 235 MSL T stg Storage temperature C to 150 C T J Maximum junction temperature 125 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

www.ti.com RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS LVPECL INPUT IN, IN LVPECL OUTPUT DRIVER Y[2:0], Y[2:0] LVPECL INPUT-TO-LVPECL OUTPUT PARAMETERS CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 MIN TYP MAX UNIT V DD Supply voltage 3.3 3.6 V T A Operating free-air temperature C over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f clk Input frequency 800 MHz V CM High-level input common mode V DD 0.3 V Input voltage swing between IN and IN (1) 500 1300 V IN mV Input voltage swing between IN and IN (2) 150 1300 I IN Input current V I V DD or V µ A R IN Input impedance 300 k Ω C I Input capacitance at IN, IN pF (1) Is required to maintain ac specifications (2) Is required to maintain device functionality PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f clk Output frequency, see Figure 800 MHz V OH High-level output voltage Termination with Ω to V DD V V DD 1.18 V DD 0.81 V V OL Low-level output voltage Termination with Ω to V DD V V DD 1.98 V DD 1.55 V Output voltage swing between Y and V O Termination with Ω to V DD V 500 mV Y see Figure I OZL V DD 3.6 V O V Output 3-state current µ A I OZH V DD 3.6 V O V DD 0.8 V 20% to 80% of V OUTPP see Fig- t r f Rise and fall time 200 350 ps ure Output skew between any LVPECL t skpecl(o) See Note A in Figure ps output Y[2-0] and Y[2-0] Crossing point-to-crossing point dis- t Duty Output duty-cycle distortion (1) ps tortion t sk(pp) Part-to-part skew Any see Note B in Figure ps C O Output capacitance V O V DD or GND pF LOAD Expected output load Ω (1) For an 800-MHz signal, the 50-ps error would result in a duty-cycle distortion of when driven by an ideal clock input signal. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVPECL INPUT-TO-LVPECL OUTPUT PARAMETER t pd(lh) Propagation delay rising edge VOX to VOX 320 600 ps t pd(hl) Propagation delay falling edge VOX to VOX 320 600 ps t sk(p) LVPECL pulse skew VOX to VOX, see Note C in Fig- 100 ps ure

www.ti.com LVCMOS OUTPUT PARAMETER, JITTER CHARACTERISTICS CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f clk OUTPUT frequency, see Figure (1) 200 MHz Output skew between the LVCMOS out- t skLVCMOS(o) VOX to V DD /2, see Figure 1.3 1.6 2.1 ns put and LVPECL outputs Y[2:0] t sk(pp) Part-to-part skew Y3, see Note B in Figure 300 ps V DD min to max I OH 100 µ A V DD 0.1 V OH High-level output voltage V DD V I OH mA 2.4 V V DD V I OH mA V DD min to max I OL 100 µ A 0.1 V OL Low-level output voltage V DD V I OL mA 0.5 V V DD V I OL mA 0.8 I OH High-level output current V DD 3.3 V V O 1.65 V mA I OL Low-level output current V DD 3.3 V V O 1.65 V mA I OZ High-impedance-state output current V DD 3.6 V V O V DD or V µ A C O Output capacitance V DD 3.3 V pF t Duty Output duty cycle distortion (2) Measured at V DD 150 150 ps Propagation delay rising edge from IN to t pd(lh) VOX to V DD load, see Figure 1.6 2.6 ns Propagation delay falling edge from IN t pd(hl) VOX to V DD load, see Figure 1.6 2.6 ns to t r Output rise slew rate 20% to 80% of swing, see Figure 1.4 2.3 V/ns t f Output fall slew rate 80% to 20% of swing, see Figure 1.4 2.3 V/ns (1) Operating the CDCM1804 LVCMOS output above the maximum frequency does not cause a malfunction to the device, but the output will not achieve enough signal swing to meet the output specification. Therefore, the CDCM1804 can be operated at higher frequencies, while the LVCMOS output becomes unusable. (2) For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of when driven by an ideal clock input signal. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT kHz to MHz, f out 250 MHz to 800 MHz, 0.15 divide-by-1 mode Additive phase jitter from input to t jitterLVPECL ps rms LVPECL output Y[2:0], see Figure kHz to MHz, f out 250 MHz to 800 MHz, 0.25 divide-by-1 mode kHz to MHz, f out 250 MHz, 0.25 divide-by-1 mode Additive phase jitter from input to t jitterLVCMOS ps rms LVCMOS output Y3, see Figure kHz to MHz, f out 250 MHz, 0.4 divide-by-1 mode

www.ti.com −160 −155 −150 −145 −140 −135 −130 −125 −120 −115 −110 VDD = 3.3 V TA = 25° C f = 622 MHz ÷ 1 Mode Additive Phase Noise − dBc/Hz f − Frequency Offset From Carrier − Hz 10 100 1k 100M10k 100k 10M1M G001 −160 −155 −150 −145 −140 −135 −130 −125 −120 −115 −110 −105 −100 VDD = 3.3 V TA = 25° C f = 250 MHz ÷ 1 Mode Additive Phase Noise − dBc/Hz f − Frequency Offset From Carrier − Hz 10 100 1k 100M10k 100k 10M1M G002 f − Frequency − GHz 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 LVPECL Output Swing − V TA = 25° C Load = 50 Ω to VDD − 2 V VDD = 3.6 V VDD = 3.3 V VDD = 3 V G003 f − Frequency − MHz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 25 75 125 175 225 275 325 375 425 475 LVCMOS Output Swing − V TA = 25° C Load = See Figure 10 VDD3 = 3 V VDD3 = 3.6 V VDD = 3.3 V G004 CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 ADDITIVE PHASE NOISE ADDITIVE PHASE NOISE vs vs FREQUENCY OFFSET FROM CARRIER LVPECL FREQUENCY OFFSET FROM CARRIER LVCMOS Figure Figure LVPECL OUTPUT SWING LVCMOS OUTPUT SWING vs vs FREQUENCY FREQUENCY Figure Figure

www.ti.com SUPPLY CURRENT ELECTRICAL CHARACTERISTICS f − Frequency − MHz 110 120 130 140 150 160 170 180 100 300 500 700 900 1100 1300 1500 IDD − Supply Current − mA VDD = 3.3 V TA = 25° C Load = 10 pF/1k/1k for LVCMOS 50 Ω to VDD − 2 V for LVPECL

3 LVPECL Outputs (÷ 1),

LVCMOS Output (÷ 4)

3 LVPECL Outputs (÷ 1)

Running, LVCMOS Output Off

2 LVPECL Outputs (÷ 1),

LVCMOS Output (÷ 4) G005 CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT All outputs enabled and terminated with Ω to V DD V on LVPECL outputs and pF on LVCMOS Full load 160 output, f 800 MHz for LVPECL outputs and 200 MHz for Supply current mA LVCMOS, V DD 3.3 V I DD Outputs enabled, no output load, f 800 MHz for LVPECL No load 110 outputs and 200 MHz for LVCMOS, V DD 3.6 V Supply current saving per LVPECL f 800 MHz for LVPECL output, V DD 3.3 V mA output stage disabled, no load All outputs in the high-impedance state by control logic, f I DDZ Supply current, 3-state Hz, 0.5 mA V DD 3.6 V SUPPLY CURRENT vs FREQUENCY Figure

www.ti.com PACKAGE THERMAL RESISTANCE CONTROL INPUT CHARACTERISTICS BIAS VOLTAGE VBB CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT QFN-24 package thermal resistance (1) 4-layer JEDEC test board (JESD51-7), R θ JA-1 106.6 C/W airflow ft/min QFN-24 package thermal resistance 4-layer JEDEC test board (JESD51-7) with four R θ JA-2 with thermal vias in PCB (1) thermal vias of 22-mil diameter each, 55.4 C/W airflow ft/min (1) It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good heat sink. Example: Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias: T Chassis C (temperature of the chassis) P effective I max V max 110 mA 3.6 V 396 mW (maximum power consumption inside the package) θ T Junction R θ JA-2 P effective 55.45 C/W 396 mW 21.96 C T Junction θ T Junction T Chassis 21.96 C C 107 C (the maximum junction temperature of T die-max 125 C is not violated) over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t su Setup time, S0, S1, S2, and EN terminals before clock IN ns t h Hold time, S0, S1, S2, and EN terminals after clock IN ns Time between latching the EN low transition and when all t (disable) outputs are disabled (how much time is required until the ns outputs turn off) Time between latching the EN low-to-high transition and when t (enable) outputs are enabled based on control settings (how much time µ s passes before the outputs carry valid signals) Rpullup Internal pullup resistor on S[2:0] and EN inputs k Ω V IH(H) Three-level input high, S0, S1, S2, and EN terminals (1) 0.9 V DD V V IM(M) Three-level input MID, S0, S1, S2, and EN terminals 0.3 V DD 0.7 V DD V V IL(L) Three-level input low, S0, S1, S2, and EN terminals 0.1 V DD V I IH V I V DD µ A Input current, S0, S1, S2, and EN terminals I IL V I GND µ A (1) Leaving this terminal floating automatically pulls the logic level high to V DD through an internal pullup resistor of k Ω over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBB Output reference voltage V DD V 3.6 I BB 0.2 mA V DD 1.4 V DD 1.2 V

www.ti.com I − Load − mA 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 −5 0 5 10 15 20 25 30 35 VDD = 3.3 V VBB − Output Reference Voltage − V G006 CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 OUTPUT REFERENCE VOLTAGE (VBB) vs LOAD Figure

www.ti.com PARAMETER MEASUREMENT INFORMATION IN IN tpd(LH1) tpd(LH2) tskLVCMOS(o) 0.5 × VDD3 NOTES: A. Output skew, tsk(o), is calculated as the greater of: − The difference between the fastest and the slowest tpd(LH)n (n = 0… 2) − The difference between the fastest and the slowest tpd(HL)n (n = 0… 2) B. Part-to-part skew, tsk(pp), is calculated as the greater of: − The difference between the fastest and the slowest tpd(LH)n (n = 0… 2 for LVPECL, n = 3 for LVCMOS) across multiple devices − The difference between the fastest and the slowest tpd(HL)n (n = 0… 2 for LVPECL, n = 3 for LVCMOS) across multiple devices C. Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL) and the low-to-high (tpd(LH)) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = | tpd(HL) − tpd(LH) |. Pulse skew is sometimes referred to as pulse width distortion or duty cycle skew. T0067-01 |YnYn| Yn Yn VOH VOL 80% 20% 0 V tr tf VOUT(pp) T0058-02 CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 Figure Waveforms for Calculation of t sk(o) and t sk(pp) Figure LVPECL Differential Output Voltage and Rise/Fall Time

www.ti.com LVCMOS 10 pF CDCM1804 1 kΩ 1 kΩ S0079-02 PCB DESIGN FOR THERMAL FUNCTIONALITY CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION (continued) Figure 10. LVCMOS Output Loading During Device Test It is recommended to take special care of the PCB design for good thermal flow from the QFN-24 terminal package to the PCB. Due to the three LVPECL outputs, the current consumption of the CDCM1804 is fixed. JEDEC JESD51-7 specifies thermal conductivity for standard PCB boards. Modeling the CDCM1804 with a standard 4-layer JEDEC board results in a 67.22 C maximum temperature with R θ JA of 106.62 C/W for C ambient temperature. When deploying four thermal vias (one per quadrant), the thermal flow improves significantly, yielding 46.94 C maximum temperature with R θ JA of 55.4 C/W for C ambient temperature. To ensure sufficient thermal flow, it is recommended to design with four thermal vias in once.

www.ti.com Package Thermal Pad (Underside) Top Side Island Thermal Via Dia 0.020 In. Heat Dissipation VSS Copper Plane VSS Copper Plane M0029-01 CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION (continued) Figure 11. Recommended Thermal Via Placement See the application reports Quad Flatpack No-Lead Logic Packages SCBA017 and QFN/SON PCB Attachment SLUA271 for further package-related information.

www.ti.com APPLICATION INFORMATION LVPECL RECEIVER INPUT TERMINATION IN 150 Ω 150 Ω CAC CAC 50 Ω 50 Ω IN CDCM1804 C VBB 50 Ω 50 Ω S0085-01 LVPECL LVPECL 130 Ω 83 Ω CDCM1804 50 Ω 50 Ω 130 Ω 83 Ω S0086-01 IN IN CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 The input of the CDCM1804 has a high impedance and comes with a large common-mode voltage range. For optimized noise performance, it is recommended to properly terminate the PCB trace (transmission line). If a differential signal drives the CDCM1804, then a 100- Ω termination resistor is recommended to be placed as close as possible across the input terminals. An even better approach is to install Ω with the center tap connected to a capacitor (C) to terminate odd-mode noise and make up for transmission-line mismatches. The VBB output can also be connected to the center tap to bias the input signal to DD 1.3 (see Figure Figure 12. Recommended AC-Coupling LVPECL Receiver Input Termination Figure 13. Recommended DC-Coupling LVPECL Receiver Input Termination The CDCM1804 can also be driven by single-ended signals. Typically, the input signal becomes connected to one input, while the complementary input must be properly biased to the center voltage of the incoming input signal. For LVCMOS signals, this would be V CC /2, realized by a simple voltage divider (e.g., two 10-k Ω resistors). The best option (especially if the dc offset of the input signal might vary) is to ac-couple the input signal and then rebias the signal using the VBB reference output. See Figure

www.ti.com INCLK CAC IN CDCM1804 CCT VBB Rdc NOTE: CAC − AC-coupling capacitor (e.g., 10 nF) CCT − Capacitor keeps voltage at IN constant (e.g., 10 nF) Rdc − Load and correct duty cycle (e.g., 50 Ω ) VBB − Bias voltage output S0087-01 DEVICE BEHAVIOR DURING RESET AND CONTROL-TERMINAL SWITCHING Output Behavior From Enabling the Device (EN CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 APPLICATION INFORMATION (continued) Figure 14. Typical Application Setting for Single-Ended Input Signals Driving the CDCM1804 In disable mode (EN 0), all output drivers are switched in high-Z mode. The S[2:0] control inputs are also switched off. In the same mode, all flip-flops are reset. The typical current consumption is below 500 µ When the device is enabled again, it takes typically µ s for the settling of the reference voltage and currents. During this time, the outputs Y[2:0] and Y[2:0] drive a high signal. is unknown (could be high or low). After the settle time, the outputs go into the low state. Due to the synchronization of each output driver signal with the input clock, the state of the waveforms after enabling the device is as shown in Figure The inverting input and output signal are not included. The Y:/1 waveform is the undivided output driver state.

www.ti.com High-Z EN IN Y:/1 Undefined Low High-ZY:/2 Undefined Low High-ZY:/4 Undefined Low 1 µs Signal State After the Device is Enabled (IN = Low) High-Z EN IN Y:/1 Undefined Low High-ZY:/2 Undefined Low High-ZY:/4 Undefined Low 1 µs Signal State After the Device is Enabled (IN = High) Undivided State is Valid After the First Positive Transition of the Input Clock T0068-01 Enabling a Single Output Stage CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 APPLICATION INFORMATION (continued) Figure 15. Waveforms If a single output stage becomes enabled: Y[2:0] is either low or high (undefined). Y[2:0] is the inverted signal of Y[2:0]. With the first positive clock transition, the undivided output becomes the input clock state. The divided output states are equal to the actual internal divider. The internal divider is not reset while enabling single-output drivers.

www.ti.com High-Z ENABLE Yx: IN Yx:/1 High-ZYx:/x Undefined EnabledDisabled Divider State Undivided State is Valid After the First Positive Transition of the Input Clock Undefined T0069-01 High-Z ENABLE Yx: IN Yx:/1 Undefined High-ZYx:/x Undefined Divider State EnabledDisabled Undivided State is Valid After the First Positive Transition of the Input Clock T0070-01 CDCM1804 SCAS697E JULY 2003 REVISED MAY 2005 APPLICATION INFORMATION (continued) Figure 16. Signal State After an Output Driver Becomes Enabled While IN Figure 17. Signal State After an Output Driver Becomes Enabled While IN

www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CDCM1804RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCM 1804 CDCM1804RGERG4 ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCM 1804 CDCM1804RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCM 1804 CDCM1804RGETG4 ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCM 1804 SN0305042RTHR ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCM 1804 SN0305042RTHT ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCM 1804 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 15-Apr-2017 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCM1804RGER VQFN RGE 24 3000 340.5 338.1 20.6 CDCM1804RGET VQFN RGE 24 250 340.5 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 Pack Materials-Page 2

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