CDCLVD1204RGTR

CDCLVD1204 TI | Alldatasheet

Document overview

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Technical content

(156.25 MHz)

156.25 MHz

_SEL Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CDCLVD1204 SCAS898B –MAY 2010–REVISED OCTOBER 2016 CDCLVD12042:4LowAdditiveJitterLVDSBuffer

1 Features

1• 2:4 Differential Buffer

• Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz
• Low Output Skew of 20 ps (Maximum)
• Universal Inputs Accept LVDS, LVPECL, and LVCMOS
• Selectable Clock Inputs Through Control Pin
• 4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible
• Clock Frequency: Up to 800 MHz
• Device Power Supply: 2.375 V to 2.625 V
• LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
• Industrial Temperature Range: –40°C to 85°C
• Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
• ESD Protection Exceeds 3 kV HBM, 1 kV CDM

2 Applications

• Telecommunications and Networking
• Medical Imaging
• Test and Measurement Equipment
• Wireless Communications
• General Purpose Clocking

3 Description

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS. The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CDCLVD1204 VQFN (16) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Example

SCAS898B –MAY 2010–REVISED OCTOBER 2016 www.ti.com Product Folder Links: CDCLVD1204 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Table of Contents

12.2 Receiving Notification of Documentation Updates 17

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2010) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Original (May 2010) to Revision A Page
• Changed Features bullet From: ESD Protection Exceeds 2 kV HBM, 500 V CDM To: ESD Protection Exceeds 3 kV

12 OUTN11GND

13OUTP2 8 VAC_REF

11 OUTP12IN_SEL

10 OUTN03INP1

9 OUTP04INN1

www.ti.com SCAS898B –MAY 2010–REVISED OCTOBER 2016 Product Folder Links: CDCLVD1204 Submit Documentation FeedbackCopyright © 2010–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

(1) G = Ground, I = Input, O = Output, P = Power Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME

1 GND G Device ground

2 IN_SEL I Input selection with an internal 200-kΩ pullup and pulldown; selects input port (see Table 1) 3, 4 INP1, INN1 I Differential redundant input pair or single-ended input 5 VCC P 2.5-V supply for the device 6, 7 INP0, INN0 I Differential input pair or single-ended input 8 VAC_REF O Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF to GND on this pin. 9, 10 OUTP0, OUTN0 O Differential LVDS output pair number 0 11,12 OUTP1, OUTN1 O Differential LVDS output pair number 1 13,14 OUTP2, OUTN2 O Differential LVDS output pair number 2 15,16 OUTP3, OUTN3 O Differential LVDS output pair number 3

SCAS898B –MAY 2010–REVISED OCTOBER 2016 www.ti.com Product Folder Links: CDCLVD1204 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The output can handle the permanent short.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VCC –0.3 2.8 V Input voltage, VI –0.2 VCC + 0.2 V Output voltage, VO –0.2 VCC + 0.2 V Driver short circuit current , IOSD See(2) Storage temperature, Tstg –65 150 °C (1) Human Body Model, 1.5 kΩ, 100 pF (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) >3000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) >1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Device supply voltage 2.375 2.5 2.625 V TA Ambient temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) CDCLVD1204 UNITRGT (VQFN)

16 PINS

RθJA Junction-to-ambient thermal resistance 51.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 85.4 °C/W RθJB Junction-to-board thermal resistance 20.1 °C/W ψJT Junction-to-top characterization parameter 1.3 °C/W ψJB Junction-to-board characterization parameter 19.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6 °C/W

www.ti.com SCAS898B –MAY 2010–REVISED OCTOBER 2016 Product Folder Links: CDCLVD1204 Submit Documentation FeedbackCopyright © 2010–2016, Texas Instruments Incorporated

6.5 Electrical Characteristics

VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IN_SEL CONTROL VdI3 3-state input Open 0.5 × VCC V VdIH Input high voltage 0.7 × VCC V VdIL Input low voltage 0.2 × VCC V IdIH Input high current VCC = 2.625 V, VIH = 2.625 V 30 µA IdIL Input low current VCC = 2.625 V, VIL = 0 V –30 µA Rpull(IN_SEL) Input pullup or pulldown resistor 200 kΩ 2.5-V LVCMOS INPUT (See Figure 5) fIN Input frequency 200 MHz Vth Input threshold voltage External threshold voltage applied to complementary input 1.1 1.5 V VIH Input high voltage Vth + 0.1 VCC V VIL Input low voltage 0 Vth – 0.1 V IIH Input high current VCC = 2.625 V, VIH = 2.625 V 10 µA IIL Input low current VCC = 2.625 V, VIL = 0 V –10 µA ΔV/ΔT Input edge rate 20% to 80% 1.5 V/ns CIN Input capacitance 2.5 pF DIFFERENTIAL INPUT fIN Input frequency Clock input 800 MHz VIN, DIFF Differential input voltage peak-to-peak VICM = 1.25 V 0.3 1.6 VPP VICM Input common mode voltage VIN, DIFF, PP > 0.4 V 1 VCC – 0.3 V IIH Input high current VCC = 2.625 V, VIH = 2.625 V 10 µA IIL Input low current VCC = 2.625 V, VIL = 0 V –10 µA ΔV/ΔT Input edge rate 20% to 80% 0.75 V/ns CIN Input capacitance 2.5 pF LVDS OUTPUT |VOD| Differential output voltage magnitude VIN, DIFF, PP = 0.3 V,RL = 100 Ω 250 450 mV ΔVOD Change in differential output voltage magnitude VIN, DIFF, PP = 0.3 V,RL = 100 Ω –15 15 mV VOC(SS) Steady-state common mode output voltage VIN, DIFF, PP = 0.3 V,RL = 100 Ω 1.1 1.375 V ΔVOC(SS) Steady-state common mode output voltage VIN, DIFF, PP = 0.6 V,RL = 100 Ω –15 15 mV Vring Output overshoot and undershoot Percentage of output amplitude VOD 10% VOS Output AC common mode VIN, DIFF, PP = 0.6 V, RL = 100 Ω 25 70 mVPP IOS Short-circuit output current VOD = 0 V ±24 mA tPD Propagation delay VIN, DIFF, PP = 0.3 V 1.5 2.5 ns tSK, PP Part-to-part skew 600 ps tSK, O Output skew 20 ps tSK,P Pulse skew 50% duty cycle input, crossing- point-to-crossing-point distortion –50 50 ps tRJIT Random additive jitter 50% duty cycle input, edge speed = 0.75 V/ns, 10 kHz to 20 MHz 0.3 ps, RMS tR/tF Output rise and fall time 20% to 80%,100 Ω, 5 pF 50 300 ps ICCSTAT Static supply current Outputs unterminated, f = 0 Hz 17 28 mA

SCAS898B –MAY 2010–REVISED OCTOBER 2016 www.ti.com Product Folder Links: CDCLVD1204 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Electrical Characteristics (continued) VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC100 Supply current All outputs, RL = 100 Ω, f = 100 MHz 40 58 mA ICC800 Supply current All outputs, RL = 100 Ω, f = 800 MHz 60 80 mA VAC_REF Reference output voltage VCC = 2.5 V, Iload = 100 µA 1.1 1.25 1.35 V

6.6 Timing Requirements

ADDITIVE PHASE NOISE FOR 100-MHZ CLOCK phn100 Phase noise at 100 Hz offset –132.9 dBc/Hz phn1k Phase noise at 1 kHz offset –138.8 dBc/Hz phn10k Phase noise at 10 kHz offset –147.4 dBc/Hz phn100k Phase noise at 100 kHz offset –153.6 dBc/Hz phn1M Phase noise at 1 MHz offset –155.2 dBc/Hz phn10M Phase noise at 10 MHz offset –156.2 dBc/Hz phn20M Phase noise at 20 MHz offset –156.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 171 fs, RMS ADDITIVE PHASE NOISE FOR 737.27-MHZ CLOCK phn100 Phase noise at 100 Hz offset –80.2 dBc/Hz phn1k Phase noise at 1 kHz offset –114.3 dBc/Hz phn10k Phase noise at 10 kHz offset –138 dBc/Hz phn100k Phase noise at 100 kHz offset –143.9 dBc/Hz phn1M Phase noise at 1 MHz offset –145.2 dBc/Hz phn10M Phase noise at 10 MHz offset –146.5 dBc/Hz phn20M Phase noise at 20 MHz offset –146.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 65 fs, RMS

6.7 Typical Characteristics

Figure 1. 100-MHz Input and Output Phase Noise Plot Figure 2. Differential Output Voltage vs Frequency

7 Parameter Measurement Information

Figure 3. LVDS Output DC Configuration During Device Test Figure 4. LVDS Output AC Configuration During Device Test Figure 5. DC Coupled LVCMOS Input During Device Test Figure 6. Output Voltage and Rise/Fall Time

IN_MUX LVDS INN0 INP0 INN1 INP1 VAC_REF IN_SEL VCC GND OUTN [0..3] OUTP [0..3] VCC 200 k: 200 k: Copyright © 2016, Texas Instruments Incorporated CDCLVD1204 SCAS898B –MAY 2010–REVISED OCTOBER 2016 www.ti.com Product Folder Links: CDCLVD1204 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The CDCLVD1204 LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing and termination are required to ensure correct operation of the device and to maximize signal integrity. The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage different than the output common mode voltage of the CDCLVD1204, AC-coupling must be used. If the LVDS receiver has internal 100-Ω termination, external termination must be omitted.

8.2 Functional Block Diagram

8.3 Feature Description

The CDCLVD1204 is a low additive jitter LVDS fan-out buffer that can generate four copies of two selectable LVPECL, LVDS, or LVCMOS inputs. The CDCLVD1204 can accept reference clock frequencies up to 800 MHz while providing low output skew.

8.4 Device Functional Modes

The two inputs of the CDCLVD1204 are internally muxed together and can be selected through the control pin (see Table 1). Unused inputs and outputs can be left floating to reduce overall component cost. Both AC- and DC-coupling schemes can be used with the CDCLVD1204 to provide greater system flexibility.

(1) The input buffers are disabled and the outputs are static. Table 1. Input Selection Table

0 INP0, INN0

1 INP1, INN1

8.4.1 LVDS Output Termination

Unused outputs can be left open without connecting any trace to the output pins. and Figure 11 (respectively). Figure 10. Output DC Termination Figure 11. Output AC Termination (With the Receiver Internally Biased)

8.4.2 Input Termination

The CDCLVD1204 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers. Figure 12. LVDS Clock Driver Connected to CDCLVD1204 Input (AC-Coupled)

156.25 MHz LVDS

156.25 MHz LVCMOS

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

package, low output skew, and low additive jitter make for a flexible device in demanding applications.

9.2 Typical Application

Figure 16. Fan-Out Buffer for Line Card Application

9.2.1 Design Requirements

• The PHY device is capable of DC-coupling with an LVDS driver such as the CDCLVD1204. This PHY device features internal termination so no additional components are required for proper operation.
• The ASIC LVDS receiver features internal termination and operates at the same common mode voltage as the CDCLVD1204. Again, no additional components are required.
• The FPGA requires external AC-coupling, but has internal termination. 0.1-µF capacitors are placed to provide AC-coupling. Similarly, the CPU is internally terminated, and requires only external AC-coupling capacitors.

9.2.2 Detailed Design Procedure

See Input Termination for proper input terminations, dependent on single ended or differential inputs. See LVDS Output Termination for output termination schemes depending on the receiver application. Unused outputs can be left floating. bypassing is critical for low-noise applications. Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043).

9.2.3 Application Curves

with 67 fs RMS jitter drives the CDCLVD12xx, resulting in 80 fs RMS when integrated from 12 kHz to 20 MHz. The resultant additive jitter is a low 44 fs RMS for this configuration. Figure 17. CDCLVD12xx Reference Phase Noise, 67 fs rms Figure 18. CDCLVD12xx Output Phase Noise, 80 fs rms

10 Power Supply Recommendations

jitter/phase noise is critical to applications. to add as many high-frequency (for example, 0.1 µF) bypass capacitors as there are supply pins in the package. to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper operation. Figure 19 shows this recommended power-supply decoupling method. Figure 19. Power-Supply Decoupling

11 Layout

11.1 Layout Guidelines

For reliability and performance reasons, the die temperature must be limited to a maximum of 125°C.

11.2 Layout Example

Figure 20. Recommended PCB Layout

11.3 Thermal Considerations

The CDCLVD1204 supports high temperatures on the printed circuit board (PCB) measured at the thermal pad. Thermal Calculation Tools for Analog Components (SLUA566).

www.ti.com SCAS898B –MAY 2010–REVISED OCTOBER 2016 Product Folder Links: CDCLVD1204 Submit Documentation FeedbackCopyright © 2010–2016, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043)
• Power Consumption of LVPECL and LVDS (SLYT127)
• Semiconductor and IC Package Thermal Metrics (SPRA953)
• Using Thermal Calculation Tools for Analog Components (SLUA566)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDCLVD1204RGTR Active Production VQFN (RGT) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 D1204 CDCLVD1204RGTR.A Active Production VQFN (RGT) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 D1204 CDCLVD1204RGTT Active Production VQFN (RGT) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 D1204 CDCLVD1204RGTT.A Active Production VQFN (RGT) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 D1204 CDCLVD1204RGTTG4.A Active Production VQFN (RGT) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 D1204 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVD1204RGTR VQFN RGT 16 3000 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) CDCLVD1204RGTR RGT VQFN 16 3000 35 X 14 150 315 135.9 7620 8.8 7.9 8.15 CDCLVD1204RGTT RGT VQFN 16 250 35 X 14 150 315 135.9 7620 8.8 7.9 8.15 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 16X 0.30 0.18 1.68 0.07 16X 0.5 0.3 1.0 0.8 (DIM A) TYP 0.05 0.00 12X 0.5 1.5 A 3.1 2.9 B 3.1 2.9 VQFN - 1 mm max heightRGT0016C PLASTIC QUAD FLATPACK - NO LEAD 4222419/D 04/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA 0.08 SEATING PLANE 5 8 16 13 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

16X (0.24) 16X (0.6) ( 0.2) TYP VIA 12X (0.5) (2.8) (2.8) (0.58) TYP ( 1.68) (R0.05) ALL PAD CORNERS (0.58) TYP VQFN - 1 mm max heightRGT0016C PLASTIC QUAD FLATPACK - NO LEAD 4222419/D 04/2022 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.24) 12X (0.5) (2.8) (2.8) ( 1.55) (R0.05) TYP VQFN - 1 mm max heightRGT0016C PLASTIC QUAD FLATPACK - NO LEAD 4222419/D 04/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM ALL AROUND METAL SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM 5 8 1316

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