CDCLVD110_12 TI1 | Alldatasheet
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SCAS684,C]
- PDF pages: 13
Technical content
FEATURES
DESCRIPTION
www.ti.com Not Recommended for New Designs PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER Low-Output Skew <30 ps (Typical) for Clock-Distribution
Applications
V CC range 2.5 V Typical Signaling Rate Capability of Up to 1.1 GHz Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs Full Rail-to-Rail Common-Mode Input Range Receiver Input Threshold 100 mV Available in 32-Pin LQFP Package Fail-Safe I/O-Pins for V DD V (Power Down) The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50- Ω transmission lines. When the control enable is high (EN 1), the differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN the outputs are not programmable and all outputs are enabled. The CDCLVD110 is characterized for operation from C to Not Recommended for New Designs. Use CDCLVD110A as a Replacement. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2002 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
www.ti.com FUNCTIONAL BLOCK DIAGRAM CDCLVD110 SCAS684C SEPTEMBER 2002 REVISED JANUARY 2008 Submit Documentation Feedback Copyright 2002 2008, Texas Instruments Incorporated Product Folder Link(s) CDCLVD110
www.ti.com ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS CDCLVD110 SCAS684C SEPTEMBER 2002 REVISED JANUARY 2008 TERMINAL FUNCTIONS TERMINAL I/O NO. CK I Control register input clock, a 120-k Ω pullup resistor SI I Control register serial input/CLK Select, a 120-k Ω pulldown resistor CLK0 I True differential input, LVDS CLK0 I Complementary differential input, LVDS V BB O Reference voltage output CLK1 I True differential input, LVDS CLK1 I Complementary differential input, LVDS EN I Control enable (for programmability), a 120-k Ω pulldown resistor, input V SS Device ground V DD 16, Supply voltage 11, 13, 15, 18, 20, 22, Q [9:0] O Clock outputs, these outputs provide low-skew copies of CLKIN 24, 27, 29, 10, 12, 14, 17, 19, Q[9:0] O Complementary clock outputs, these outputs provide low-skew copies of CLKIN 21,23, 26, 28, VALUE UNIT V DD Supply voltage 0.3 to 2.8 V V I Input voltage 0.2 to DD 0.2) V V O VI Output voltage 0.2 to DD 0.2) V Qn, Qn I OSD Driver short circuit current Continuous Electrostatic discharge (HBM 1.5 k Ω 100 pF), ESD >2000 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. MIN NOM MAX UNIT V DD Supply voltage 2.375 2.5 2.625 V V IC Receiver common-mode input voltage 0.5|V ID V DD 0.5|V ID V T A Operating free-air temperature C over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER OD Differential output voltage R L 100 Ω 250 450 600 mV Δ V OD V OD magnitude change mV V OS Offset voltage C to C 0.95 1.2 1.45 V Δ V OS V OS magnitude change 350 mV V O V I OS Output short circuit current mA OD V V BB Reference output voltage V DD 2.5 I BB 100 µ A 1.15 1.25 1.35 V C O Output capacitance V O V DD or GND pF Copyright 2002 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCLVD110
www.ti.com JITTER CHARACTERISTICS LVDS SWITCHING CHARACTERISTICS CONTROL REGISTER CHARACTERISTICS CDCLVD110 SCAS684C SEPTEMBER 2002 REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RECEIVER V IDH Input threshold high 100 mV V IDL Input threshold low 100 mV ID Input differential voltage 200 mV I IH V I V DD Input current, CLK0/ CLK0 CLK1/ CLK1 µ A I IL V I V C I Input capacitance V I V DD or GND pF SUPPLY CURRENT Full loaded All outputs enabled and loaded, R L 100 Ω f Hz 130 I DD Supply current No load Outputs enabled, no output load, f Hz mA I DDZ 3-State All outputs 3-state by control logic, f Hz characterized with CDCLVD110 performance EVM, V DD 3.3 OUTPUTS NOT UNDER TEST are terminated to Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT kHz to MHz, f out 30.72 MHz 650 Additive phase jitter from input to t jitterLVDS fs rms LVDS output and kHz to MHz, f out 125 MHz 299 over recommended operating free-air temperature range, V DD 2.5 V FROM TO PARAMETER MIN TYP MAX UNIT (INPUT) (OUTPUT) CLK0, CLK0 t PLH Propagation delay low-to-high Qn, Qn ns CLK1, CLK1 Propagation delay high-to-low CLK0, CLK0 t PHL Qn, Qn ns CLK1, CLK1 CLK0, CLK0 t duty Duty cycle Qn, Qn 45% 55% CLK1, CLK1 t sk(o) Output skew Any Qn, Qn ps t sk(p) Pulse skew Any Qn, Qn ps t sk(pp) Part-to-part skew Any Qn, Qn 600 ps t r Output rise time, 20% to 80%, R L 100 Ω C L pF Any Qn, Qn 350 ps t f Output fall time, 20% to 80%, R L 100 Ω C L pF Any Qn, Qn 350 ps CLK0, CLK0 f clk Max input frequency Any Qn, Qn 900 1100 MHz CLK1, CLK1 over recommended operating free-air temperature range, V DD 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f MAX Maximum frequency of shift register 100 150 MHz t su Setup time, clock to SI ns t h Hold time, clock to SI 1.5 ns t removal Removal time, enable to clock 1.5 ns t w Clock pulse width, minimum ns V IH Logic input high V DD 2.5 V V V IL Logic input low V DD 2.5 V 0.8 V Submit Documentation Feedback Copyright 2002 2008, Texas Instruments Incorporated Product Folder Link(s) CDCLVD110
www.ti.com SPECIFICATION OF CONTROL REGISTER CDCLVD110 SCAS684C SEPTEMBER 2002 REVISED JANUARY 2008 CONTROL REGISTER CHARACTERISTICS (continued) over recommended operating free-air temperature range, V DD 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input current, CK pin I IH V I V DD µ A Input current, SI and EN pins Input current, CK pin I IL V I GND µ A Input current, SI and EN pins The CDCLVD110 is provided with an 11-bit, serial-in shift register and an 11-bit control register. The control Register enables/disables each output clock and selects either CLK0 or CLK1 as the input clock. The CDCLVD110 has two modes of operation: Programmable Mode (EN=1) The shift register utilizes a serial input (SI) and a clock input (CK). Once the shift register is loaded with clock pulses, the twelfth clock pulse loads the control register. The first bit (bit on SI enables the Q9, output pair, and the tenth bit (bit enables the Q0, pair. The eleventh bit (bit 10) on SI selects either CLK0 or CLK1 as the input clock; a bit value of selects CLK0, whereas a bit value of selects CLK1. To restart the control register configuration, a reset of the state machine must be done with a clock pulse on CK (shift register clock input) and EN set to low. The control register can be configured only once after each reset. Standard Mode (EN=0) In this mode, the CDCLVD110 is not programmable and all the clock outputs are enabled. The clock input (CLK0 or CLK1) is selected with the SI pin, as is shown in the table entitled control register. STATE-MACHINE INPUTS EN SI CK OUTPUT L L X All outputs enabled, CLK0 selected, control register disabled, default state L H X All outputs enabled, CLK1 selected, control register disabled H L First stage stores other stage stores data of previous stage H H First stage stores other stage stores data of previous stage L X Reset of state machine, shift and control registers CONTROL REGISTER BIT BITS [0-9] Q N [0-9] L H CLK0 H H CLK1 X L Outputs disabled SERIAL INPUT (SI) SEQUENCE BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT CLK_SEL TRUTH TABLE FOR CONTROL LOGIC CK EN SI CLK0 CLK0 CLK1 CLK1 Q(0-9) Q(0-9) L L L L H X X L H L L L H L X X H L L L L Open Open X X L H L L H X X L H L H L L H X X H L H L L L H X X Open Open L H All outputs enabled X Don't care Copyright 2002 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCLVD110
www.ti.com APPLICATION INFORMATION Fall-Safe Information LVDS Receiver Input Termination Control Inputs Termination CDCLVD110 SCAS684C SEPTEMBER 2002 REVISED JANUARY 2008 For V DD V (power-down mode) the CDCLVD110 has fail-safe input and output pins. In power-on mode, fail-safe biasing at input pins can be accomplished with a 10-k Ω pullup resistor from CLK0/CLK1 to VDD and a 10-k Ω pulldown resistor from CLK0 CLK1 to GND. The LVDS receiver inputs need to have 100- Ω termination resistors placed as close as possible across the input pins. No external termination is required. The CK control input has an internal 120-k. pullup resistor while SI- and EN-control inputs each have an internal 120-k Ω pulldown resistor. If the control pins are left open per the default, all outputs are enabled, CLK0, CLK0 is selected, and the control register is disabled. Submit Documentation Feedback Copyright 2002 2008, Texas Instruments Incorporated Product Folder Link(s) CDCLVD110
www.ti.com PARAMETER MEASUREMENT INFORMATION CDCLVD110 SCAS684C SEPTEMBER 2002 REVISED JANUARY 2008 Output skew, t sk(o) is calculated as the greater of: The difference between the fastest and the slowest t PLHn 2,...10) The difference between the fastest and the slowest t PHLn 2,...10) Part-to-part skew, t sk(pp) is calculated as the greater of: The difference between the fastest and the slowest t PLHn 2,...10) across multiple devices The difference between the fastest and the slowest t PHLn 2,...10) across multiple devices Pulse skew, t sk(p) is calculated as the magnitude of the absolute time difference between the high-to-low PHL and the low-to-high PLH propagation delays when a single switching input causes one or more outputs to switch, t sk(p) t PHL t PLH Pulse skew is sometimes referred to as pulse width distortion or duty cycle skew. Figure Waveforms for Calculation of t sk(o) and t sk(pp) Copyright 2002 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCLVD110
www.ti.com CDCLVD110 SCAS684C SEPTEMBER 2002 REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION (continued) Figure Test Criteria for f clk Duty Cycle, t r t f V OD Submit Documentation Feedback Copyright 2002 2008, Texas Instruments Incorporated Product Folder Link(s) CDCLVD110
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCLVD110VF NRND LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCLVD110VFG4 NRND LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCLVD110VFR NRND LQFP VF 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCLVD110VFRG4 NRND LQFP VF 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2009 Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Mar-2012 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVD110VFR LQFP VF 32 1000 341.0 159.0 123.5 PACKAGE MATERIALS INFORMATION www.ti.com 3-Mar-2012 Pack Materials-Page 2
MTQF002B – JANUARY 1995 – REVISED MAY 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VF (S-PQFP-G32) PLASTIC QUAD FLATPACK 4040172/D 04/00 Gage Plane Seating Plane 1,60 MAX 1,45 1,35 8,80 9,20 SQ 0,05 MIN 0,45 0,75 0,25 0,13 NOM 5,60 TYP 7,20 6,80 SQ 0,25 0,45 0,10 0°–7° M0,200,80 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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