CDCLVC1102 TI | Alldatasheet
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Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CDCLVC1102,CDCLVC1103,CDCLVC1104 CDCLVC1106,CDCLVC1108,CDCLVC1110,CDCLVC1112 SCAS895B – MAY 2010– REVISED FEBRUARY 2017 CDCLVC11xx3.3-Vand2.5-VLVCMOSHigh-PerformanceClockBufferFamily
1 Features
1• High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10, 1:12 LVCMOS Clock Buffer Family
- Very Low Pin-to-Pin Skew < 50 ps
- Very Low Additive Jitter < 100 fs
- Supply Voltage: 3.3 V or 2.5 V
- fmax = 250 MHz for 3.3 V fmax = 180 MHz for 2.5 V
- Operating Temperature Range: –40°C to 85°C
- Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP Package (All Pin-Compatible)
2 Applications
General-Purpose Communication, Industrial, and Consumer Applications
3 Description
The CDCLVC11xx is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. It is intended to round up TI's series of LVCMOS clock generators. Seven different fan-out variations, 1:2 to 1:12, are available. All of the devices are pin-compatible to each other for easy handling. All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range. The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low. The CDCLVC11xx family operates in a 2.5-V and 3.3-V environment and are characterized for operation from –40°C to 85°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CDCLVC1102 TSSOP (8) 3.00 mm × 4.40 mmCDCLVC1103 CDCLVC1104 CDCLVC1106 TSSOP (14) 5.00 mm × 4.40 mm CDCLVC1108 TSSOP (16) CDCLVC1110 TSSOP (20) 6.50 mm × 4.40 mm CDCLVC1112 TSSOP (24) 7.80 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram
CDCLVC1102,CDCLVC1103,CDCLVC1104 CDCLVC1106,CDCLVC1108,CDCLVC1110,CDCLVC1112 SCAS895B –MAY 2010– REVISED FEBRUARY 2017 www.ti.com Product Folder Links: CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC1110 CDCLVC1112 Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Table of Contents
12.2 Receiving Notification of Documentation Updates 15
13 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision A (October 2014) to Revision B Page Changes from Original (May 2010) to Revision A Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
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CDCLVC1102,CDCLVC1103,CDCLVC1104 CDCLVC1106,CDCLVC1108,CDCLVC1110,CDCLVC1112 www.ti.com SCAS895B – MAY 2010– REVISED FEBRUARY 2017 Product Folder Links: CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC1110 CDCLVC1112 Submit Documentation FeedbackCopyright © 2010–2017, Texas Instruments Incorporated
5 Pin Configuration and Functions
8-, 14-, 16-, 20, 24-Pin TSSOP Top View Pin Functions PIN TYPE DESCRIPTION NAME CDCLVC 1102 CDCLVC 1103 CDCLVC 1104 CDCLVC 1106 CDCLVC 1108 CDCLVC 1110 CDCLVC 1112 LVCMOS CLOCK INPUT CLKIN 1 1 1 1 1 1 1 Input Input Pin CLOCK OUTPUT ENABLE 1G 2 2 2 2 2 2 2 Input Output Enable LVCMOS CLOCK OUTPUT Y0 3 3 3 3 3 3 3 Output LVCMOS output. Unused outputs can be left floating. Y1 8 8 8 14 16 20 24 Y2 — 5 5 11 13 17 21 Y3 — — 7 13 15 19 23 Y4 — — — 6 6 6 6 Y5 — — — 9 11 15 19 Y6 — — — — 8 8 8 Y7 — — — — 9 13 17 SUPPLY VOLTAGE VDD 6 6 6 5 5 Power 2.5-V or device supply 9 13 8 10 14 18 12 14 18 22 GROUND
CDCLVC1102,CDCLVC1103,CDCLVC1104 CDCLVC1106,CDCLVC1108,CDCLVC1110,CDCLVC1112 SCAS895B –MAY 2010– REVISED FEBRUARY 2017 www.ti.com Product Folder Links: CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC1110 CDCLVC1112 Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE DESCRIPTION NAME CDCLVC 1102 CDCLVC 1103 CDCLVC 1104 CDCLVC 1106 CDCLVC 1108 CDCLVC 1110 CDCLVC 1112 GND 4 4 4 4 4 GND Device ground 7 11 7 7 11 15 10 12 16 20
CDCLVC1102,CDCLVC1103,CDCLVC1104 CDCLVC1106,CDCLVC1108,CDCLVC1110,CDCLVC1112 www.ti.com SCAS895B – MAY 2010– REVISED FEBRUARY 2017 Product Folder Links: CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC1110 CDCLVC1112 Submit Documentation FeedbackCopyright © 2010–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) This value is limited to 4.6 V maximum.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD Supply voltage –0.5 4.6 V VIN Input voltage(2) –0.5 VDD + 0.5 V VO Output voltage(2) –0.5 VDD + 0.5 V IIN Input current –20 20 mA IO Continuous output current –50 50 mA TJ Maximum junction temperature 125 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 3.3-V supply 3.0 3.3 3.6 V 2.5-V supply 2.3 2.5 2.7 VIL Low-level input voltage VDD = 3.0 V to 3.6 V VDD/2 – 600 mV VDD = 2.3 V to 2.7 V VDD/2 – 400 VIH High-level input voltage VDD = 3.0 V to 3.6 V VDD/2 + 600 mV VDD = 2.3 V to 2.7 V VDD/2 + 400 Vth Input threshold voltage VDD = 2.3 V to 3.6 V VDD/2 mV tr / tf Input slew rate 1 4 V/ns tw Minimum pulse width at CLKIN VDD = 3.0 V to 3.6 V 1.8 ns VDD = 2.3 V to 2.7 V 2.75 fCLK LVCMOS clock Input Frequency VDD = 3.0 V to 3.6 V DC 250 MHz VDD = 2.3 V to 2.7 V DC 180 TA Operating free-air temperature –40 85 °C
CDCLVC1102,CDCLVC1103,CDCLVC1104 CDCLVC1106,CDCLVC1108,CDCLVC1110,CDCLVC1112 SCAS895B –MAY 2010– REVISED FEBRUARY 2017 www.ti.com Product Folder Links: CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC1110 CDCLVC1112 Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6.4 Thermal Information
THERMAL METRIC(1) CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC11010 CDCLVC1112 UNIT PW (TSSOP)
8 PINS 14 PINS 16 PINS 20 PINS 24 PINS
RθJA Junction-to-ambient thermal RθJC(top) Junction-to-case(top) thermal (1) All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 Ω to VDD/2 (see Figure 3). (2) For dynamic IDD over frequency see and Figure 1. (3) This is the formula for the power dissipation calculation (see and the Power Considerations section). Ptot = Pstat + Pdyn + PCload [W] Pstat = VDD × IDD [W] Pdyn = CPD × VDD2 × ƒ [W] PCload = Cload × VDD2 × ƒ × n [W] n = Number of switching output pins
6.5 Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT OVERALL PARAMETERS FOR ALL VERSIONS IDD Static device current(2) 1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V 6 10 mA 1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 2.7 V 3 6 IPD Power-down current 1G = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V or 2.7 V 60 µA CPD Power dissipation capacitance per output(3) VDD = 3.3 V; f = 10 MHz 6 pF VDD = 2.5 V; f = 10 MHz 4.5 II Input leakage current at 1G VI = 0 V or VDD, VDD = 3.6 V or 2.7 V 8 8 µA Input leakage current at CLKIN 25 25 ROUT Output impedance VDD = 3.3 V 45 Ω VDD = 2.5 V 60 fOUT Output frequency VDD = 3 V to 3.6 V DC 250 MHz VDD = 2.3 V to 2.7 V DC 180 OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V VOH High-level output voltage VDD = 3 V, IOH = –0.1 mA 2.9 VVDD = 3 V, IOH = –8 mA 2.5 VDD = 3 V, IOH = –12 mA 2.2 VOL Low-level output voltage VDD = 3 V, IOL = 0.1 mA 0.1 VVDD = 3 V, IOL = 8 mA 0.5 VDD = 3 V, IOL = 12 mA 0.8 OUTPUT PARAMETERS FOR VDD = 2.5 V ± 0.2 V VOH High-level output voltage VDD = 2.3 V, IOH = –0.1 mA 2.2 V VDD = 2.3 V, IOH = –8 mA 1.7 VOL Low-level output voltage VDD = 2.3 V, IOL = 0.1 mA 0.1 V VDD = 2.3 V, IOL = 8 mA 0.5
width of output waveform and tperiod is 1/fOUT. (2) Parameter is specified by characterization. Not tested in production.
6.6 Switching Characteristics
6.7 Typical Characteristics
Figure 1. Device Power Consumption vs Clock Frequency Figure 2. Dynamic Supply Current vs Clock Frequency
7 Parameter Measurement Information
Figure 3. Test Load Circuit Figure 4. Application Load With 50-Ω Line Termination Figure 5. Application Load With Series Line Termination Figure 6. tDIS and tEN for Disable Low Figure 7. Output Skew tsk(o)
8 Detailed Description
8.1 Overview
VDD = 2.5 V. TI recommends placing the series resistor close to the driver to minimize signal reflection.
8.2 Functional Block Diagram
Table 1. Output Logic Table
8.3 Feature Description
The outputs of the CDCLVC11xx can be disabled by driving the asynchronous output enable pin (1G) low. connected to VDD and GND, respectively.
8.4 Device Functional Modes
The CDCLVC11xx operates from supplies between 2.5 V and 3.3 V.
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
simultaneously enable or disable buffered clock outputs as necessary in the application.
9.2 Typical Application
Figure 10. Example System Configuration
9.2.1 Design Requirements
The CDCLVC11xx shown in Figure 10 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator. The CPU is configured to control the output state through 1G.
- The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near the CDCLVC11xx to closely match the characteristic impedance of the trace to minimize reflections.
- The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the CDCLVC11xx.
- The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used. The PLL receiver features internal biasing, so AC coupling can be used when common-mode voltage is mismatched.
9.2.2 Detailed Design Procedure
9.2.3 Application Curves
Figure 11. CDCLVC11xx Reference Phase Noise 26 fs Figure 12. CDCLVC11xx Output Phase Noise 86 fs kHz to 20 MHz. The resultant additive jitter is a low 82-fs RMS for this configuration.
10 Power Supply Recommendations
the jitter and phase noise is critical to applications. required for proper operation.
Figure 13 shows this recommended power supply decoupling method. Figure 13. Power Supply Decoupling
10.1 Power Considerations
- Power used by the device as it switches states.
- Power required to charge any output load. The output load can be capacitive only or capacitive and resistive. The following formula and the power graphs in and Figure 1 can be used to obtain the power consumption of the device: Pdev = Pstat + n (Pdyn + PCload) Pstat = VDD × IDD Pdyn + PCload = see and Figure 1 where: VDD = Supply voltage ( or 2.5 V) IDD = Static device current (typical 6 mA for VDD = 3.3 V; typical 3 mA for VDD = 2.5 V) n = Number of switching output pins Example for device power consumption for CDCLVC1104: four outputs are switching, f = 120 MHz, VDD = 3.3 V, and Cload = 2 pF per output: Pdev = Pstat + n (Pdyn + PCload) = 19.8 mW + 40 mW = 59.8 mW Pstat = VDD × IDD = 6 mA × 3.3 V = 19.8 mW n (Pdyn + PCload) = 4 × 10 mW = 40 mW NOTE For dimensioning the power supply, the total power consumption must be considered. The total power consumption is the sum of the device power consumption and the power consumption of the load.
11 Layout
11.1 Layout Guidelines
of the capacitor using a low-impedance connection to the ground plane.
11.2 Layout Example
Figure 14. PCB Conceptual Layout
12 Device and Documentation Support
12.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 2. Related Links
12.2 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDCLVC1102PW Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C2 CDCLVC1102PW.B Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C2 CDCLVC1102PWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C2 CDCLVC1102PWR.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C2 CDCLVC1102PWRG4 Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C2 CDCLVC1102PWRG4.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C2 CDCLVC1103PW Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C3 CDCLVC1103PW.B Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C3 CDCLVC1103PWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C3 CDCLVC1103PWR.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C3 CDCLVC1103PWRG4 Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C3 CDCLVC1103PWRG4.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C3 CDCLVC1104PW Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C4 CDCLVC1104PW.B Active Production TSSOP (PW) | 8 150 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C4 CDCLVC1104PWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C4 CDCLVC1104PWR.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C4 CDCLVC1104PWRG4 Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C4 CDCLVC1104PWRG4.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C4 CDCLVC1106PW Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C6 CDCLVC1106PW.B Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C6 CDCLVC1106PWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C6 CDCLVC1106PWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C6 CDCLVC1106PWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C6 CDCLVC1106PWRG4.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C6 CDCLVC1108PW Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C8 CDCLVC1108PW.B Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C8 CDCLVC1108PWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C8 CDCLVC1108PWR.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C8 CDCLVC1108PWRG4 Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C8 Addendum-Page 1
www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDCLVC1108PWRG4.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9C8 CDCLVC1110PW Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CA CDCLVC1110PW.B Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CA CDCLVC1110PWR Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CA CDCLVC1110PWR.B Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CA CDCLVC1110PWRG4 Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CA CDCLVC1110PWRG4.B Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CA CDCLVC1112PW Active Production TSSOP (PW) | 24 60 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CC CDCLVC1112PW.B Active Production TSSOP (PW) | 24 60 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CC CDCLVC1112PWR Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CC CDCLVC1112PWR.B Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CC CDCLVC1112PWRG4 Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CC CDCLVC1112PWRG4.B Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 C9CC (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 2
www.ti.com 7-Oct-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVC1102PWR TSSOP PW 8 2000 353.0 353.0 32.0 CDCLVC1102PWRG4 TSSOP PW 8 2000 353.0 353.0 32.0 CDCLVC1103PWR TSSOP PW 8 2000 353.0 353.0 32.0 CDCLVC1103PWRG4 TSSOP PW 8 2000 353.0 353.0 32.0 CDCLVC1104PWR TSSOP PW 8 2000 353.0 353.0 32.0 CDCLVC1104PWRG4 TSSOP PW 8 2000 353.0 353.0 32.0 CDCLVC1106PWR TSSOP PW 14 2000 353.0 353.0 32.0 CDCLVC1106PWRG4 TSSOP PW 14 2000 353.0 353.0 32.0 CDCLVC1108PWR TSSOP PW 16 2000 353.0 353.0 32.0 CDCLVC1108PWRG4 TSSOP PW 16 2000 353.0 353.0 32.0 CDCLVC1110PWR TSSOP PW 20 2000 353.0 353.0 32.0 CDCLVC1110PWRG4 TSSOP PW 20 2000 353.0 353.0 32.0 CDCLVC1112PWR TSSOP PW 24 2000 353.0 353.0 32.0 CDCLVC1112PWRG4 TSSOP PW 24 2000 353.0 353.0 32.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CDCLVC1102PW PW TSSOP 8 150 530 10.2 3600 3.5 CDCLVC1102PW.B PW TSSOP 8 150 530 10.2 3600 3.5 CDCLVC1103PW PW TSSOP 8 150 530 10.2 3600 3.5 CDCLVC1103PW.B PW TSSOP 8 150 530 10.2 3600 3.5 CDCLVC1104PW PW TSSOP 8 150 530 10.2 3600 3.5 CDCLVC1104PW.B PW TSSOP 8 150 530 10.2 3600 3.5 CDCLVC1106PW PW TSSOP 14 90 530 10.2 3600 3.5 CDCLVC1106PW.B PW TSSOP 14 90 530 10.2 3600 3.5 CDCLVC1108PW PW TSSOP 16 90 530 10.2 3600 3.5 CDCLVC1108PW.B PW TSSOP 16 90 530 10.2 3600 3.5 CDCLVC1110PW PW TSSOP 20 70 530 10.2 3600 3.5 CDCLVC1110PW.B PW TSSOP 20 70 530 10.2 3600 3.5 CDCLVC1112PW PW TSSOP 24 60 530 10.2 3600 3.5 CDCLVC1112PW.B PW TSSOP 24 60 530 10.2 3600 3.5 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 18X 0.65 5.85 20X 0.30 0.19 TYP6.6 6.2
1.2 MAX
0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 6.6 6.4 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 10 11 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 10 11
www.ti.com PACKAGE OUTLINE C 22X 0.65 7.15 24X 0.30 0.19 TYP6.6 6.2 0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 7.9 7.7 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.000
www.ti.com EXAMPLE BOARD LAYOUT 24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 12 13 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 12 13
www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6
6.2 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9
www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6 0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8
www.ti.com PACKAGE OUTLINE C TYP6.6 6.2 6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT (5.8) 8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X
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