CDCLVC11XX_12 TI1 | Alldatasheet
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www.ti.com SCAS895 –MAY 2010 3.3V and2.5V LVCMOSHigh-PerformanceClockBufferFamily Check forSamples: CDCLVC11xx 1FEATURES • OperatingTemperature Range: –40°C to85°C
- High-Performance1:2,1:3,1:4,1:6,1:8,1:10, • Availablein8-,14-,16-,20-,24-PinTSSOP 1:12LVCMOS Clock BufferFamily Package (allpincompatible)
- Very Low Pin-to-PinSkew < 50 ps APPLICATIONS• Very Low AdditiveJitter< 100 fs
- GeneralPurpose Communication, Industrial• Supply Voltage:3.3V or 2.5V and Consumer Applications
- fmax = 250 MHz for3.3V fmax = 180 MHz for2.5V
DESCRIPTION
The CDCLVC11xx isa modular,high-performance,low-skew,generalpurpose clockbufferfamilyfrom Texas Instruments. The whole familyisdesignedwitha modularapproachinmind.Itisintendedtoroundup TI's seriesofLVCMOS clockgenerators. There are7 differentfan-outvariations,1:2to1:12,available.Allofthedevicesarepincompatibletoeach other foreasy handling. Allfamilymembers share the same highperformingcharacteristicslikelow additivejitter,low skew, and wide operatingtemperaturerange. The CDCLVC11xx supportsan asynchronousoutputenablecontrol(1G) which switchestheoutputsintoa low statewhen 1G islow.Also,versionswithsynchronizedenablecontrolforglitchfreeswitchingand three-state outputsareplannedinfuturedeviceoptions. The CDCLVC11xx operateina 2.5V and 3.3V environmentand arecharacterizedforoperationfrom–40°C to 85°C. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
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SCAS895 –MAY 2010 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. PACKAGE OPTIONS PIN FUNCTIONS LVCMOS CLOCK OUTPUT SUPPLYLVCMOS CLOCK OUTPUT GROUNDCLOCK INPUT ENABLE VOLTAGEDEVICES CLKIN 1G Y0,Y1,… Y11 VDD GND CDCLVC1102 1 2 3,8 6 4 CDCLVC1103 1 2 3,8,5 6 4 CDCLVC1104 1 2 3,8,5,7 6 4 CDCLVC1106 1 2 3,14,11,13,6,9 5,8,12 4,7,10 CDCLVC1108 1 2 3,16,13,15,6,11,8,9 5,10,14 4,7,12 CDCLVC1110 1 2 3,20,17,19,6,15,8,13,10 5,9,14,18 4,7,11,16 OUTPUT LOGIC TABLE INPUTS OUTPUTS CLKIN 1G Yn X L L L H L H H H
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www.ti.com SCAS895 –MAY 2010 ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE /UNIT VDD Supplyvoltagerange –0.5V to4.6V VIN Inputvoltagerange (2) –0.5V toVDD + 0.5V VO Outputvoltagerange (2) –0.5V toVDD + 0.5V IIN Inputcurrent ±20 mA IO Continuousoutputcurrent ±50 mA TJ Maximum junctiontemperature 125°C TST Storagetemperaturerange –65°C to150°C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Thisvalueislimitedto4.6V maximum. THERMAL INFORMATION DCDLVC1102/03/04 CDCLVC1106 CDCLVC1108 CDCLVC11010 CDCLVC1112 THERMAL METRIC (1) PW PW PW PW PW UNITS
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°C/W (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . (2) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,high-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (3) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specific JEDEC-standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT 3.3V supply 3.0 3.3 3.6 VDD Supplyvoltagerange V 2.5V supply 2.3 2.5 2.7 VDD = 3.0V to3.6V VDD /2– 600 VIL Low-levelinputvoltage mV VDD = 2.3V to2.7V VDD /2– 400 VDD = 3.0V to3.6V VDD /2+ 600 VIH High-levelinputvoltage mV VDD = 2.3V to2.7V VDD /2+ 400 Vth Inputthresholdvoltage VDD = 2.3V to3.6V VDD /2 mV tr /tf Inputslewrate 1 4 V/ns VDD = 3.0V to3.6V DC 250LVCMOS clockInputfCLK MHzFrequency VDD = 2.3V to2.7V DC 180 TA Operatingfree-airtemperature –40 85 °C Copyright© 2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):CDCLVC11xx
SCAS895 –MAY 2010 www.ti.com DEVICE CHARACTERISTICS overrecommended operatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER CONDITION MIN TYP (1) MAX UNIT OVERALL PARAMETERS FOR ALL VERSIONS 1G = VDD ;CLKIN = 0 V orVDD ;IO = 0 mA; VDD = 3.6V 6 10 mA IDD Staticdevicecurrent(2) 1G = VDD ;CLKIN = 0 V orVDD ;IO = 0 mA; VDD = 2.7V 3 6 mA IPD Power down current 1G = 0 V;CLKIN = 0 V orVDD ;IO = 0 mA; VDD = 3.6V or2.7V 60 µA VDD = 3.3V;f= 10 MHz 6 pFPower dissipationcapacitanceC PD peroutput(3) VDD = 2.5V;f= 10 MHz 4.5 pF Inputleakagecurrentat1G ± 8 II VI= 0 V orVDD ,VDD = 3.6V or2.7V µA InputleakagecurrentatCLKIN ± 25 VDD = 3.3V 45 Ω R OUT Outputimpedance VDD = 2.5V 60 Ω VDD = 3.0V to3.6V DC 250 MHz fOUT Outputfrequency VDD = 2.3V to2.7V DC 180 MHz OUTPUT PARAMETERS FOR VDD = 3.3V ± 0.3V VDD = 3 V,IOH = –0.1mA 2.9 VOH High-leveloutputvoltage VDD = 3 V,IOH = –8 mA 2.5 V VDD = 3 V,IOH = –12 mA 2.2 VDD = 3 V,IOL = 0.1mA 0.1 VOL Low-leveloutputvoltage VDD = 3 V,IOL = 8 mA 0.5 V VDD = 3 V,IOL = 12 mA 0.8 tPLH , Propagationdelay CLKIN toYn 0.8 2.0 nstPHL tsk(o) Outputskew Equalloadofeach output 50 ps tr/tf Riseand falltime 20% –80% (VOH -VOL ) 0.3 0.8 ns tDIS Outputdisabletime 1G toYn 6 ns tEN Outputenabletime 1G toYn 6 ns Pulseskew ;tsk(p) To be measured withinputdutycycleof50% 180 pstPLH(Yn) – tPHL(Yn) (4) tsk(pp) Part-to-partskew Under equaloperatingconditionsfortwo parts 0.5 ns tjitter Additivejitterrms 12kHz… 20 MHz, fOUT = 250 MHz 100 fs (1) AlltypicalvaluesareatrespectivenominalVDD .Forswitchingcharacteristics,outputsareterminatedto50 Ω toVDD /2(seeFigure1). (2) FordynamicIDD overfrequencysee Figure8 and Figure9. (3) Thisistheformulaforthepower dissipationcalculation(seeFigure8 and thePower Considerationsection). Ptot= Pstat+ Pdyn + PCload [W] Pstat= VDD × IDD [W] Pdyn = C PD × VDD 2 × ƒ [W] PCload = C load× VDD 2 × ƒ × n [W] n = Number ofswitchingoutputpins (4) tsk(p)depends on outputrise-and fall-time(tr/tf).The outputduty-cyclecan be calculated:odc = (tw(OUT) ± tsk(p))/tperiod;tw(OUT) is pulse-widthofoutputwaveform and tperiodis1/fOUT .
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www.ti.com SCAS895 –MAY 2010 DEVICE CHARACTERISTICS (continued) overrecommended operatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER CONDITION MIN TYP (1) MAX UNIT OUTPUT PARAMETERS FOR VDD = 2.5V ± 0.2V VDD = 2.3V,IOH = –0.1mA 2.2 VOH High-leveloutputvoltage V VDD = 2.3V,IOH = –8 mA 1.7 VDD = 2.3V,IOL = 0.1mA 0.1 VOL Low-leveloutputvoltage V VDD = 2.3V,IOL = 8 mA 0.5 tPLH , Propagationdelay CLKIN toYn 1.0 2.6 nstPHL tsk(o) Outputskew Equalloadofeach output 50 ps tr/tf Riseand falltime 20% –80% referencepoint 0.3 1.2 ns tDIS Outputdisabletime 1G toYn 10 ns tEN Outputenabletime 1G toYn 10 ns Pulseskew ;tsk(p) To be measured withinputdutycycleof50% 220 pstPLH(Yn) – tPHL(Yn) (5) tsk(pp) Part-to-partskew Under equaloperatingconditionsfortwo parts 1.2 ns tjitter Additivejitterrms 12kHz… 20 MHz, fOUT = 180 MHz 350 fs (5) tsk(p)depends on outputrise-and fall-time(tr/tf).The outputduty-cyclecan be calculated:odc = (tw(OUT) ± tsk(p))/tperiod;tw(OUT) is pulse-widthofoutputwaveform and tperiodis1/fOUT . Copyright© 2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):CDCLVC11xx
Z =□50O /c87 R=50 /c87 from□Measurement□Equipment V /2DD LVCMOS Output C = 2 pF parasitic□capasitance LVCMOS Output VDD R=100 /c87 R= 100 /c87 Z =□50O /c87 parasitic□input□capacitance LVCMOS Output Z =□50O /c87 RS□=□0 (V =□2.5□V) /c87 /c87 DD DD parasitic□input□capacitance tDIS tEN VIN / 2 1 G Yn VIN / 2 tsk(o) VDD / 2 Yn+1 VDD / 2 Yn tsk(o) CDCLVC11xx SCAS895 –MAY 2010 www.ti.com PARAMETERS MEASUREMENT INFORMATION Figure1. TestLoad Circuit Figure2. ApplicationLoad With 50 Ω LineTermination Figure3. ApplicationLoad With SeriesLineTermination Figure4.tDIS and tEN forDisableLow Figure5.Output Skew tsk(o)
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80 % V OH - VOL CLKIN t f 20 % V OH - VOL VOH V OL t PLH V DD / 2 Y n V DD / 2 CLKIN t PHL Note : t sk (p ) = | t PLH – t PHL | CDCLVC11xx www.ti.com SCAS895 –MAY 2010 PARAMETERS MEASUREMENT INFORMATION (continued) Figure6.Pulse Skew tsk(p)and PropagationDelay Figure7.Rise/FallTimes tr/tf tPLH /tPHL TYPICAL CHARACTERISTICS Power Consideration The followingpower considerationrefersto the device-consumedpower consumptiononly.The devicepower consumption is the sum of staticpower and dynamic power. The dynamic power usage consistsof two components: 1. Power used by thedeviceas itswitchesstates. 2. Power requiredtochargeany outputload. The outputloadcan be capacitiveonlyorcapacitiveand resistive.The followingformulaand thepower graphsin Figure8 and Figure9 can be used toobtainthepower consumptionofthedevice: Pdev = Pstat+ n (Pdyn + PCload) Pstat= VDD x IDD Pdyn + PCload = see Figure8 and Figure9 where: VDD = Supplyvoltage(3.3V or2.5V) IDD = Staticdevicecurrent(typ6 mA forVDD = 3.3V;typ3 mA forVDD = 2.5V) n = Number ofswitchingoutputpins Example forDevicePower Consumption forCDCLVC1104: 4 outputsare switching,f= 120 MHz, VDD = 3.3V and C load= 2 pF peroutput: Pdev = Pstat+ n (Pdyn + PCload)= 19.8mW + 40 mW = 59.8mW Pstat= VDD x IDD = 6 mA x 3.3V = 19.8mW n (Pdyn + PCload)= 4 x 10 mW = 40 mW NOTE For dimensioningthepower supply,thetotalpower consumptionneeds tobe considered. The totalpower consumptionisthesum ofthedevicepower consumptionand thepower consumptionoftheload. Copyright© 2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):CDCLVC11xx
0 20 40 60 80 100 120 140 160 180 V = 2.5 VDD P + Pdyn Cload8pF P + Pdyn Cload50/2 P + Pdyn Cload2pF f - Clock Frequency - MHz Device Power Consumption - mW 0 20 40 60 80 100 120 140 160 180 200 220 240 f - Clock Frequency - MHz V = 3.3 VDD P + Pdyn Cload8pF P + Pdyn Cload50/2 P + Pdyn Cload2pFDevice Power Consumption - mW 0 20 40 60 80 100 120 140 160 180 I = C * V * fdyn PD DD V = 2.5 VDD f - Clock Frequency - MHz I - Dynamic Supply Current - mAdyn 0 20 40 60 80 100 120 140 160 180 200 220 240 f - Clock Frequency - MHz I - Dynamic Supply Current - mAdyn I = C * V * fdyn PD DD V = 3.3 VDD CDCLVC11xx SCAS895 –MAY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure8.Device Power Consumption vs Clock Frequency Figure9.Device Power Consumption vs Clock Frequency (Load 50Ω intoVDD /2.2pF,8pF; Per Output) (Load 50Ω intoVDD /2.2pF,8pF; Per Output) Figure10.Dynamic Supply Currentvs Clock Frequency Figure11.Dynamic Supply Currentvs Clock Frequency (CPD = 6pF,No Load; Per Output) (CPD = 4.5pF,No Load; Per Output)
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www.ti.com 26-Jun-2010 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CDCLVC1102PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples CDCLVC1102PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples CDCLVC1103PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples CDCLVC1103PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples CDCLVC1104PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples CDCLVC1104PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples CDCLVC1106PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples CDCLVC1106PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples CDCLVC1108PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples CDCLVC1108PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples CDCLVC1110PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples CDCLVC1110PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples CDCLVC1112PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples CDCLVC1112PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
www.ti.com 26-Jun-2010 Addendum-Page 2 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVC1102PWR TSSOP PW 8 2000 367.0 367.0 35.0 CDCLVC1103PWR TSSOP PW 8 2000 367.0 367.0 35.0 CDCLVC1104PWR TSSOP PW 8 2000 367.0 367.0 35.0 CDCLVC1106PWR TSSOP PW 14 2000 367.0 367.0 35.0 CDCLVC1108PWR TSSOP PW 16 2000 367.0 367.0 35.0 CDCLVC1110PWR TSSOP PW 20 2000 367.0 367.0 38.0 CDCLVC1112PWR TSSOP PW 24 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2
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