CDCL6010RGZT

CDCL6010 TI | Alldatasheet

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LVDS□Input 30MHz 319MHz/c45 1□Bypass CML□Output 5□Differential CML□Outputs 15MHz 1.25GHz/c45 5□Differential CML□Outputs 15MHz 1.25GHz/c45 CDCL6010 SLLS780 FEBRUARY 2007 1.8V, Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements Single 1.8V Supply Integrated LC Oscillator Allows External High-Performance Clock Multiplier, Bandwidth Adjustment Distributor, Jitter Cleaner, and Buffer With Outputs PLL Lock Indication Low Output Jitter: 400fs RMS Power Consumption: 640mW Typical Output Group Phase Adjustment Output Enable Control for Each Output Low-Voltage Differential Signaling (LVDS) SDA/SCL Device Management Interface Input, 100 Ω Differential On-Chip Termination, 48-pin QFN (RGZ) Package 30MHz to 319MHz Frequency Range Industrial Temperature Range: C to +85 C Differential Current Mode Logic (CML) Outputs, Ω Single-Ended On-Chip Termination, 15MHz to 1.25GHz Frequency Low Jitter Clocking for High-Speed SERDES Range Jitter Cleaning of SERDES Reference Clocks One Dedicated Differential CML Output, for 1G/10G Ethernet, 1X/2X/4X/10X Fibre Straight PLL and Frequency Divider Bypass Channel, PCI Express, Serial ATA, SONET, CPRI, OBSAI, etc. Two Groups of Five Outputs Each with Up to 1-to-11 Clock Buffering and Fan-out Independent Frequency Division Ratios; Optional PLL Bypass Fully Integrated Voltage Controlled Oscillator (VCO); Supports Wide Output Frequency Range Output Frequency Derived From VCO Frequency with Divide Ratios of 10, 16, 20, 32, 40, and Meets OBSAI RP1 v1.0 Standard and CPRI v2.0 Requirements Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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DESCRIPTION

a high-performance, low phase The CDCL6010 supports one differential LVDS clock noise clock multiplier, distributor, jitter cleaner, and input and a total of differential CML outputs. One low skew buffer. It effectively cleans a noisy system output is a straight bypass with no support for jitter clock with a fully-integrated low noise Voltage cleaning or clock multiplication. The remaining Controlled Oscillator (VCO) that operates in the outputs are available in two groups of five outputs 1.2GHz 1.275GHz range. (Note that the LC each with independent frequency division ratios. oscillator oscillates in the 2.4GHz 2.55GHz range. Those outputs can be optionally setup to bypass The frequency is predivided by before the the PLL when no jitter cleaning is needed. The CML post-dividers and P1.) outputs are compatible with LVDS receivers if ac-coupled. The output frequency OUT is synchronized to the frequency of the input clock IN The programmable With careful observation of the input voltage swing pre-dividers, M and and the post-dividers, and and common-mode voltage limits, the CDCL6010 P1, give a high flexibility to the ratio of the output can support a single-ended clock input as outlined in frequency to the input frequency: the Pin F OUT F IN N/(M The CDCL6010 can operate as a multi-output clock buffer in a PLL bypass mode. Where: P (P0, P1) 10, 16, 20, 32, 40, All device settings are programmable through the SDA/SCL, serial two-wire interface. M N 32, The phase of one output group relative to the other can be adjusted through the SDA/SCL interface. For provided that: post-divide ratios (P0, P1) that are multiples of the 30MHz IN /M) 40MHz total number of phase adjustment steps n equals 1200MHz OUT 1275MHz the divide-ratio divided by For post-divide ratios (P0, P1) that are not multiples of the total number The PLL loop bandwidth is user-selectable by of steps n is the same as the post-divide ratio. The external filter components or by using the internal phase adjustment step Δ Φ in time units is given as: loop filter. The PLL loop bandwidth and damping Δ Φ 1/(n F OUT factor can be adjusted to meet different system requirements. where F OUT is the respective output frequency. The device operates in a 1.8V supply environment and is characterized for operation from C to +85 The CDCL6010 is available in a 48-pin QFN (RGZ) package. Submit Documentation Feedback

www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS CDCL6010 SLLS780 FEBRUARY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) T A PACKAGED DEVICES C to +85 C CDCL6010RGZT 48-pin QFN (RGZ) Package, small tape and reel C to +85 C CDCL6010RGZR 48-pin QFN (RGZ) Package, tape and reel (1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or refer to our web site at www.ti.com over operating free-air temperature range (unless otherwise noted). (1) VALUE UNIT V DD AV DD Supply voltage (2) 0.3 to 2.5 V V LVDS Voltage range at LVDS input pins (2) 0.3 to 4.0 V V I Voltage range at all non-LVDS input pins (2) 0.3 to 3.0 V ESD Electrostatic discharge (HBM) kV T J Junction temperature +125 C T STG Storage temperature range to +150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. Over operating free-air temperature range (unless otherwise noted). MIN NOM MAX UNIT V DD Digital supply voltage 1.7 1.8 1.9 V AV DD Analog supply voltage 1.7 1.8 1.9 V T A Ambient temperature (no airflow, no heatsink) +85 C T J Junction temperature +105 C θ JA Junction-to-ambient thermal resistance (1) airflow lfm 28.3 C/W airflow lfm 22.4 (1) No heatsink; power uniformly distributed; ground vias x array) tied to the thermal exposed pad; 4-layer high-K board. Submit Documentation Feedback

www.ti.com DC ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS CDCL6010 SLLS780 FEBRUARY 2007 Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I VDD Total current from digital 1.8V supply All outputs enabled; V DD V DD,typ 270 mA 30.72MHz input; 61.44MHz output I AVDD Total current from analog 1.8V supply All outputs enabled; AV DD V DD,typ mA 30.72MHz input; 61.44MHz output V IL,CMOS Low level CMOS input voltage V DD 1.8V 0.2 0.6 V V IH,CMOS High level CMOS input voltage V DD 1.8V V DD 0.6 V DD V I IL,CMOS Low level CMOS input current V DD V DD,max V IL 0.0V 120 µ A I IH,CMOS High level CMOS input current V DD V DD,max V IH 1.9V µ A V OL,SDA Low level CMOS output voltage for the Sink current 3mA 0.2V DD V SDA pin I OL,CMOS Low level CMOS output current mA Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential input impedance for the LVDS input Z D,IN 132 Ω terminals V CM,IN Common-mode voltage, LVDS input 1125 1200 1375 mV V S,IN Single-ended LVDS input voltage swing 100 600 mV PP V D,IN Differential LVDS input voltage swing 200 1200 mV PP t R,OUT Output signal rise/fall time 20% 80% 100 ps t F,OUT V CM,OUT Common-mode voltage, CML outputs V DD 0.31 V DD 0.23 V DD 0.19 V V S,OUT Single-ended CML output voltage swing ac-coupled 180 230 280 mV PP V D,OUT Differential CML output voltage swing ac-coupled 360 460 560 mV PP F IN Clock input frequency 319 MHz F OUT Clock output frequency 1250 MHz L OUT Residual clock output phase noise F IN 30.72MHz F OUT 61.44MHz 400kHz PLL bandwidth at 10Hz offset 103 dBc/Hz at 100Hz offset 114 dBc/Hz at 1kHz offset 123 dBc/Hz at 10kHz offset 121 dBc/Hz at 100kHz offset 119 dBc/Hz at 1MHz offset 138 dBc/Hz at 10MHz offset 152 dBc/Hz at 20MHz offset 152 dBc/Hz Submit Documentation Feedback

www.ti.com AC ELECTRICAL CHARACTERISTICS FOR THE SDA/SCL INTERFACE (1) CDCL6010 SLLS780 FEBRUARY 2007 AC ELECTRICAL CHARACTERISTICS (continued) Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT J OUT Residual clock output jitter F IN 30.72MHz, F OUT 61.44MHz 400kHz PLL bandwidth 10Hz 1MHz offset 2.01 ps RMS 1MHz 20MHz offset 0.45 ps RMS 12kHz 20MHz offset 2.11 ps RMS T P Input-to-output delay F IN 30.72MHz, F OUT 30.72MHz ns YP[9:0] outputs, PLL bypass mode F IN 30.72MHz, F OUT 61.44MHz 150 ps YP[9:0] outputs, PLL mode F IN 30.72MHz, F OUT 61.44MHz TS OUT Clock output skew ps YP[9:0] outputs relative to YP[0] DCycle OUT Clock output duty cycle (1) (1) Output duty cycle of the bypass output and for post-divide ratio is just as good as the input duty cycle. PARAMETER MIN TYP MAX UNIT f SCL SCL frequency 400 kHz t h(START) START hold time 0.6 µ s t w(SCLL) SCL low-pulse duration 1.3 µ s t w(SCLH) SCL high-pulse duration 0.6 µ s t su(START) START setup time 0.6 µ s t h(SDATA) SDA hold time µ s t su(DATA) SDA setup time 0.6 µ s t r(SDATA) SCL SDA input rise time 0.3 µ s t f(SDATA) SCL SDA input fall time 0.3 µ s t su(STOP) STOP setup time 0.6 µ s t BUS Bus free time 1.3 µ s (1) See Figure for the timing behavior. Submit Documentation Feedback

www.ti.com DEVICE INFORMATION VCP AVDD CLKP CLKN AVDD YP0 YN0 VDD YP1 YN1 VDD VSS ADD0 VDD YN7 YP7 V DD YN6 YP6 V DD YN5 YP5 V DD SDA 13 16 19 22 14 17 20 23 15 18 21 24 CDCL6010 STA TUS 48 45 42 3947 44 41 3846 43 40 37 VCN YN9YP10 YP8AV DD V DD AV DD V DD YN10 YN8YP9 ADD1 V DD YP2 YN2 V DD YP3 YN3 V DD YP4 YN4 V DD SCL NOTE:□Exposed□thermal□pad□must□be□soldered□to VSS. CDCL6010 SLLS780 FEBRUARY 2007 48-PIN QFN (RGZ) (TOP VIEW) The CDCL6010 is available in a 48-pin QFN (RGZ) package with a pin pitch of 0,5mm. The exposed thermal pad serves both thermal and electrical grounding purposes. NOTE: The device must be soldered to ground SS using as many ground vias as possible. The device performance will be severely impacted if the exposed thermal pad is not grounded appropriately. Submit Documentation Feedback

www.ti.com CDCL6010 SLLS780 FEBRUARY 2007 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS TERMINAL NAME PIN NO. TYPE 11, 14,17, 20, 23, 26, V DD Power 1.8V digital power supply. 29, 32, 35, 38, AV DD 44, Power 1.8V analog power supply. Exposed V SS thermal pad Power Ground reference. and pin VCP, VCN I External loop filter terminals. Differential LVDS input. Single-ended 1.8V input can be dc-coupled to pin with pin either CLKP, CLKN I tied to pin (recommended) or left open. YP0, YN0 YP1, YN1 YP2, YN2 15, YP3, YN3 18, YP4, YN4 21, differential CML outputs with support for jitter cleaning and clock multiplication. Support O YP5, YN5 27, optional PLL bypass mode when jitter cleaning is not needed. YP6, YN6 30, YP7, YN7 33, YP8, YN8 40, YP9, YN9 43, YP10, YN10 46, O Differential CML output. Straight bypass with no jitter cleaning and no clock multiplication. SCL I SDA/SCL serial clock pin. Open drain. Always connect to a pull-up resistor. SDA I/O SDA/SCL bidirectional serial data pin. Open drain. Always connect to a pull-up resistor. STATUS O LVCMOS status signaling. High status indicates PLL lock. Configurable least significant bits (ADD[1:0]) of the SDA/SCL device address. The fixed ADD1, ADD0 37, I most significant bits (ADD[6:2]) of the 7-bit device address are 11010. Submit Documentation Feedback

www.ti.com VDD CLKN CLKP YN[4:0] YP[4:0] YN[9:5] YP[9:5] SDA/SCL PLL□Bypass Outputs orDisable□to□Low 3-State Post□Divider□Setting PLL□Setting VCNVCP STATUS PLL_LOCK Control I LPF External□Low-Pass□Filter AVDD LVDS CML CML YN10 YP10 RC1 SDA/SCL Divider□M VSS Control CML CML CML Divider N PFD CP VCO 2/c184 Internal LPF MUX MUX Divider Divider CDCL6010 SLLS780 FEBRUARY 2007 FUNCTIONAL BLOCK DIAGRAM Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS -250 -200 -150 -100 -50 100 150 200 250 0 0.5 1 1.5 2 t□-□Time□-□ns Differential□Output□V oltage□-□mV -300 -200 -100 100 200 300 0 10 20 30 40 50 t□-□Time□-□ns Differential□Output□V oltage□-□mV -160 -150 -140 -130 -120 -110 -100 -90 -80 10 100 1□k Offset□Frequency□-□Hz Phase□Noise□-□dBc/Hz 10□k 100□k 1□M 10□M 100□M CDCL6010 SLLS780 FEBRUARY 2007 Typical operating conditions are at V DD 1.8V and T A +25 V D,IN 200mV PP (unless otherwise noted). TRANSIENT PERFORMANCE: TRANSIENT PERFORMANCE: F IN 30.72MHz, F OUT 61.44MHz F IN 250MHz, F OUT 1.25GHz Figure Figure PHASE NOISE: F IN 30.72MHz, F OUT 61.44MHz Figure Submit Documentation Feedback

www.ti.com SDA/SCL INTERFACE SDA/SCL Bus Slave Device Address Command Code Definition CDCL6010 SLLS780 FEBRUARY 2007 This section describes the SDA/SCL interface of the The device address is made up of the fixed internal CDCL6010 device. The CDCL6010 operates as a address, 11010 (A6:A2), and configurable external slave device of the industry standard 2-pin SDA/SCL pins ADD1 (A1) and ADD0 (A0). Four different bus. It operates in the fast-mode at a bit-rate of up to devices with addresses 1101000, 1101001, 1101010 400kbit/s and supports 7-bit addressing compatible and 1101011, can be addressed via the same with the popular two-pin serial interface standard. SDA/SCL bus interface. The least significant bit of the address byte designates a write or read operation. R/W R/W Bit: ADD1 ADD0 Write to CDCL6010 device Read from CDCL6010 device BIT (C6:C0) Byte Offset for Byte Write Read and Word Write Read operation. Command Code for Byte Write Read Hex Operation Code Byte 80h Byte 81h Byte 82h Byte 83h Byte 84h Byte 85h Byte 86h Byte 87h Command Code for Word Write Read Hex Operation Code Word Byte and byte 80h Word Byte and byte 81h Word Byte and byte 82h Word Byte and byte 83h Word Byte and byte 84h Word Byte and byte 85h Word Byte and byte 86h Word Byte 87h Submit Documentation Feedback

www.ti.com SDA/SCL Timing Characteristics SCL SDA t(BUS) tSU(SDATA) t (SDATA)h tr(SM) tr(SM) tf(SM) tf(SM)tw(SCLH) VIH(SM) VIH(SM) VIL(SM) VIL(SM) P S Bit□7□(MSB) Bit□0□(LSB) Bit□6 A P tSU(STOP)t (START)h tSU(START) tw(SCLL) SDA/SCL Programming Sequence 1 7 1 1 8 1 1 S Slave□Address Data□ByteWr A A P S Sr Rd Wr A N P Start□condition Repeated□start□condition Read□(bit□value□=□1) Write□(bit□value□=□0) Acknowledge□(bit□value□=□0) Not□acknowledge□(bit□value□=□1) Stop□condition Master□to□Slave□transmission Slave□to□Master□transmission CDCL6010 SLLS780 FEBRUARY 2007 Figure Timing Diagram for the SDA/SCL Serial Control Interface LEGEND FOR PROGRAMMING SEQUENCE Byte Write Programming Sequence: S Slave Address Wr A Command Code A Data Byte A P Byte Read Programming Sequence: Wr Command S Slave Address A A S Slave Address Rd A Data Byte N P Code Submit Documentation Feedback

www.ti.com SDA/SCL Bus Configuration Command Bitmap Byte Byte Byte CDCL6010 SLLS780 FEBRUARY 2007 Word Write Programming Sequence: S Slave Address Wr A Command Code A Data Byte Low A Data Byte High A P Word Read Programming Sequence: Slave Command Slave S Wr A A S Rd A Data Byte A Data Byte N P Address Code Address Power Up Bit Bit Name Description/Function Type Condition Reference To PLL-LOCK if PLL has achieved lock, otherwise R MANF[6] Manufacturer reserved R MANF[5] Manufacturer reserved R MANF[4] Manufacturer reserved R MANF[3] Manufacturer reserved R MANF[2] Manufacturer reserved R MANF[1] Manufacturer reserved R MANF[0] Manufacturer reserved R Power Up Bit Bit Name Description/Function Type Condition Reference To RES Reserved R/W RES Reserved R/W ENPH Phase select enable R/W PH1[4] Phase select for YP[9:5] and YN[9:5] R/W Table Table PH1[3] Phase select for YP[9:5] and YN[9:5] R/W Table Table PH1[2] Phase select for YP[9:5] and YN[9:5] R/W Table Table PH1[1] Phase select for YP[9:5] and YN[9:5] R/W Table Table PH1[0] Phase select for YP[9:5] and YN[9:5] R/W Table Table Power Up Bit Bit Name Description/Function Type Condition Reference To RES Reserved R/W RES Reserved R/W ENP1 Post-divider enable; if output YP[9:5] and YN[9:5] are disabled R/W ENBP1 Bypass PLL for post-divider P1: If input is CLKP/CLKN, if input is PLL R/W clock SELP1[3] Divide ratio select for post-divider R/W Table SELP1[2] Divide ratio select for post-divider R/W Table SELP1[1] Divide ratio select for post-divider R/W Table SELP1[0] Divide ratio select for post-divider R/W Table Submit Documentation Feedback

www.ti.com Byte Byte Byte CDCL6010 SLLS780 FEBRUARY 2007 Bit Power Up Bit Name Description/Function Type Condition Reference To RES Reserved R/W RES Reserved R/W PLLLOC PLL Lock Overwrite: If output not gated by PLL Lock status. R/W K OW PH0[4] Phase select for YP[4:0] and YN[4:0] R/W Table Table PH0[3] Phase select for YP[4:0] and YN[4:0] R/W Table Table PH0[2] Phase select for YP[4:0] and YN[4:0] R/W Table Table PH0[1] Phase select for YP[4:0] and YN[4:0] R/W Table Table PH0[0] Phase select for YP[4:0] and YN[4:0] R/W Table Table Power Up Bit Bit Name Description/Function Type Condition Reference To RES Reserved R/W RES Reserved R/W ENP0 Post-divider enable. If output YP[4:0] and YN[4:0] are disabled R/W ENBP0 Bypass PLL for post-divider P0. If input is CLKP/CLKN; if input is PLL R/W clock SELP0[3] Divide ratio select for post-divider R/W Table SELP0[2] Divide ratio select for post-divider R/W Table SELP0[1] Divide ratio select for post-divider R/W Table SELP0[0] Divide ratio select for post-divider R/W Table Power Up Bit Bit Name Description/Function Type Condition Reference To EN Chip enable; if chip is in Iddq mode R/W ENDRV10 YP10, YN10 enable; if output is disabled R/W ENDRV9 YP[9], YN[9] enable; if output is disabled R/W ENDRV8 YP[8], YN[8] enable; if output is disabled R/W ENDRV7 YP[7], YN[7] enable; if output is disabled R/W ENDRV6 YP[6], YN[6] enable; if output is disabled R/W ENDRV5 YP[5], YN[5] enable; if output is disabled R/W ENDRV4 YP[4], YN[4] enable; if output is disabled R/W Submit Documentation Feedback

www.ti.com Byte Byte CDCL6010 SLLS780 FEBRUARY 2007 Power Up Bit Bit Name Description/Function Type Condition Reference To ENDRV3 YP[3], YN[3] enable; if output is disabled R/W ENDRV2 YP[2], YN[2] enable; if output is disabled R/W ENDRV1 YP[1], YN[1] enable; if output is disabled R/W ENDRV0 YP[0], YN[0] enable; if output is disabled R/W SELBW[3] PLL BW select; if external loop filter is expected R/W Table SELBW[2] PLL BW select; if external loop filter is expected R/W Table SELBW[1] PLL BW select; if external loop filter is expected R/W Table SELBW[0] PLL BW select; if external loop filter is expected R/W Table Bit Power Up Bit Name Description/Function Type Condition Reference To ENPLL PLL enable; if PLL is switched off R/W RES Reserved R/W SELM[1] Divide ratio select for input clock CLKP and CLKN R/W Table SELM[0] Divide ratio select for input clock CLKP and CLKN R/W Table SELN[3] Divide ratio select for pre-divider N (PLL clock) R/W Table SELN[2] Divide ratio select for pre-divider N (PLL clock) R/W Table SELN[1] Divide ratio select for pre-divider N (PLL clock) R/W Table SELN[0] Divide ratio select for pre-divider N (PLL clock) R/W Table Submit Documentation Feedback

www.ti.com CDCL6010 SLLS780 FEBRUARY 2007 Table Divide Ratio Settings for Post-Divider or Divide SELP1[3] or SELP1[2] or SELP1[1] or SELP1[0] or Ratio SELP0[3] SELP0[2] SELP0[1] SELP0[0] Notes Default Table Divide Ratio Settings for Divider N Divide Ratio SELN[3] SELN[2] SELN[1] SELN[0] Notes Default Table Divide Ratio Settings for Divider M Divide Ratio SELM[1] SELM[0] Notes Default Submit Documentation Feedback

www.ti.com CDCL6010 SLLS780 FEBRUARY 2007 Table Phase Settings for Divide Ratio 10, 20, 40, With PH0[4:0] 00000 PH1 Divide Phase Lead Ratio [4] [3] [2] [1] [0] (radian) Notes X X X X X Phase setting not available X X X X X X X X π /2) X X X 00000:Default X X X π /4) X X X 2(2 π /4) X X X 3(2 π /4) X X X X π /8) X X 2(2 π /8) X X 3(2 π /8) X X 4(2 π /8) X X 5(2 π /8) X X 6(2 π /8) X X 7(2 π /8) X X π /16) X 2(2 π /16) X 3(2 π /16) X 4(2 π /16) X 5(2 π /16) X 6(2 π /16) X 7(2 π /16) X 8(2 π /16) X 9(2 π /16) X 10(2 π /16) X 11(2 π /16) X 12(2 π /16) X 13(2 π /16) X 14(2 π /16) X 15(2 π /16) Submit Documentation Feedback

www.ti.com CDCL6010 SLLS780 FEBRUARY 2007 Table Phase Settings for Divide Ratio 16, With PH0[4:0] 00000 PH1 Divide Phase Lead Ratio [4] [3] [2] [1] [0] (radian) Notes X X X X X Phase setting not available X X X X X X X X π /2) X X X X X X π /4) X X X 2(2 π /4) X X X 3(2 π /4) X X X X π /8) X X 2(2 π /8) X X 3(2 π /8) X X 4(2 π /8) X X 5(2 π /8) X X 6(2 π /8) X X 7(2 π /8) X X π /16) X 2(2 π /16) X 3(2 π /16) X 4(2 π /16) X 5(2 π /16) X 6(2 π /16) X 7(2 π /16) X 8(2 π /16) X 9(2 π /16) X 10(2 π /16) X 11(2 π /16) X 12(2 π /16) X 13(2 π /16) X 14(2 π /16) X 15(2 π /16) Submit Documentation Feedback

www.ti.com CDCL6010 SLLS780 FEBRUARY 2007 Table Phase Settings for Divide Ratio 16, (continued) With PH0[4:0] 00000 PH1 Divide Phase Lead Ratio [4] [3] [2] [1] [0] (radian) Notes π /32) 2(2 π /32) 3(2 π /32) 4(2 π /32) 5(2 π /32) 6(2 π /32) 7(2 π /32) 8(2 π /32) 9(2 π /32) 10(2 π /32) 11(2 π /32) 12(2 π /32) 13(2 π /32) 14(2 π /32) 15(2 π /32) 16(2 π /32) 17(2 π /32) 18(2 π /32) 19(2 π /32) 20(2 π /32) 21(2 π /32) 22(2 π /32) 23(2 π /32) 24(2 π /32) 25(2 π /32) 26(2 π /32) 27(2 π /32) 28(2 π /32) 29(2 π /32) 30(2 π /32) 31(2 π /32) Submit Documentation Feedback

www.ti.com FREQUENCY SETTINGS FOR SOME (1) C R C On-Chip Loop (kHz) [3] [2] [1] [0] (nF) Ω (nF) Filter ON/OFF Notes 400 N/A N/A N/A ON Default 350 2.2 8660 OFF 300 3.3 7500 OFF 250 4.7 6200 OFF 200 8.2 4990 OFF 175 4300 OFF 150 3740 OFF 125 3090 OFF 100 2490 0.24 OFF 1870 0.82 OFF 150 1210 2.70 OFF 680 470 OFF 3300 220 OFF (1) Refer to Functional Block Diagram for the external low pass filter architecture. APPLICATION PROTOCOL Output Output VCO PLL Ref Clock Ref Clock PLL Ref Clock Ref Clock Clock Divider Freq Divider Divider Max Freq Divider Divider Min Freq MHz P0, GHz N (max M (max MHz N (min M (min MHz 10G Ethernet 312.5 1.250 312.5 31.25 (XAUI) 156.25 1.250 312.5 31.25 78.125 1.250 312.5 31.25 62.5 1.250 312.5 31.25 Ethernet 250 1.250 250 31.25 Serial ATA 125 1.250 250 31.25 62.5 1.250 250 31.25 10X FIBRE CHANNEL 159.375 1.275 318.75 31.875 63.75 1.275 318.75 31.875 CPRI 245.76 1.229 245.78 30.72 122.88 1.229 245.78 30.72 61.44 1.229 245.78 30.72 30.72 1.229 245.78 30.72 OBSAI 153.6 1.229 307.2 38.4 76.8 1.229 307.2 38.4 PCI Express 250 1.250 250 31.25 Serial ATA 150 1.200 300 37.5 1.200 300 37.5 SONET 622.08 1.244 311.04 31.104 311.04 1.244 311.04 31.104 155.52 1.244 311.04 31.104 62.208 1.244 311.04 31.104 Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCL6010RGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCL6010RGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCL6010RGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCL6010RGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 Addendum-Page 1

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