CDCFR83

CDCFR83_08 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SCAS665,B][M]
• PDF pages: 15

Technical content

/C0067/C0068/C0067/C0070/C0082/C0056/C0051 /C0068/C0073/C0082/C0069/C0067/C0084 /C0082/C0065/C0077/C0066/C0085/C0083 /C0067/C0076/C0079/C0067/C0075 /C0071/C0069/C0078/C0069/C0082/C0065/C0084/C0079/C0082 SCAS665B − APRIL 2001 REVISED OCTOBER 2005 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068533-MHz Differential Clock Source for Direct Rambus Memory Systems for an 1066-MHz Data Transfer Rate /C0068Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock /C0068Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications /C0068Operates From a Single 3.3-V Supply and 120 mW at 300 MHz (Typ) /C0068Packaged in a Shrink Small-Outline Package (DBQ) /C0068Supports Frequency Multipliers: 4, 6, 8, /C0068No External Components Required for PLL /C0068Supports Independent Channel Clocking /C0068Spread Spectrum Clocking Tracking Capability to Reduce EMI /C0068Designed for Use With TI’s 133-MHz Clock Synthesizers CDC924 and CDC921 /C0068Cycle-Cycle Jitter Is Less Than 40 ps at

533 MHz

/C0068Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement /C0068Supports Industrial Temperature Range of −40 °C to 85°C

description

The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications. The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency. User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 533 MHz with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state for board testing. The CDCFR83 is characterized for operation over free-air temperatures of −40°C to 85°C. Copyright  2001 − 2005, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Direct Rambus and Rambus are trademarks of Rambus Inc. VDD IR REFCLK VDD P GNDP GNDI PCLKM SYNCLKN GNDC VDD C VDD IPD STOPB PWRDNB VDD O GNDO CLK NC CLKB GNDO V DD O MULT0 MULT1 DBQ PACKAGE (TOP VIEW) NC − No internal connection

/C0067/C0068/C0067/C0070/C0082/C0056/C0051 /C0068/C0073/C0082/C0069/C0067/C0084 /C0082/C0065/C0077/C0066/C0085/C0083 /C0067/C0076/C0079/C0067/C0075 /C0071/C0069/C0078/C0069/C0082/C0065/C0084/C0079/C0082 SCAS665B − APRIL 2001 REVISED OCTOBER 2005

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

B A PLL Phase Aligner PACLK PLLCLK ByPCLK CLK CLKB REFCLK φD SYNCLKNPCLKM MULT0 MULT1 PWRDWNB S0 S1 S2 STOPB FUNCTION TABLE † MODE S0 S1 S2 CLK CLKB Normal 0 0 0 Phase aligned clock Phase aligned clock B Bypass 1 0 0 PLLCLK PLLCLKB Test 1 1 0 REFCLK REFCLKB Output test (OE) 0 1 X Hi-Z Hi-Z Reserved 0 0 1 — — Reserved 1 0 1 — — Reserved 1 1 1 Hi-Z Hi-Z † X = don’t care, Hi-Z = high impedance

/C0067/C0068/C0067/C0070/C0082/C0056/C0051 /C0068/C0073/C0082/C0069/C0067/C0084 /C0082/C0065/C0077/C0066/C0085/C0083 /C0067/C0076/C0079/C0067/C0075 /C0071/C0069/C0078/C0069/C0082/C0065/C0084/C0079/C0082 SCAS665B − APRIL 2001 REVISED OCTOBER 2005 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION CLK 20 O Output clock CLKB 18 O Output clock (complement) GNDC 8 GND for phase aligner GNDI 5 GND for control inputs GNDO 17, 21 GND for clock outputs GNDP 4 GND for PLL MULT0 15 I PLL multiplier select MULT1 14 I PLL multiplier select NC 19 Not used PCLKM 6 I Phase detector input PWRDNB 12 I Active low power down REFCLK 2 I Reference clock S0 24 I Mode control S1 23 I Mode control S2 13 I Mode control STOPB 11 I Active low output disable SYNCLKN 7 I Phase detector input VDD C 9 VDD for phase aligner VDD IPD 10 Reference voltage for phase detector inputs and STOPB VDD IR 1 Reference voltage for REFCLK VDD O 16, 22 VDD for clock outputs VDD P 3 VDD for PLL

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

provided that (267 MHz < BUSCLK < 533 MHz) and (33 MHz < REFCLK < 100 MHz). Table 1. REFCLK and BUSCLK Frequencies Table 2. Clock Output Driver States implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

/C0067/C0068/C0067/C0070/C0082/C0056/C0051 /C0068/C0073/C0082/C0069/C0067/C0084 /C0082/C0065/C0077/C0066/C0085/C0083 /C0067/C0076/C0079/C0067/C0075 /C0071/C0069/C0078/C0069/C0082/C0065/C0084/C0079/C0082 SCAS665B − APRIL 2001 REVISED OCTOBER 2005 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 3.135 3.3 3.465 V High-level input voltage, VIH (CMOS) 0.7 × VDD V Low-level input voltage, VIL (CMOS) 0.3 × VDD V Initial phase error at phase detector inputs (required range for phase aligner)−0.5 × tc(PD) 0.5 × tc(PD) REFCLK low-level input voltage, VIL 0.3 × VDD IR V REFCLK high-level input voltage, VIH 0.7 × VDD IR V Input signal low voltage, VIL (STOPB) 0.3 × VDD IPD V Input signal high voltage, VIH (STOPB) 0.7 × VDD IPD V Input reference voltage for (REFCLK) (VDD IR) 1.235 3.465 V Input reference voltage for (PCLKM and SYSCLKN) (VDD IPD) 1.235 3.465 V High-level output current, IOH −16 mA Low-level output current, IOL 16 mA Operating free-air temperature, TA −40 85 °C timing requirements MIN MAX UNIT Input cycle time, tc(in) 10 40 ns Input cycle-to-cycle jitter 250 ps Input duty cycle over 10,000 cycles 40% 60% Input frequency modulation, fmod 30 33 kHz Modulation index, nonlinear maximum 0.5% 0.6% Phase detector input cycle time (PCLKM and SYNCLKN) 30 100 ns Input slew rate, SR 1 4 V/ns Input duty cycle (PCLKM and SYNCLKN) 25% 75%

/C0067/C0068/C0067/C0070/C0082/C0056/C0051 /C0068/C0073/C0082/C0069/C0067/C0084 /C0082/C0065/C0077/C0066/C0085/C0083 /C0067/C0076/C0079/C0067/C0075 /C0071/C0069/C0078/C0069/C0082/C0065/C0084/C0079/C0082 SCAS665B − APRIL 2001 REVISED OCTOBER 2005

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † MIN TYP ‡ MAX UNIT VO(STOP) Output voltage during CLK Stop (STOPB = 0) See Figure 1 1.1 2 VO(X) Output crossing-point voltage See Figure 1 and Figure 6 1.3 1.8 V VO Output voltage swing See Figure 1 0.4 0.6 V VIK Input clamp voltage VDD = 3.135 V, II = −18 mA −1.2 V See Figure 1 2 VOH High-level output voltage VDD = min to max,IOH = −1 mA VDD − 0.1 V VVOH High-level output voltage VDD = 3.135 V, IOH = −16 mA 2.4 V See Figure 1 1 VOL Low-level output voltage VDD = min to max,IOL = 1 mA 0.1 VVOL Low-level output voltage VDD = 3.135 V, IOL = 16 mA 0.5 V VDD = 3.135 V, VO = 1 V −32 −52 IOH High-level output current VDD = 3.3 V, VO = 1.65 V −51 mAIOH High-level output current VDD = 3.465 V, VO = 3.135 V −14.5 −21 mA VDD = 3.135 V, VO = 1.95 V 43 61.5 IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 65 mAIOL Low-level output current VDD = 3.465 V, VO = 0.4 V 25.5 36 mA IOZ High-impedance-state output current S0 = 0, S1 = 1 ±10 µA IOZ(STOP) High-impedance-state output current during CLK stop Stop = 0, VO = GND or VDD ±100 µA IOZ(PD) High-impedance-state output current in power-down state PWRDNB = 0, VO = GND or VDD −10 100 µA IIH High-level REFCLK, PCLKM, SYNCLKN, STOPB VDD = 3.465 V, VI = VDD 10 AIIH High-level input current PWRDNB, S0, S1, S2, MULT0, MULT1 VDD = 3.465 V, VI = VDD 10 µA IIL Low-level REFCLK, PCLKM, SYNCLKN, STOPB VDD = 3.465 V, VI = 0 −10 AIIL Low-level input current PWRDNB, S0, S1, S2, MULT0, MULT1 VDD = 3.465 V, VI = 0 −10 µA ZO Output High state R I at IO −14.5 mA to −16.5 mA 15 35 50 ΩZO Output impedance Low state R I at IO 14.5 mA to 16.5 mA 11 17 35 Ω Reference VDD IR, VDD IPD VDD = 3.465 V PWRDNB = 0 50 µAReference current VDD IR, VDD IPD VDD = 3.465 V PWRDNB = 1 0.5 mA C I Input capacitance VI = VDD or GND 2 pF C O Output capacitance VO = VDD or GND 3 pF IDD(PD) Supply current in power-down stateREFCLK = 0 MHz to 100 MHz, PWDNB = 0, STOPB = 1 100 µA IDD(CLKSTOP) Supply current in CLK stop stateBUSCLK configured for 533 MHz 45 mA IDD(NORMAL) Supply current in normal stateBUSCLK = 533 MHz 100 mA † VDD refers to any of the following; VDD , VDD IPD, VDD IR, VDD O, VDD C, and VDD P ‡ All typical values are at VDD = 3.3 V, TA = 25°C.

/C0067/C0068/C0067/C0070/C0082/C0056/C0051 /C0068/C0073/C0082/C0069/C0067/C0084 /C0082/C0065/C0077/C0066/C0085/C0083 /C0067/C0076/C0079/C0067/C0075 /C0071/C0069/C0078/C0069/C0082/C0065/C0084/C0079/C0082 SCAS665B − APRIL 2001 REVISED OCTOBER 2005 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT tc(out) Clock output cycle time 1.87 3.75 ns

267 MHz 80

Total cycle jitter over 1, 2,Infinite and 300 MHz 70 t(jitter) Total cycle jitter over 1, 2, 3, 4, 5, or 6 clock cycles Infinite and stopped phase alignment

356 MHz See Figure 3 60 pst(jitter) 3, 4, 5, or 6 clock cyclesstopped phase

533 MHz§ 40

t(phase) Phase detector phase error for distributed loopStatic phase error/C0125 −100 100 ps t(phase, SSC) PLL output phase error when tracking SSC Dynamic phase error/C0125 −100 100 ps t(DC) Output duty cycle over 10,000 cycles See Figure 4 45% 55% Output cycle-to-cycle Infinite and 300 MHz 70 t(DC, err) Output cycle-to-cycle duty cycle error Infinite and stopped phase alignment

356 MHz See Figure 5 60 pst(DC, err) duty cycle error stopped phase

533 MHz 50

tr, tf Output rise and fall times (measured at 20%−80% of output voltage) See Figure 7 160 400 ps ∆t Difference between rise and fall times on a single device (20%−80%) |tf − tr| See Figure 7 100 ps † All typical values are at VDD = 3.3 V, TA = 25°C. ‡ Assured by design § Jitter measurement according to Rambus validation specification state transition latency specifications PARAMETER FROM TO TEST CONDITIONS MIN TYP † MAX UNIT t(powerup) Delay time, PWRDNB↑ to CLK/CLKB output settled (excluding t(DISTLOCK)) Powerdown Normal See Figure 8 3 mst(powerup) Delay time, PWRDNB↑ to internal PLL and clock are on and settled Powerdown Norma l ms t(VDD powerup) Delay time, power up to CLK/CLKB output settled VDD Normal See Figure 8 3 mst(VDD powerup) Delay time, power up to internal PLL and clock are on and settled VDD Norma l ms t(MULT) MULT0 and MULT1 change to CLK/CLKB output resettled (excluding t(DISTLOCK)) Normal Normal See Figure 9 1 ms t(CLKON) STOPB ↑ to CLK/CLKB glitch-free clock edges CLK Stop Normal See Figure 10 10 ns t(CLKSETL) STOPB ↑ to CLK/CLKB output settled to within 50 ps of the phase before STOPB was disabled CLK Stop Normal See Figure 10 20 cycles t(CLKOFF) STOPB ↓ to CLK/CLKB output disabled Normal CLK Stop See Figure 10 5 ns † All typical values are at VDD = 3.3 V, TA = 25°C.

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

† All typical values are at VDD = 3.3 V, TA = 25°C. Figure 1. Test Load and Voltage Definitions (VO(STOP) , VO(X), VO , VOH , VOL ) Figure 2. Cycle-to-Cycle Jitter

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 8. PWRDNB Transition Timings Figure 9. MULT Transition Timings Figure 10. STOPB Transition Timings

/C0067/C0068/C0067/C0070/C0082/C0056/C0051 /C0068/C0073/C0082/C0069/C0067/C0084 /C0082/C0065/C0077/C0066/C0085/C0083 /C0067/C0076/C0079/C0067/C0075 /C0071/C0069/C0078/C0069/C0082/C0065/C0084/C0079/C0082 SCAS665B − APRIL 2001 REVISED OCTOBER 2005 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA DBQ (R-PDSO-G) PLASTIC SMALL-OUTLINE PACKAGE Gage Plane 0.008 (0,20) NOM 0.010 (0,25) 0.016 (0,40) 0.035 (0,89) 2420 Seating Plane (8,74) (8,56) 0.3370.337 (8,56) (8,74) 0.344 0.344 4073301/C 02/97 0.150 (3,81) 0.157 (3,99) 0.012 (0,30) 0.008 (0,20) A 24-PIN SHOWN 16DIM PINS A MIN A MAX 0.004 (0,10) 0.010 (0,25) 0.069 (1,75) MAX 0.244 (6,20) 0.228 (5,80) 0.197 (5,00) (4,78) 0.188 0.004 (0,10) 0°−/C0257 8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-137

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCFR83DBQ NRND SSOP/ QSOP DBQ 24 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCFR83DBQG4 NRND SSOP/ QSOP DBQ 24 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCFR83DBQR NRND SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCFR83DBQRG4 NRND SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2006 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CDCFR83DBQR SSOP/ QSOP PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCFR83DBQR SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2

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