CDCF5801DBQG4

CDCF5801_14 TI1 | Alldatasheet

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• Manufacturer or author: Texas Instruments, Incorporated [SCAS698,F]
• PDF pages: 22

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(Not Recommended for New Designs Use CDCF5801A as a Replacement) Video Graphics Low-Jitter Clock Multiplier: Gaming Products Programmable Bidirectional Delay Steps of Datacom 1.3 mUI Telecom Output Frequency Range of MHz to Noise Cancellation Created by FPGAs 280 MHz Input Frequency Range of 12.5 MHz to 240 MHz Low Jitter Generation Single-Ended REFCLK Input With Adjustable Trigger Level (Works With LVTTL, HSTL, and LVPECL) Differential/Single-Ended Output Output Can Drive LVPECL, LVDS, and LVTTL Three Power Operating Modes to Minimize Power Low Power Consumption 190 mW at 280 MHz/3.3 Packaged in a Shrink Small-Outline Package (DBQ) No External Components Required for PLL Spread Spectrum Clock Tracking Ability to Reduce EMI (SSC) The CDCF5801 provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin, while strapping the LEADLAG pin to dc high or low. Further possible are: Aligning the rising edge of the output clock signal to the input clock rising edge Avoiding PLL instability in availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2003 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 The CDCF5801 provides clock multiplication and division from a reference clock (REFCLK) signal. The device is optimized to have extremely low jitter impact from input to output. The predivider pins MULT[0:1] and post-divider pins P[0:2] provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from MHz to 280 MHz with clock input references (REFCLK) ranging from 12.5 MHz to 240 MHz. See Table for detailed frequency support. The selection of pins MULT[0:1] and P[1:2] determines the multiplication value of or The CDCF5801 offers several power-down/ high-impedance modes, selectable by pins P0, STOPB and PWRDN. Another unique capability of the CDCF5801 is the high sensitivity and wide common-mode range of the clock-input pin REFCLK by varying the voltage on the VDDREF pin. The clock signal outputs CLKOUT and CLKOUTB can be used independently to generate single-ended clock signals. The CLKOUT/CLKOUTB outputs can also be combined to generate a differential output signal suitable for LVDS, LVPECL, or HSTL/SSTL signaling. The CDCF5801 is characterized for operation over free-air temperatures of -40 C to Submit Documentation Feedback

www.ti.com PWRDNB >CLK REFCLK 01 div2 00 div4 11 div8 10 div16 PLL VDDREF/2 12.5-240 MHz Control VDDP GNDP MULT[0:1] Delay Phase Aligner DLY+ DLY- VDDPD/2 DLYCTRL 0-240 MHz LEADLAG 0-280 MHz CLKOUTB CLKOUT 25-280 MHz div2 div4 div8 P[1:2] GNDO STOPB VDDO GNDPAVDDPA Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 FUNCTIONAL BLOCK DIAGRAM Submit Documentation Feedback

www.ti.com Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 TERMINAL FUNCTIONS TERMINAL I/O NO. CLKOUT 2018 O Output CLK signal (low-noise CMOS) Complementary output CLK signal (low-noise CMOS) CLKOUTB DLYCTRL I Every rising edge on this pin delays/advances the CLKOUT/CLKOUTB signal by th of the CLKOUT/CLKOUTB period (1.3 mUI). (E.g., for a 90-degree delay or advancement one needs to provide 192 rising edges). See Table GND GND for VDDREF and VDDPD GNDO 17, GND for the output pins (CLKOUT, CLKOUTB) GNDP GND for the PLL GNDPA GND for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], STOPB, PWRDNB LEADLAG I Controls whether the output CLK is delayed or advanced relative to REFCLK. See Table MULT0 I PLL multiplication factor select. See Table MULT1 MULT[0:1] 10: MULT[0:1] 11: MULT[0:1] 00: MULT[0:1] 01: NC Not connected; leave pin floating or tied to GND. I Mode control pins (see Table Normal operation High-Z outputs and other special settings I Post divider control (see Table P[1:2] 11: div2 P[1:2] 10: div4 P[1:2] 01: div8 PWRDNB I Active-low power-down state. CLKOUT/CLKOUTB goes low, See Table IC in power down Normal operation REFCLK I Reference input clock STOPB I Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as listed in Table Outputs disabled Normal operation VDDO 16, VDD for the output pin (CLKOUT, CLKOUTB) and power down circuit VDDP VDD for PLL and input buffer VDDPA VDD for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], and STOPB VDDPD Reference voltage for inputs LEADLAG and DLYCTRL VDDREF Reference voltage for REFCLK Submit Documentation Feedback

www.ti.com PLL DIVIDER/MULITPLIER SELECTION Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 Table Input-to-Output Settings INPUT OUTPUT FREQUENCY PREDIVIDER POST DIVIDER INPUT-TO-OUTPUT FREQUENCY (MHz) NOTE (MHz) MULTIPLICATION-RATIO FROM TO FROM TO MULT0 MULT1 12.5 100 280 12.5 156 100 280 12.5 156 Normal operation (1) 140 100 280 156 156 100 240 100 240 CLKOUT high-impedance X X CLOUOTB high-impedance CLKOUT high X X Special mode of operation CLKOUTB high CLKOUT X X X CLKOUTB (1) There is some overlapping of the input frequency ranges for multiplication ratios of and For example, an input frequency of MHz for a multiplication ratio of four falls within both the 12.5 to 39-MHz range and the to 70-MHz range. For best device operation in a case such as this, always select the input frequency range nearer to the top of the table. Table Power Down Modes STATE PWRDNB STOPB CLKOUT and CLKOUTB Power down X GNDO Clock stop V O STOP Normal See Table Table Programmable Delay and Phase Alignment DLYCTR NOTE LEADLAG CLKOUT and CLKOUTB Advanced by one step: For every edges, there are one or two Each rising step size: of the CLKOUT period (1.3 mUI) at P[1:2] HI edges for which the phase aligner does not edge+ of the CLKOUT period (0.65 mUI) at P[1:2] update the phase. Therefore, CLKOUT of the CLKOUT period (0.325 mUI) at P[1:2] phase is not updated for every nd edge. Delayed by one step: The frequency of the DLYCTRL pin should Each rising step size: of the CLKOUT period (1.3 mUI) at P[1:2] always be equal to or less than the LO edge+ of the CLKOUT period (0.65 mUI) at P[1:2] frequency of the LEADLAG pin. of the CLKOUT period (0.325 mUI) at P[1:2] Submit Documentation Feedback

www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS VDDPD 2 0.2 VDDPD 2 0.2 VDDREF 2 0.2 VDDREF 2 0.2 TIMING REQUIREMENTS Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 over operating free-air temperature (unless otherwise noted) (1) V DDx (2) Supply voltage range -0.5 V to V Voltage range at any output terminal -0.5 V to V DD 0.5 V Voltage range at any input terminal -0.5 V to V DD 0.5 V T stg Storage temperature range -65 C to 150 C Lead temperature 1,6 mm (1/16 inch) from case for seconds 260 C (1) Stresses beyond those listed under, absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under, recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the GND terminals. POWER DISSIPATION RATING TABLE T A C POWER DERATING T A C PACKA RATING FACTOR (1) POWER RATING GE ABOVE T A C DBQ 830 mW 8.3 mW/ C 332 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. MIN NOM MAX UNIT VDDP, VDDPA, VDDO Supply voltage 3.3 3.6 V V IH (CMOS) High-level input voltage 0.7 VDD V V IL (CMOS) Low-level input voltage 0.3 VDD V V IL (DLYCTRL, LEADLAG) Input signal low voltage V V IH (DLYCTRL, LEADLAG) Input signal high voltage V (VDDPD) Input reference voltage for DLYCNTRL and LEADLAG 1.2 VDD V I OH High-level output current -16 mA I OL Low-level output current mA (VDDREF) (see Application Input reference voltage for REFCLK 1.2 VDD V section) V IL (see Application section) REFCLK input low voltage V V IH (see Application section) REFCLK input high voltage V T A Operating free-air temperature -40 C PARAMETER MIN MAX UNIT F mod Input frequency of modulation, (if driven by SSC CLKIN) kHz Modulation index, nonlinear maximum 0.5% 0.6% SR Input slew rate V/ns Input duty cycle on REFCLK 40% 60% Input frequency on REFCLK 12.5 240 MHz Output frequency on CLKOUT and CLKOUTB 280 MHz Allowable frequency on DLYCTRL 240 MHz Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS VDDO 2 0.2 VDDO 2 0.2 Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 TIMING REQUIREMENTS (continued) PARAMETER MIN MAX UNIT Allowable frequency on LEADLAG 280 MHz Allowable duty cycle on DLYCTRL and LEADLAG pins 25% 75% over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP (2) MAX UNIT V O(STOP) Output voltage during Clkstop mode See Figure 1.1 V V O(X) Output crossing-point voltage See Figure and Figure V V O Output voltage swing OH V OL See Figure 1.7 2.9 V V IK Input clamp voltage V DD I I -18 mA -1.2 V V DD to 3.6 See Figure 2.5 V OH High-level output voltage V V DD I OH -16 mA 2.2 V DD to 3.6 See Figure 0.4 0.6 V OL Low-level output voltage V V DD I OH mA 0.5 V DD 3.135 V O V -32 -52 I OH High-level output current V DD 3.3 V O 1.65 V -51 mA V DD 3.465 V O 3.135 V -14.5 -21 V DD 3.135 V O 1.95 V 61.5 I OL Low-level output current V DD 3.3 V O 1.65 V mA V DD 3.465 V O 0.4 V 25.5 I OZ High-impedance-state output current µ A High-impedance-state output current I OZ(STOP) Stop V O GND or V DD 100 µ A during Clk Stop High-impedance-state output current I OZ(PD) PWRDNB V O GND or V DD -10 100 µ A in power-down state I IH REFCLK; STOPB; V DD 3.6 V I V DD µ A High-level PWRDNB; P[0:2]; input current MULT[0:1]; I IL V DD 3.6 V I -10 µ A DLYCTRL; LEADLAG Output High state R I at I O -14.5 mA to -16.5 mA impedance Z O Ω (single Low state R I at I O 14.5 mA to 16.5 mA ended) PWRDNB µ A Reference I REF V DD REF; VDDPD V DD 3.6 V current PWRDNB 0.5 mA C I Input capacitance V I V DD or GND pF C O Output capacitance V O GND or V DD pF REFCLK MHz to 280 MHz; I DD (PD) Supply current in power-down state mA PWRDNB STOPB I DD (CLKSTOP) Supply current in CLK stop state BUSCLK configured for 280 MHz mA Supply current (normal operation BUSCLK 280 MHz, MULT[0:1] 10; I DD (NORMAL) mA mode) P[0:2] 011; Load See Figure (1) V DD refers to any of the following; VDDP, VDDREF, VDDO, VDDPD, and VDDPA (2) All typical values are at V DD 3.3 T A Submit Documentation Feedback

www.ti.com JITTER SPECIFICATION Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 over recommended free-air temperature range and V CC range (unless otherwise noted) TEST CONDITIONS PARAMETER TYP (ps) MAX (ps) REFCLK CLKOUT MULT[0:1] P[0:2] NOTES (MHz) (MHz) Period rms (1-sigma jitter, full 001 frequency band) Period p-p 120 225 Cycle to cycle 165 Cycle to cycle 165 RMS phase jitter (accumulated, 160 100 kHz-12.5 MHz) Period rms (1-sigma jitter, full 001 frequency band) Period p-p Cycle to cycle Cycle to cycle Phase RMS phase jitter (accumulated, aligner 100 kHz-25 MHz) running (CLKOUT Period rms (1-sigma jitter, full 100 100 010 tight to frequency band) LEADLAG; Period p-p REFCLK t (jitter) Cycle to cycle tight to DLYCTRL). Cycle to cycle All typical RMS phase jitter (accumulated, values are 100 kHz-40 MHz) at VDD 3.3 Period rms (1-sigma jitter, full 156 156 010 frequency band) T A Period p-p Cycle to cycle Cycle to cycle RMS phase jitter (accumulated, 100 kHz-40 MHz) Period rms (1-sigma jitter, full 200 200 011 frequency band) Period p-p Cycle to cycle Cycle to cycle RMS phase jitter (accumulated, 100 kHz-40 MHz) Submit Documentation Feedback

www.ti.com SWITCHING CHARACTERISTICS STATE TRANSITION LATENCY SPECIFICATIONS Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 JITTER SPECIFICATION (continued) over recommended free-air temperature range and V CC range (unless otherwise noted) TEST CONDITIONS PARAMETER TYP (ps) MAX (ps) REFCLK CLKOUT MULT[0:1] P[0:2] NOTES (MHz) (MHz) Period rms (1-sigma jitter, full 200 011 frequency band) Period p-p Cycle to cycle Cycle to cycle Period rms (1-sigma jitter, full 100 010 frequency band) Period p-p Cycle to cycle Cycle to cycle Period rms (1-sigma jitter, full 280 011 Phase frequency band) aligner not running Period p-p (LEADLAG Cycle to cycle DLYCTRL Cycle to cycle t (jitter) 0). All Period rms (1-sigma jitter, full 001 typical frequency band) values are at Period p-p VDD 3.3 Cycle to cycle T A Cycle to cycle Period rms (1-sigma jitter, full 156 010 frequency band) Period p-p Cycle to cycle Cycle to cycle Period rms (1-sigma jitter, full 62.5 125 011 frequency band) Period p-p Cycle to cycle Cycle to cycle over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t (DC) Output duty cycle over 1000 cycles See Figure 42% 58% t r t f Output rise and fall times (measured at 20%-80% of output voltage See Figure 150 250 350 ps TEST PARAMETER FROM TO MIN TYP MAX UNIT CONDITION Delay time, PWRDNB to CLKOUT CLKOUTB settled t (powerup) Power down Normal See Figure ms Delay time, PWRDNB to internal PLL and clock are on and settled Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION TESTING CONDITIONS CLKOUT 10 pF 50 Ω 50 Ω CLKOUTB VCM CLKOUT CLKOUTB tCYCLE(i) Cycle-to-Cycle Jitter (t(jitter)) = | tCYCLE(i) - tCYCLE(i+1) | over 1000 consecutive cycles tCYCLE(i+1) Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 STATE TRANSITION LATENCY SPECIFICATIONS (continued) TEST PARAMETER FROM TO MIN TYP MAX UNIT CONDITION Delay time, power up to CLKOUT output settled t (VDDpowerup) V DD Normal See Figure ms Delay time, power up to internal PLL and clock are on and settled MULT0 and MULT1 change to t (MULT) Normal Normal See Figure ms CLKOUT output resettled STOPB to CLKOUT glitch-free clock t (CLKON) CLK stop Normal See Figure ns edges STOPB to CLKOUT output settled to t (CLKSETL) within ps of the phase before CLK stop Normal See Figure cycles STOPB was disabled t (CLKOFF) STOPB to CLKOUT output disabled Normal CLK stop See Figure ns Delay time, PWRDNB to the device t (powerdown) Normal Power down See Figure ms in the power-down mode Maximum time in CLKSTOP (STOPB t (STOP) before reentering normal mode STOPB Normal See Figure 100 µ s (STOPB Minimum time in normal mode t (ON) (STOPB before reentering Normal CLK stop See Figure 100 ms CLKSTOP (STOPB Figure Test Load and Voltage Definitions V OH V OL V O(STOP) Figure Cycle-to-Cycle Jitter Submit Documentation Feedback

www.ti.com CLKOUT CLKOUTB tPW+ tCYCLE Duty Cycle = (tPW+/tCYCLE) CLKOUT CLKOUTB VO(X)+ VO(X), nom VO(X)- 80% tftr 20% VOL VOH PWRDNB CLKOUTB t(powerdown) t(powerup) CLKOUT MULT0 and/or MULT1 CLKOUTB t(MULT) CLKOUT Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION (continued) Figure Output Duty Cycle Figure Crossing Point Voltage Figure Voltage Waveforms Figure PWRDNB Transition Timings Figure MULT Transition Timings Submit Documentation Feedback

www.ti.com STOPB t(CLKOFF) (see Note A) t(ON) t(STOP) t(CLKSETL) t(CLKON) (see Note A) Clock output settled within 50 ps of the phase before disabled Clock enabled and glitch free Output clock not specified glitches ok CLKOUT CLKOUTB Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION (continued) V ref V O 200 mV Figure STOPB Transition Timings Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION APPLICATION EXAMPLE Z = 50 Ω Z = 50 Ω CDCV304 Clock Buffer

25 MHz

3.3 V CLK 35 Ω 3.3 V 3.3 V CDCF5801 CDCV304 Clock Buffer CLK Z = 50 Ω ; Length = L1 Z = 50 Ω Outputs are Phase Aligned Between the Two Buffers 3.3 V Z = 50 Ω ; Length = L1 30 Ω 3.3 V SELECTING VDDREF Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 The following figure shows an example of using the CDCF5801 as a phase aligner de-skewing the unknown buffer delay of the two CDCV304s in the circuit. This circuitry would not be possible with a simple PLL because the feedback of the PLL would have the second CDCV304 in the loop, causing instability of the PLL due to a long delay. Figure Application Example NOTE: If an active element (microcontroller, ASIC, DSP FPYA, DSP, etc.) is used in the CDCF5801 CLKOUT to DLYCTRL feedback loop, see application report SCAA075. Generally, VDDREF can be set to any value between 1.2 V and VDD. The setting of VDDREF directly influences the trigger voltage of the input. Special care must be taken when using small signal swings to drive the CVDCF5801 input (e.g., PECL). It is recommended to connect VDDREF directly to VDD, ac-couple the REFCLK input, and rebias the signal. The following circuit is recommended to drive the CDCF5801 from a differential clock signal like PECL. Submit Documentation Feedback

www.ti.com Z = 50 Ω VDDREF REFCLK GNDP GND CDCF5801100 Ω 150 Ω 150 Ω PECL

3.3 V ± 10%

100 Ω Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 APPLICATION INFORMATION (continued) NOTE: If more signal swing is required and an unterminated transmission is on option, then and can both be replaced with 10-k Ω resistors. Submit Documentation Feedback

www.ti.com Revision History Not Recommended for New Designs CDCF5801 SCAS698F SEPTEMBER 2003 REVISED APRIL 2006 DATE REV PAGE SECTION E Application Example Changed first paragraph and changed connection in Figure DEC D Unknown FEB C Unknown OCT B Unknown OCT A Unknown SEP Original version Submit Documentation Feedback

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples CDCF5801DBQ NRND SSOP DBQ 24 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCF5801 CDCF5801DBQG4 NRND SSOP DBQ 24 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCF5801 CDCF5801DBQR NRND SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCF5801 CDCF5801DBQRG4 NRND SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCF5801 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 11-Apr-2013 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCF5801DBQR SSOP DBQ 24 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 2

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