CDCF2510PW

CDCF2510_15 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SCAS628,D]
• PDF pages: 15

Technical content

/C0067/C0068/C0067/C0070/C0050/C0053/C0049/C0048 /C0051/C0046/C0051/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Use CDCVF2510A as a Replacement for this Device /C0068Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 /C0068Spread Spectrum Clock Compatible /C0068Operating Frequency 25 MHz to 140 MHz /C0068Static Phase Error Distribution at 66 MHz to 133 MHz is ±125 ps /C0068Jitter (cyc−cyc) at 66 MHz to 133 MHz Is |70| ps /C0068Available in Plastic 24-Pin TSSOP /C0068Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications /C0068Distributes One Clock Input to One Bank of

10 Outputs

/C0068Output Enable Pin to Enable/Disable All 10 Outputs /C0068External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input /C0068On-Chip Series Damping Resistors /C0068No External RC Network Required /C0068Operates at 3.3 V

description

The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2510 operates at a 3.3-V V CC . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. The outputs can be enabled/disabled with the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCF2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCF2510 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV CC to ground. The CDCF2510 is characterized for operation from 0°C to 85°C. For application information see the High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039) application reports. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright  2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CLK AV CC VCC 1Y9 1Y8 GND GND 1Y7 1Y6 1Y5 V CC FBIN AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 V CC G FBOUT PW PACKAGE (TOP VIEW)

/C0067/C0068/C0067/C0070/C0050/C0053/C0049/C0048 /C0051/C0046/C0051/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS628D − APRIL 1999 − REVISED DECEMBER 2004

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(0:9) FBOUT X L L L L HL H H H H H functional block diagram 1Y2 1Y1 1Y0 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÁÁÁÁÁÁ PLL FBIN AV CC CLK G 1Y7 1Y6 1Y5 1Y8 FBOUT 1Y3 1Y4 1Y921 AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (PW) 0°C to 85°C CDCF2510PWR

/C0067/C0068/C0067/C0070/C0050/C0053/C0049/C0048 /C0051/C0046/C0051/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL TYPE DESCRIPTIONNAME NO. TYPE DESCRIPTION CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CDCF2510 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. G 11 I Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25-Ω series-damping resistor. 1Y (0:9) 3, 4, 5, 8, 9, 15, 16, 17, 20, O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via the G input. These outputs can be disabled to a logic-low state by deasserting the G control input. Each output has an integrated 25-Ω series-damping resistor. AV CC 23 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC 2, 10, 14, 22Power Power supply GND 6, 7, 18, 19Ground Ground

/C0067/C0068/C0067/C0070/C0050/C0053/C0049/C0048 /C0051/C0046/C0051/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS628D − APRIL 1999 − REVISED DECEMBER 2004

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range applied to any output in the high or low state, VO † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. AV CC must not exceed VCC . 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 4.6 V maximum. 4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions (see Note 5) MIN MAX UNIT Supply voltage, VCC , AVCC 3 3.6 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V Input voltage, VI 0 VCC V High-level output current, IOH −12 mA Low-level output current, IOL 12 mA Operating free-air temperature, TA 0 85 °C NOTE 5: Unused inputs must be held high or low to prevent them from floating. timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT fclk Clock frequency 25 140 MHz Input clock duty cycle 40% 60% Stabilization time‡ 1 ms ‡ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application.

/C0067/C0068/C0067/C0070/C0050/C0053/C0049/C0048 /C0051/C0046/C0051/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC , AVCC MIN TYP † MAX UNIT VIK Input clamp voltage II = −18 mA 3 V −1.2 V IOH = −100 µA MIN to MAX VCC −0.2 VOH High-level output voltage IOH = −12 mA 3 V 2.1 VVOH High-level output voltage IOH = −6 mA 3 V 2.4 V IOL = 100 µA MIN to MAX 0.2 VOL Low-level output voltage IOL = 12 mA 3 V 0.8 VVOL Low-level output voltage IOL = 6 mA 3 V 0.55 V VO = 1 V 3.135 V −32 IOH High-level output current VO = 1.65 V 3.3 V −36IOH High-level output current VO = 3.135 V 3.465 V −12 VO = 1.95 V 3.135 V 34 IOL Low-level output current VO = 1.65 V 3.3 V 40IOL Low-level output current VO = 0.4 V 3.465 V 14 II Input current VI = VCC or GND 3.6 V ±5 µA ICC § Supply current VI = VCC or GND, Outputs: low or high IO = 0, 3.6 V 10 µA ∆ICC Change in supply current One input at VCC − 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V 500 µA C i Input capacitance VI = VCC or GND 3.3 V 4 pF C o Output capacitance VO = VCC or GND 3.3 V 6 pF † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ For ICC of AVCC , and ICC vs Frequency (see Figures 8 and 9). switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Note 6 and Figures 1 and 2)§ PARAMETER FROM (INPUT) TO (OUTPUT) VCC , AVCC = 3.3 V ± 0.3 V UNITPARAMETER (INPUT) (OUTPUT) MIN TYP MAX UNIT Phase error time − static (normalized) (See Figures 3 − 6) CLKIN ↑ = 66 MHz to133 MHz FBIN↑ −125 125 ps tsk(o) Output skew time¶ Any Y or FBOUT Any Y or FBOUT 200 ps Phase error time − jitter (see Note 7) Clkin = 66 MHz to 100 MHz Any Y or FBOUT −50 50 ps Jitter(cycle-cycle) Clkin = 66 MHz to 100 MHz Any Y or FBOUT |70| ps Jitter(cycle-cycle) (See Figure 7) Clkin = 100 MHz to 133 MHz Any Y or FBOUT |65| ps Duty cycle F(clkin > 60 MHz) Any Y or FBOUT 45% 55% tr Rise time (See Notes 8 and 9) VO = 1.2 V to 1.8 V, IBIS simulation Any Y or FBOUT 2.5 1 V/ns tf Fall time (See Notes 8 and 9) VO = 1.2 V to 1.8 V, IBIS simulation Any Y or FBOUT 2.5 1 V/ns § These parameters are not production tested. ¶ The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 7. Calculated per PC DRAM SPEC (tphase error, static − jitter(cycle-to-cycle)). 9. 64 MB DIMM configuration according to PC SDRAM Registered DIMM Design Support Document, Figure 20 and Table 13. Intel is a trademark of Intel Corporation. PC SDRAM Register DIMM Design Support Document is published by Intel Corporation.

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2 VOutput500 /C0087 50% V CC25 pF

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms Figure 2. Phase Error and Skew Calculations

/C0067/C0068/C0067/C0070/C0050/C0053/C0049/C0048 /C0051/C0046/C0051/C0262/C0086 /C0080/C0072/C0065/C0083/C0069/C0262/C0076/C0079/C0067/C0075 /C0076/C0079/C0079/C0080 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0261 SCAS628D − APRIL 1999 − REVISED DECEMBER 2004

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Phase Error − ps 50 60 70 80 90 100 110 120 fc − Clock Frequency − MHz −100 −150 −250 −300 −350 −400 −200 −50 −450 −500 VCC = 3.3 V C (LY) = 25 pF C (LF) = 12 pF TA = 25°C See Note A 130 140 Figure 7 300 250 200 Jitter − ps 50 60 70 80 90 100 110 120 130 140 150 100

50 Cycle to Cycle

fc − Clock Frequency − MHz VCC = 3.3 V C (LY) = 25 pF C (LF) = 12 pF TA = 25°C See Notes A and B JITTER vs CLOCK FREQUENCY NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω B. Phase error measured from CLK to FBIN C. C (LY) = Lumped capacitive load at Y D. C (LF) = Lumped feedback capacitance at FBIN Figure 8 ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY 10 30 50 70 90 110 130 150 AV CC = VCC = 3.465 V Bias = 0/3 V C (LY) = 25 pF C (LF) = 0 TA = 25°C See Notes A and B fc − Clock Frequency − MHz AICC − Analog Supply Current − mA Figure 9 SUPPLY CURRENT vs CLOCK FREQUENCY 250 150 100 200 10 30 50 70 90 110 130 150 ICC − Supply Current − mA fc − Clock Frequency − MHz 300 AV CC = VCC = 3.465 V Bias = 0/3 V C (LY) = 25 pF C (LF) = 0 TA = 25°C See Notes A and B NOTES: A. C (LY) = Lumped capacitive load at Y B. C (LF) = Lumped feedback capacitance at FBIN

www.ti.com 9-Sep-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CDCF2510PW NRND TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDCF2510 CDCF2510PWG4 NRND TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDCF2510 CDCF2510PWR NRND TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDCF2510 CDCF2510PWRG4 NRND TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDCF2510 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 9-Sep-2014 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCF2510PWR TSSOP PW 24 2000 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 2

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