CDCE913PWRG4

CDCE913_15 TI1 | Alldatasheet

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CDCE(L)9xx Clock Ethernet PHY USB Controller WiFi FPGA MHz Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design CDCE913,CDCEL913 SCAS849F –JUNE 2007–REVISED APRIL 2015 CDCEx913Programmable1-PLLVCXOClockSynthesizer With1.8-V,2.5-V,and3.3-VOutputs

1 Features 3 Description

The CDCE913 and CDCEL913 devices are modular 1• Member of Programmable Clock Generator PLL-based, low-cost, high-performance,Family programmable clock synthesizers. They generate up– CDCE913/CDCEL913: 1-PLL, 3 Outputs to three output clocks from a single input frequency. – CDCE925/CDCEL925: 2-PLL, 5 Outputs Each output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated– CDCE937/CDCEL937: 3-PLL, 7 Outputs configurable PLL.– CDCE949/CDCEL949: 4-PLL, 9 Outputs The CDCx913 has separate output supply pins,• In-System Programmability and EEPROM VDDOUT, which is 1.8 V for CDCEL913 and 2.5 V to– Serial Programmable Volatile Register 3.3 V for CDCE913. – Nonvolatile EEPROM to Store Customer The input accepts an external crystal or LVCMOSSettings clock signal. A selectable on-chip VCXO allows

Flexible Input Clocking Concept synchronization of the output frequency to an external control signal.– External Crystal: 8 MHz to 32 MHz – On-Chip VCXO: Pull Range ±150 ppm The PLL supports SSC (spread-spectrum clocking) for better electromagnetic interference (EMI)– Single-Ended LVCMOS up to 160 MHz performance.• Free Selectable Output Frequency up to 230 MHz The device supports nonvolatile EEPROM• Low-Noise PLL Core programming for easy customization of the device to– PLL Loop Filter Components Integrated the application. All device settings are programmable – Low Period Jitter (Typical 50 ps) through the SDA/SCL bus, a 2-wire serial interface.
Separate Output Supply Pins The CDCx913 operates in a 1.8-V environment. It – CDCE913: 3.3 V and 2.5 V operates in a temperature range of –40°C to 85°C. – CDCEL913: 1.8 V Device Information(1)
Flexible Clock Driver PART NUMBER PACKAGE BODY SIZE (NOM) – Three User-Definable Control Inputs CDCE913 TSSOP (14) 5.00 mm × 4.40 mm[S0/S1/S2], for Example, SSC Selection, CDCEL913 Frequency Switching, Output Enable, or Power (1) For all available packages, see the orderable addendum atDown the end of the data sheet. – Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth®, Typical Application Schematic WLAN, Ethernet, and GPS – Generates Common Clock Frequencies Used With TI-DaVinci™ , OMAP™ , DSPs – Programmable SSC Modulation – Enables 0-PPM Clock Generation
1.8-V Device Power Supply
Wide Temperature Range –40°C to 85°C
Packaged in TSSOP
Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™ )

2 Applications

D-TVs, STBs, IP-STBs, DVD Players, DVD Recorders, and Printers An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

CDCE913,CDCEL913 SCAS849F –JUNE 2007–REVISED APRIL 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2010) to Revision F Page

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision D (October 2009) to Revision E Page Changes from Revision C (August 2007) to Revision D Page
Deleted sentence - A different default setting can be programmed upon customer request. Contact Texas

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Product Folder Links: CDCE913 CDCEL913

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5 Pin Configuration and Functions

NAME NO. GND 5, 10 Ground Ground SCL: serial clock input LVCMOS (default configuration), internal pullup 500 kΩ orSCL/S2 12 I S2: user-programmable control input; LVCMOS inputs; 500-kΩ internal pullup SDA: bidirectional serial data input/output (default configuration), LVCMOS internal pullup; orSDA/S1 13 I/O or I S1: user-programmable control input; LVCMOS inputs; 500-kΩ internal pullup S0 2 I User-programmable control input S0; LVCMOS inputs; 500-kΩ internal pullup VCtrl 4 I VCXO control voltage (leave open or pull up when not used) VDD 3 Power 1.8-V power supply for the device CDCE913: 3.3-V or 2.5-V supply for all outputs VDDOUT 6, 7 Power CDCEL913: 1.8-V supply for all outputs Xin/CLK 1 I Crystal oscillator input or LVCMOS clock Input (selectable through SDA/SCL bus) Xout 14 O Crystal oscillator output (leave open or pull up when not used) Y1 11 O LVCMOS outputs Y2 9 O LVCMOS outputs Y3 8 O LVCMOS outputs

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Supply voltage –0.5 2.5 V VDDOUT CDCEL913 –0.5 VDD Output clocks supply voltage V CDCE913 –0.5 3.6 + 0.5 VI Input voltage(2)(3) –0.5 VDD + 0.5 V VO Output voltage(2) –0.5 VDDOUT + 0.5 V II Input current (VI < 0, VI > VDD) 20 mA IO Continuous output current 50 mA TJ Maximum junction temperature 125 Tstg Storage temperature –65 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CDCE913 CDCEL913

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6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V(ESD) Electrostatic discharge VCharged device model (CDM), per JEDEC specification JESD22-C101, ±1500 all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

VDD Device supply voltage 1.7 1.8 1.9 V Output Yx supply voltage for CDCE913, VDDOUT 2.3 3.6 VO V Output Yx supply voltage for CDCEL913, VDDOUT 1.7 1.9 VIL Low-level input voltage, LVCMOS 0.3 VDD V VIH High-level input voltage, LVCMOS 0.7 VDD V VI (thresh) Input voltage threshold, LVCMOS 0.5 VDD V Input voltage range, S0 0 1.9 VI(S) V Input voltage range S1, S2, SDA, SCL; VI(thresh) = 0.5 VDD 0 3.6 VI(CLK) Input voltage range CLK 0 1.9 V Output current (VDDOUT = 3.3 V) ±12 IOH /IOL Output current (VDDOUT = 2.5 V) ±10 mA Output current (VDDOUT = 1.8 V) ±8 CL Output load, LVCMOS 15 pF TA Operating free-air temperature –40 85 °C RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS(1) fXtal Crystal input frequency range (fundamental mode) 8 27 32 MHz ESR Effective series resistance 100 Ω fPR Pulling range (0 V ≤ VCtrl ≤ 1.8 V)(2) ±120 ±150 ppm Frequency control voltage, VCtrl 0 VDD V C0/C1 Pullability ratio 220 CL On-chip load capacitance at Xin and Xout 0 20 pF (1) For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085). (2) Pulling range depends on crystal type, on-chip crystal load capacitance, and PCB stray capacitance; pulling range of minimum ±120 ppm applies for crystal listed in the application report (SCAA085).

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6.4 Thermal Information(1)(2)

over operating free-air temperature range (unless otherwise noted) CDCEx913 THERMAL METRIC(3) PW [TSSOP] UNIT

14 PINS

RθJA Junction-to-ambient thermal resistance Airflow 200 lfm 92 Airflow 250 lfm 90 Airflow 500 lfm 85 RθJC(to °C/WJunction-to-case (top) thermal resistance 1.4 RθJB Junction-to-board thermal resistance 66 ψJT Junction-to-top characterization parameter 1.35 ψJB Junction-to-board characterization parameter 61.83 RθJC(b Junction-to-case (bottom) thermal resistance 62 ot) (1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-K board). (2) For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (3) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS MIN TYP(1) MAX UNIT OVERALL PARAMETER All outputs off, fCLK = 27 MHz, All PLLS on 11 IDD Supply current (see Figure 1) fVCO = 135 MHz; mA9Per PLLfOUT = 27 MHz VDDOUT = 3.3 V 1.3No load, all outputs on,IDD(OUT) Supply current (see Figure 2 and Figure 3) mAfOUT = 27 MHz VDDOUT = 1.8 V 0.7 Power-down current. Every circuit poweredIDD(PD) fIN = 0 MHz, VDD = 1.9 V 30 μAdown except SDA/SCL Supply voltage Vdd threshold for power-upV(PUC) 0.85 1.45 Vcontrol circuit fVCO VCO frequency range of PLL 80 230 MHz VDDOUT = 3.3 V 230 fOUT LVCMOS output frequency MHz VDDOUT = 1.8 V 230 LVCMOS PARAMETER VIK LVCMOS input voltage VDD = 1.7 V; II = –18 mA –1.2 V II LVCMOS input current VI = 0 V or VDD; VDD = 1.9 V ±5 μA IIH LVCMOS input current for S0/S1/S2 VI = VDD; VDD = 1.9 V 5 μA IIL LVCMOS input current for S0/S1/S2 VI = 0 V; VDD = 1.9 V –4 μA Input capacitance at Xin/Clk VIClk = 0 V or VDD 6 CI Input capacitance at Xout VIXout = 0 V or VDD 2 pF Input capacitance at S0/S1/S2 VIS = 0 V or VDD 3 CDCE913 - LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE VDDOUT = 3 V, IOH = –0.1 mA 2.9 VOH LVCMOS high-level output voltage VDDOUT = 3 V, IOH = –8 mA 2.4 V VDDOUT = 3 V, IOH = –12 mA 2.2 VDDOUT = 3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 3 V, IOL = 8 mA 0.5 V VDDOUT = 3 V, IOL = 12 mA 0.8 (1) All typical values are at respective nominal VDD. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: CDCE913 CDCEL913

CDCE913,CDCEL913 SCAS849F –JUNE 2007–REVISED APRIL 2015 www.ti.com Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH, tPHL Propagation delay PLL bypass 3.2 ns tr/tf Rise and fall time VDDOUT = 3.3 V (20%–80%) 0.6 ns tjit(cc) Cycle-to-cycle jitter(2)(3) 1 PLL switching, Y2-to-Y3 50 70 ps tjit(per) Peak-to-peak period jitter(3) 1 PLL switching, Y2-to-Y3 60 100 ps tsk(o) Output skew (4), See Table 2 fOUT = 50 MHz; Y1-to-Y3 60 ps odc Output duty cycle (5) fVCO = 100 MHz; Pdiv = 1 45% 55% CDCE913 – LVCMOS PARAMETER for VDDOUT = 2.5 V – MODE VDDOUT = 2.3 V, IOH = –0.1 mA 2.2 VOH LVCMOS high-level output voltage VDDOUT = 2.3 V, IOH = –6 mA 1.7 V VDDOUT = 2.3 V, IOH = –10 mA 1.6 VDDOUT = 2.3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 2.3 V, IOL = 6 mA 0.5 V VDDOUT = 2.3 V, IOL = 10 mA 0.7 tPLH, tPHL Propagation delay PLL bypass 3.6 ns tr/tf Rise and fall time VDDOUT = 2.5 V (20%–80%) 0.8 ns tjit(cc) Cycle-to-cycle jitter(2)(3) 1 PLL switching, Y2-to-Y3 50 70 ps tjit(per) Peak-to-peak period jitter(3) 1 PLL switching, Y2-to-Y3 60 100 ps tsk(o) Output skew(4) , See Table 2 fOUT = 50 MHz; Y1-to-Y3 60 ps odc Output duty cycle(5) fVCO = 100 MHz; Pdiv = 1 45% 55% CDCEL913 — LVCMOS PARAMETER for VDDOUT = 1.8 V – MODE VDDOUT = 1.7 V, IOH = –0.1 mA 1.6 VOH LVCMOS high-level output voltage VDDOUT = 1.7 V, IOH = –4 mA 1.4 V VDDOUT = 1.7 V, IOH = –8 mA 1.1 VDDOUT = 1.7 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 1.7 V, IOL = 4 mA 0.3 V VDDOUT = 1.7 V, IOL = 8 mA 0.6 tPLH, tPHL Propagation delay PLL bypass 2.6 ns tr/tf Rise and fall time VDDOUT = 1.8 V (20%–80%) 0.7 ns tjit(cc) Cycle-to-cycle jitter(2)(3) 1 PLL switching, Y2-to-Y3 80 110 ps tjit(per) Peak-to-peak period jitter(3) 1 PLL switching, Y2-to-Y3 100 130 ps tsk(o) Output skew(4), See Table 2 fOUT = 50 MHz; Y1-to-Y3 50 ps odc Output duty cycle(5) fVCO = 100 MHz; Pdiv = 1 45% 55% SDA/SCL PARAMETER VIK SCL and SDA input clamp voltage VDD = 1.7 V; II = –18 mA –1.2 V IIH SCL and SDA input current VI = VDD; VDD = 1.9 V ±10 μA VIH SDA/SCL input high voltage(6) 0.7 VDD V VIL SDA/SCL input low voltage(6) 0.3 VDD V VOL SDA low-level output voltage IOL = 3 mA, VDD = 1.7 V 0.2 VDD V CI SCL/SDA input capacitance VI = 0 V or VDD 3 10 pF (2) 10,000 cycles. (3) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2). (4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider. (5) odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr) (6) SDA and SCL pins are 3.3-V tolerant.

6.6 EEPROM Specification

EEcyc Programming cycles of EEPROM 100 1000 cycles EEret Data retention 10 years

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6.7 Timing Requirements: CLK_IN

over recommended ranges of supply voltage, load, and operating free-air temperature MIN NOM MAX UNIT PLL bypass mode 0 160 fCLK LVCMOS clock input frequency MHz PLL mode 8 160 tr / tf Rise and fall time CLK signal (20% to 80%) 3 ns Duty cycle CLK at VDD/2 40% 60%

6.8 Timing Requirements: SDA/SCL(1)

STANDARD FAST MODEMODE UNIT MIN MAX MIN MAX fSCL SCL clock frequency 0 100 0 400 kHz tsu(START) START setup time (SCL high before SDA low) 4.7 0.6 μs th(START) START hold time (SCL low after SDA low) 4 0.6 μs tw(SCLL) SCL low-pulse duration 4.7 1.3 μs tw(SCLH) SCL high-pulse duration 4 0.6 μs th(SDA) SDA hold time (SDA valid after SCL low) 0 3.45 0 0.9 μs tsu(SDA) SDA setup time 250 100 ns tr SCL/SDA input rise time 1000 300 ns tf SCL/SDA input fall time 300 300 ns tsu(STOP) STOP setup time 4 0.6 μs tBUS Bus free time between a STOP and START condition 4.7 1.3 μs (1) See Figure 13 Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: CDCE913 CDCEL913

6.9 Typical Characteristics

Figure 2. CDCE913 Output Current vs Output FrequencyFigure 1. CDCE913, CDCEL913 Supply Current vs PLL Figure 3. CDCEL913 Output Current vs Output Frequency

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7 Parameter Measurement Information

Figure 4. Test Load Figure 5. Test Load for 50-Ω Board Environment

Input□ClockVctr Programming and SDA/SCL Register LV CMOS Pdiv1 10-BitM 1 LV CMOS Pdiv3 7-Bit Pdiv2 7-Bit PLL Bypass LV CMOS PLL 1 with□SSC M U X1 S1/SDA S2/SCL VCXO XO LVCMOS VDDOUT CDCE913,CDCEL913 SCAS849F –JUNE 2007–REVISED APRIL 2015 www.ti.com

8 Detailed Description

8.1 Overview

The CDCE913 and CDCEL913 devices are modular PLL-based, low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. They generate up to three output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated configurable PLL. The CDCx913 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL913 and 2.5 V to 3.3 V for CDCE913. The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control signal, that is, the PWM signal. The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth, Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from, for example, a 27-MHz reference input frequency. The PLL supports spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking, which is a common technique to reduce electromagnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristics. The device supports nonvolatile EEPROM programming for easy customization of the device to the application. It is preset to a factory default configuration (see Default Device Configuration). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface. Three programmable control inputs, S0, S1, and S2, can be used to select different frequencies, change SSC setting for lowering EMI, or control other features like outputs disable to low, outputs 3-state, power down, PLL bypass, and so forth). The CDCx913 operates in a 1.8-V environment. It operates in a temperature range of –40° C to 85° C.

8.2 Functional Block Diagram

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Product Folder Links: CDCE913 CDCEL913

8.3 Feature Description

8.3.1 Control Terminal Configuration

Spread-spectrum clocking selection → spread type and spread amount selection
Frequency selection → switching between any of two user-defined frequencies
Output state selection → output configuration and power-down control The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.

Table 1. Control Terminal Definition Table 2. PLLx Setting (Can Be Selected for Each PLL Individually)(1) (1) Center/down-spread, Frequency0/1 and State0/1 are user-definable in PLLx configuration register. Table 3. PLLx Setting, Frequency Selection (Can Be Selected for Each PLL

0 Frequency0

1 Frequency1

(1) Frequency0 and Frequency1 can be any frequency within the specified fVCO range. Table 4. PLLx Setting, Output Selection(1) (Y2 ... Y3)

0 State0

1 State1

Table 5. Y1 Setting(1)

0 State 0

1 State 1

have no effect until they are written into the EEPROM. forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL). S0 is not a multi-use pin; it is a control pin only.

8.3.2 Default Device Configuration

configuration. A new register setting is programmed through the serial SDA/SCL interface. Figure 6. Default Configuration with S0, as S1 and S2 are configured as programming pins in default mode. Table 6. Factory Default Setting for Control Terminal Register(1) switches all outputs ON or OFF (as previously predefined).

8.3.3 SDA/SCL Serial Interface

transfer (up to 400 kbit/s) and supports 7-bit addressing. control pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].

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8.3.4 Data Protocol

The device supports Byte Write and Byte Read and Block Write and Block Read operations. For Byte Write/Read operations, the system controller can individually access addressed bytes. bytes defined in Byte Count must be read out to finish the read cycle correctly. each transferred byte, regardless of whether this is a Byte Write or a Block Write sequence. The offset of the indexed byte is encoded in the command code, as described in Table 7. Table 7. Slave Receiver Address (7 Bits) connected to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.

8.4 Device Functional Modes

8.4.1 SDA/SCL Hardware Interface

maximum) if many devices are connected. VOLmax = 0.4 V for the output stages (for more details see the SMBus or I2C Bus specification). Figure 7. SDA / SCL Hardware Interface

8.5 Programming

Table 8. Command Code Definition Figure 8. Generic Programming Sequence Figure 9. Byte Write Protocol Figure 10. Byte Read Protocol and should not be overwritten. Figure 11. Block Write Protocol Figure 12. Block Read Protocol

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Figure 13. Timing Diagram for SDA/SCL Serial Control Interface

8.6 Register Maps

8.6.1 SDA/SCL Configuration Registers

optimized performance at lowest jitter. Table 9. SDA/SCL Registers selected by the external control pins, S0, S1, and S2. See Control Terminal Configuration.

Table 10. Configuration Register, External Control Terminals (1) Address offset refers to the byte address in the configuration register in Table 11 and Table 12.

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Table 11. Generic Configuration Register 0 – EEPROM programming is completed.6 EEPIP 0b EEPROM programming Status4:(4) (read-only) 1 – EEPROM is in programming mode. 1 – EEPROM is permanently locked. 01h Note: PWDN cannot be set to 1 in the EEPROM.

4 PWDN 0b

7 M1 1b Clock source selection for output Y1: 0 – Input clock 1 – PLL1 clock

6 SPICON 0b 0 – Serial programming interface SDA (pin 13) and SCL (pin 12)

7 Y1_7 0b

6 Y1_6 0b

5 Y1_5 0b

4 Y1_4 0b 0 – State0 (predefined by Y1_ST0)04h Y1_x State Selection(7)

2 Y1_2 0b

1 Y1_1 1b

0 Y1_0 0b

7-bit byte count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes7:1 BCOUNT 20h must be read out to finish the read cycle correctly. (1) Writing data beyond ‘20h may affect device function. completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read). (5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible. can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM. (SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0. settings then can be selected by the external control pins, S0, S1, and S2. pF (6 pF//2 pF) to the selected CL. For more about VCXO config. and crystal recommendation, see application report SCAA085. EEPIP. If EELOCK is set to high, no EEPROM programming is possible.

Table 12. PLL1 Configuration Register

7 FS1_7 0b FS1_x: PLL1 frequency selection(4)

6 FS1_6 0b

5 FS1_5 0b

4 FS1_4 0b

2 FS1_2 0b

1 FS1_1 0b

0 FS1_0 0b

6 Y2Y3_6 0b

5 Y2Y3_5 0b

4 Y2Y3_4 0b

2 Y2Y3_2 0b

1 Y2Y3_1 1b

0 Y2Y3_0 0b

(1) Writing data beyond 20h may adversely affect device function. (2) All data is transferred MSB-first. control pins, S0, S1, and S2.

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Table 12. PLL1 Configuration Register (continued) 000h PLL1_1(5): 30-bit multiplier/divider value for frequency fVCO1_11Eh 7:3 PLL1_1R[4:0] (for more information see the PLL Multiplier/Divider Definition).

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

EEPROM. This section shows some examples of using CDCE913 in various applications.

9.2 Typical Application

Figure 14 shows the use of the CDCEL913 in an audio/video application using a 1.8-V single supply. Figure 14. Single-Chip Solution Using CDCE913 for Generating Audio/Video Frequencies

9.2.1 Design Requirements

Modulation amount (%)
Modulation frequency (>20 kHz)
Modulation shape (triangular, hershey, and others)
Center spread / down spread (± or –)

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Figure 15. Modulation Frequency (fm) and Modulation Amount Figure 16. Spread Spectrum Modulation Shapes

9.2.2 Detailed Design Procedure

9.2.2.1 Spread Spectrum Clock (SSC)

Figure 17. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock

9.2.2.2 PLL Frequency Planning

M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output divider. (1) The target VCO frequency (ƒVCO) of each PLL can be calculated: (2) The PLL internally operates as fractional divider and needs the following multiplier/divider settings:
N
P = 4 – int(log2N/M; if P < 0 then P = 0
Q = int(N'/M)
R = N′ – M × Q where N′ = N × 2P N ≥ M;

80 MHz ≤ ƒVCO ≤ 230 MHz

The values for P, Q, R, and N’are automatically calculated when using TI Pro-Clock™ software.

9.2.2.3 Crystal Oscillator Start-up

to the crystal start-up time. Figure 18. Crystal Oscillator Start-up vs PLL Lock Time

9.2.2.4 Frequency Adjustment with Crystal Oscillator Pulling

input Vctrl. If a PWM modulated signal is used as a control signal for the VCXO, an external filter is needed. Figure 19. Frequency Adjustment using PWM Input to the VCXO Control

9.2.2.5 Unused Inputs/Outputs

GND. Unused outputs should be left floating. the supply for the second output block even if it is disabled.

9.2.2.6 Switching Between XO and VCXO Mode

While in XO mode, put Vctrl = Vdd/2
Switch from X0 mode to VCXO mode
Program the internal capacitors in order to obtain 0ppm at the output.

9.2.3 Application Curves

Figure 20, Figure 21, Figure 22, and Figure 23 show CDCE913 measurements with the SSC feature enabled. Device Configuration: 27-MHz input, 27-MHz output. Figure 20. fout = 27 MHz, VCO frequency < 125 MHz, SSC Figure 21. fout = 27 MHz, VCO frequency > 175 MHz, SSC

Figure 23. Output Spectrum With SSC On, 2% CenterFigure 22. Output Spectrum With SSC Off

CDCE913,CDCEL913 SCAS849F –JUNE 2007–REVISED APRIL 2015 www.ti.com

10 Power Supply Recommendations

There is no restriction on the power-up sequence. In case VDDOUT is applied first, it is recommended to ground VDD. In case VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT. The device has a power-up control that is connected to the 1.8-V supply. This will keep the whole device disabled until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components, including the outputs. If there is a 3.3-V Vddout available before the 1.8-V, the outputs will stay disabled until the 1.8-V supply has reached a certain level.

11 Layout

11.1 Layout Guidelines

When the CDCE913 is used as a crystal buffer, any parasitics across the crystal affects the pulling range of the VCXO. Therefore, care must be taken in placing the crystal units on the board. Crystals should be placed as close to the device as possible, ensuring that the routing lines from the crystal terminals to XIN and XOUT have the same length. If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise coupling. Additional discrete capacitors can be required to meet the load capacitance specification of certain crystal. For example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an internal 10 pF. To minimize the inductive influence of the trace, it is recommended to place this small capacitor as close to the device as possible and symmetrically with respect to XIN and XOUT. Figure 24 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Ground the other side of the capacitor using a low-impedance connection to the ground plane.

Product Folder Links: CDCE913 CDCEL913

1 Place crystal with associated load

3 Use ferrite beads to isolate the device

11.2 Layout Example

Figure 24. Annotated Layout

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

12.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 13. Related Links

12.3 Trademarks

DaVinci, OMAP, Pro-Clock are trademarks of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples CDCE913PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDCE913 CDCE913PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDCE913 CDCE913PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDCE913 CDCE913PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDCE913 CDCEL913PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKEL913 CDCEL913PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKEL913 CDCEL913PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKEL913 CDCEL913PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKEL913 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

www.ti.com 11-Apr-2013 Addendum-Page 2 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CDCEL913 :

Automotive: CDCEL913-Q1 NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCE913PWR TSSOP PW 14 2000 367.0 367.0 35.0 CDCEL913PWR TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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Summary

Programmable 1-PLL VCXO Clock Synthesizer

Description

Programmable 1-PLL VCXO Clock Synthesizer

Source title CDCE913PWRG4 Datasheet(PDF) - Texas Instruments

Read CDCE913PWRG4 online.

CDCE913_15 TI1 | Alldatasheet

Document overview

Technical content

1 Features 3 Description

2 Applications

4 Revision History

2 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

4 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

6.4 Thermal Information(1)(2)

14 PINS

6.5 Electrical Characteristics

6.6 EEPROM Specification

6 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

6.7 Timing Requirements: CLK_IN

6.8 Timing Requirements: SDA/SCL(1)

6.9 Typical Characteristics

8 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

7 Parameter Measurement Information

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

10 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Control Terminal Configuration

0 Frequency0

1 Frequency1

0 State0

1 State1

0 State 0

1 State 1

8.3.2 Default Device Configuration

8.3.3 SDA/SCL Serial Interface

12 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

8.3.4 Data Protocol

8.4 Device Functional Modes

8.4.1 SDA/SCL Hardware Interface

8.5 Programming

14 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

8.6 Register Maps

8.6.1 SDA/SCL Configuration Registers

16 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

4 PWDN 0b

7 M1 1b Clock source selection for output Y1: 0 – Input clock 1 – PLL1 clock

6 SPICON 0b 0 – Serial programming interface SDA (pin 13) and SCL (pin 12)

7 Y1_7 0b

6 Y1_6 0b

5 Y1_5 0b

4 Y1_4 0b 0 – State0 (predefined by Y1_ST0)04h Y1_x State Selection(7)

2 Y1_2 0b

1 Y1_1 1b

0 Y1_0 0b

7 FS1_7 0b FS1_x: PLL1 frequency selection(4)

6 FS1_6 0b

5 FS1_5 0b

4 FS1_4 0b

2 FS1_2 0b

1 FS1_1 0b

0 FS1_0 0b

6 Y2Y3_6 0b

5 Y2Y3_5 0b

4 Y2Y3_4 0b

2 Y2Y3_2 0b

1 Y2Y3_1 1b

0 Y2Y3_0 0b

18 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

9 Application and Implementation

9.1 Application Information

9.2 Typical Application

9.2.1 Design Requirements

20 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

9.2.2 Detailed Design Procedure

9.2.2.1 Spread Spectrum Clock (SSC)

9.2.2.2 PLL Frequency Planning