CDCE72010RGCT

CDCE72010_09 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 73

Technical content

FEATURES

APPLICATIONS

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor Wide Charge-Pump Current Range From 200 µ A to 3mA High Performance LVPECL, LVDS, LVCMOS PLL Clock Synchronizer Dedicated Charge-Pump Supply for Wide Tuning Voltage Range VCOs Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support Presets Charge-Pump to V CC_CP for Fast with Manual or Automatic Selection Center-Frequency Setting of VC(X)O, Controlled Via the SPI Bus Accepts Two Differential Input (LVPECL or LVDS) References up to 500MHz (or Two SERDES Startup Mode (Depending on VCXO LVCMOS Inputs up to 250MHz) as PLL Range) Reference Auxiliary Input: Output can Serve as 2nd VCXO_IN Clock is Synchronized to One of Two VCXO Input to Drive All Outputs or to Serve as Reference Clocks PLL Feedback Signal VCXO_IN Frequencies up to 1.5GHz (LVPECL) RESET or HOLD Input Pin to Serve as Reset or 800Mhz for LVDS and 250MHz for LVCMOS Hold Functions Level Signaling REFERENCE SELECT for Manual Select Outputs Can be a Combination of LVPECL, Between Primary and Secondary Reference LVDS, and LVCMOS (Up to Differential Clocks LVPECL or LVDS Outputs or up to LVCMOS POWER DOWN PD to Put Device in Standby Outputs), Output can be Converted to an Mode Auxiliary Input as a 2nd VC(X)O. Analog and Digital PLL Lock Indicator Output Divider is Selectable to Divide by Internally Generated VBB Bias Voltages for 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, Single-Ended Input Signals 40, 42, 48, 50, 56, 60, 64, 70, or On Each Frequency Hold-Over Mode Activated by Output Individually up to Eight Dividers. HOLD Pin or SPI Bus to Improve Fail-Safe (Except for Output and Output Follows Operation Output Divider and Output Follows Output Input to All Outputs Skew Control Divider) Individual Skew Control for Each Output with SPI Controllable Device Setting Each Output Divider Individual Output Enable Control via SPI Packaged in a QFN-64 Package Interface ESD Protection Exceeds 2kV HBM Integrated On-Chip Non-Volatile Memory (EEPROM) to Store Settings without the Need Industrial Temperature Range of C to to Apply High Voltage to the Device Optional Configuration Pins to Select Between Low Jitter Clock Driver for High-End Telecom Two Default Settings Stored in EEPROM and Wireless (Input Reference to Outputs) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2008 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DESCRIPTION

PPRRII __II NN SSEECC__II NN AAuuxxiilliiaarryy IInnppuutt VCXO/□VCO□IN EEPROM Output□Divider□1 U0N U0P U1N U1P U2N U2P U3N U3P U4N U4P U5N U5P U6N U6P U7N U7P U8N U8P U9N□or AUX□IN– U9P or AUX□IN+ Output□Divider□2 Output□Divider□3 Output□Divider□4 Output□Divider□5 Output□Divider□6 Output□Divider□7 Output□Divider□8 PLL_LOCK REF_SEL POWER□DOWN RESET HOLDor MODE_SEL AUX_SEL SPI_MISO SPI_LE□(CD1) SPI_CLK□(CD2) SPI_MOSI□(CD3) Interface &□Control Feedback Divider CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The following relationship applies to the dividers: Frequency (VCXO_IN or AUX_IN) Frequency (PRI_REF or SEC_REF) (P*N)/(R*M) The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filter components. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user definable and can be any combination of up to LVPECL/LVDS outputs or up to LVCMOS outputs. The built-in synchronization latches ensure that all outputs are synchronized for very low output skew. All device settings, including output signaling, divider value selection, input selection, and many more, are programmable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the device settings. The device operates in a 3.3V environment and is characterized for operation from C to +85 Figure High Level Block Diagram of the CDCE72010 Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

Top□View Bottom□View CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 The CDCE72010 is available in a 64-pin lead-free green plastic quad flatpack package with enhanced bottom thermal pad for heat dissipation. The Texas Instruments package designator is RGC (S-PQFP-N64). TERMINAL FUNCTIONS TERMINAL I/O NO. 5,8,11,14,19 22,25,28,31 3.3V supply for the output buffers. There is no internal connection between V CC and AV CC VCC Power 34,37,40, and It is recommended that each V CC uses its own supply filter. VCC_PLL Power 3.3V PLL supply voltage for the PLL circuitry. VCC_IN 57, Power 3.3V reference input buffers and circuitry supply voltage. VCC_VCXO 51, Power 3.3V VCXO input buffer and circuitry supply voltage. GND Ground Ground connected to thermal pad internally. GND PAD Ground Ground on thermal pad. See layout recommendations. VCCA 48, Power 3.3V for internal analog circuitry power supply GND_CP Analog ground for charge pump Ground Charge pump power supply pin used to have the same supply as the external VCO/VCXO. VCC_CP Power It can be set from 2.3V to 3.6V. In SPI mode it is an open drain output and it functions as a master and in slave out as a SPI_MISO DO serial control data output from the CDCE72010. LVCMOS input, control latch enable for the Serial Programmable Interface (SPI), with SPI_LE I hysteresis in SPI mode. or CD1 In configuration default mode this pin becomes CD1. SPI_CLK LVCMOS input, serial control clock input for the SPI bus interface, with hysteresis. In I or CD2 configuration default mode this pin becomes CD2. LVCMOS input, master out slave in as a serial control data input to CDCE72010 for the SPI SPI_MOSI I bus interface. In configuration default mode this pin becomes CD3 and it should be tied to or CD3 GND. SPI MODE H when driven high or left unconnected, it defaults to SPI bus interface mode. CD MODE L If tied low the device goes into configuration default mode which is MODE_SEL I configured by CD1, CD2, CD3, and AUX_SEL (CTRL_LE, CTRL_CLK, and CTRL_MOSI). In configuration default mode the device loads various configuration defaults from the EEPROM into memory at start-up. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL I/O NO. This pin is used in CD mode only. If set to or left unconnected, it disables output and enables the AUXILIARY input to drive all outputs from output0 to output8 depending on the AUX_SEL I EEPROM configuration. If driven low in CD mode, it enables output and makes all outputs driven by the VCXO Input depending on the internal EEPROM configuration. If Auto Reference Select mode is OFF, this pin acts as an External Input Reference Select Pin; The REF_SEL signal selects one of two input clocks: REF_SEL [1]: PRI_REF is selected; REF_SEL I REF_SEL [0]: SEC_REF is selected; The input has an internal 150-k Ω pull­up resistor and if left unconnected it will default to logic level If Auto Reference Select mode in ON, this pin not used. This pin is active low and can be activated externally or by the corresponding bit in the SPI register (in case of logic high, the SPI setting is valid). POWER_DOWN I This pin switches the device into powerdown mode The input has an internal 150-k Ω pull­up resistor and if left unconnected it will default to logic level This LVCMOS input can be programmed (SPI) to act as HOLD or RESET RESET is the default function. This pin is active low and can be activated external or via the corresponding bit in the SPI register. In the case of RESET the CP (Charge Pump) is switched to 3-state and all counters are reset to zero. The LVPECL outputs are static low (N) and high (P) respectively, and the RESET or HOLD I LVCMOS outputs are all low or high if inverted. In the case of HOLD the CP (Charge Pump) is switched into 3-state mode only. After HOLD is released and with the next valid reference clock cycle, the charge pump is switched back into normal operation (CP stays in 3-state as long as no reference clock is valid). During HOLD all outputs are at normal operation. This mode allows external control of frequency hold-over mode. The input has an internal 150-k Ω pull­up resistor. VCXO IN+ I VCXO input (+) for LVPECL+, LVDS+, and LVCMOS level inputs. Complementary VCXO input for LVPECL-, LVDS- inputs. In the case of a LVCMOS level VCXO IN I input on VCXO IN+, ground this pin. Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference PRI REF+ I Clock. Universal input buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In PRI REF I the case of LVCMOS signaling, ground this pin. Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary SEC REF+ I Reference Clock. Universal input buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock. SEC REF I In the case of LVCMOS signaling, ground this pin. Analog Test Point for TI internal testing. Connect a Ω pull-down resistor or leave TESTOUTA A unconnected. LVCMOS output for TI internal testing. Leave unconnected unless it is configured as the STATUS AO/O IREF_CP pin. In this case it should be connected to a 12-k Ω resistor to GND. CP_OUT AO Charge pump output VBB AO Internal voltage bias analog output LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock. This output can be programmed to be a digital lock detect or analog lock detect (see Lock). The PLL is locked (set high), if the rising edge of either the PRI_REF or SEC_REF clock and the VCXO_IN clock at the PFD (Phase Frequency Detector) are inside PLL_LOCK AI/O the lock detect window for a predefined number of successive clock cycles. The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF clock and the VCXO_IN clock at the PFD are outside the lock detect window. The lock detect window and the number of successive clock cycles are user definable (via the SPI interface). Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

(RGZ) PACKAGE (1) (2) ABSOLUTE MAXIMUM RATINGS CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 TERMINAL FUNCTIONS (continued) TERMINAL I/O NO. U0P:U0N 7,6 U1P:U1N 10,9 U2P:U2N 13,12 U3P:U3N 21,20 The main outputs of the CDCE72010 are user definable and can be any combination of up U4P:U4N 24,23 O to LVPECL outputs, LVDS outputs, or up to LVCMOS outputs. The outputs are U5P:U5N 27,26 selectable via the SPI interface. The power-up setting is EEPROM configurable. U6P:U6N 30,29 U7P:U7N 36,35 U8P:U8N 39,38 Positive universal output buffer can be 3-stated and used as a positive universal auxiliary U9P or AUXINP I/O input buffer (It requires external termination). The auxiliary input signal can be routed to drive the outputs or the feedback loop to the PLL. Negative universal output buffer can be 3-stated and used as a negative universal U9N or AUXINN I/O auxiliary input buffer (It requires external termination). The auxiliary input signal can be routed to drive the outputs or the feedback loop to the PLL. AIRFLOW θ JP C/W) (3) θ JA C/W) (LFM) JEDEC compliant board VIAs on PAD) 1.5 100 JEDEC compliant board VIAs on PAD) 1.5 17.6 Recommended layout (10 VIAs on PAD) 1.5 22.8 100 Recommended layout (10 VIAs on PAD) 1.5 13.8 (1) The package thermal impedance is calculated in accordance with JESD and JEDEC2S2P (high-k board). (2) Connected to GND with thermal vias (0.3 mm diameter). (3) θ JP (Junction Pad) is used for the QFN package, because the main heat flow is from the junction to the GND-pad of the QFN. over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC AV CC Supply voltage range (1) 0.5 4.6 V V CC_CP V I Input voltage range (2) 0.5 V CC 0.5 V V O Output voltage range (2) 0.5 V CC 0.5 V Input current V I V I V CC mA Output current for LVPECL/LVCMOS Outputs V O V CC mA T J Junction temperature 125 C T stg Storage temperature range 150 C (1) All supply voltages have to be supplied simultaneously. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com for the CDCE72010 device for under the specified industrial temperature range of C to C MIN NOM MAX UNIT Power Supply V CC Supply voltage 3.3 3.6 V V CC_PLL V CC_IN Analog supply voltage 3.3 3.6 V CC_VCXO V CCA V CC_CP 2.3 V CC V REF at 30.72MHz VCXO at Divider set to divide by (DCR P LVPECL 491.52MHz Outputs are 30%) Divider set to divide by 2.9 W LVPECL-HS (DCR 30%) Divider set to divide by (DCR 30%) Divider set to REF at 30.72MHz VCXO at P LVDS 2.0 W divide by (DCR 30%) Divider 491.52MHz Outputs are LVDS-HS set to divide by (DCR 30%) Divider set to divide by (DCR 0%) Divider set to divide by REF at 30.72MHz VCXO at P LVCMOS 2.2 W (DCR 0%) Divider set to divide by 122.88MHz Outputs are LVCMOS (DCR 0%) DCR: Divider Current Reduction Setting REF at 30.72MHz VCXO at Dividers are disabled. Outputs are P OFF 775 mW 491.52MHz disabled. P PD Device is powered down mW Typical Operating Conditions at V CC =3.3V and C unless otherwise specified. Differential Input Mode (PRI_REF, SEC_REF, VCXO_IN and AUX_IN) V INPP Input amplitude (1) _INP V INN 0.1 1.3 V V ICM Common-mode input voltage 1.0 V CC 0.3 V Differential input current high No I IH V I V CC V CC 3.6 V µ A internal termination) Differential input current low( No I IL V I V CC 3.6 V µ A internal termination) Input capacitance on PRI_REF, SEC_REF and VCXO_REF pF Input capacitance on AUX_IN pF LVCMOS Input Mode (SPI_CLK, SPI_MOSI, SPI_LE, PD, RESET, REF_SEL, MOD_SEL) V IL Low-level input voltage LVCMOS (2) 0.3 V CC V V IH High-level input voltage LVCMOS (2) 0.7 V CC V CC V V IK LVCMOS input clamp voltage V CC II mA 1.2 V I IH LVCMOS input current V I V CC V CC 3.6 V µ A I IL LVCMOS input V I V CC 3.6 V µ A C I Input capacitance (LVCMOS V I V or V CC pF signals) (1) V INPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum V INPP of 150mV. (2) V IL and V IH are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an AC coupling to V CC is provided. Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 over recommended ranges of supply voltage, load, and operating free-air temperature (1) (2) (3) (4) PARAMETER MIN TYP MAX UNIT PRI_REF/SEC_REFIN f REF Single For single-ended inputs LVCMOS) on PRI_REF and SEC_REF 250 MHz For differential inputs (LVDS and LVPECL) on PRI_REF and f REF Diff SEC_REF 500 MHz divider set to DIV2) Duty Cycle 60% Duty cycle of PRI_REF or SEC_REF at V CC 40% Single Duty Cycle Duty cycle of PRI_REF or SEC_REF at V CC 40% 60% Diff VCXO_IN, AUX _IN f REF Single For single-ended inputs LVCMOS) 250 MHz f REF Diff For differential inputs (LVDS and LVPECL) 1500 MHz Duty Cycle 60% Duty cycle of PRI_REF or SEC_REF at V CC 40% Single Duty Cycle Duty cycle of PRI_REF or SEC_REF at V CC 40% 60% Diff SPI/Control (SPI Bus Timing) f CTRL_CLK CTRL_CLK frequency MHz SPI_MOSI to SPI_CLK setup time ns SPI_MOSI to SPI_CLK hold time ns SPI_CLK high duration ns SPI_CLK low duration ns SPI_LE to SPI_CLK setup time ns SPI_CLK to SPI_LE setup time ns SPI_LE pulse width ns SPI_MISO to SPI_CLK data valid (first valid bit after LE) ns PD RESET Hold REF_SEL Rise and fall time of the PD RESET Hold REF_SEL signal from 20% t r f ns to 80% of V CC (1) From 250MHz to 500MHz is achieved by setting the divide by in P (2) If the feedback clock (derived from the VCXO input) is less than 2MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This affects the HOLD-Over-Function as well as the PLL_LOCK signal is no longer valid. (3) Use a square wave for lower frequencies MHz). (4) Slew rate requirement Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com over the specified industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT SPI Output (MISO) PLL Digital (Output Mode) I OH High-level output current V CC 3.3 V V O 1.65 V mA I OL Low-level output current V CC 3.3 V V O 1.65 V mA High-level output voltage V OH V CC V I OH 100 µ A V CC 0.5 V for LVCMOS outputs Low-level output voltage V OL V CC V I OL 100 µ A 0.3 V for LVCMOS outputs Output capacitance on C O V CC 3.3 VO V or V CC pF MISO I OZH 3-state output current µ A V O V CC V O I OZL 3-state output current µ A PLL Analog (Input Mode) High-impedance state I OZH LOCK output current for PLL V O 3.3 V PD is set low) µ A LOCK output (2) High-impedance state I OZL LOCK output current for PLL V O V PD is set low) µ A LOCK output Positive input threshold V V CC min to max V CC 0.55 V voltage Negative input threshold V T V CC min to max V CC 0.35 V voltage VBB VCXO termination voltage depends on the settings IBB 0.2mA VBB 0.9 1.9 V of the VCXO/AUX_IN Depending on the setting input buffers Input Buffers Internal Termination Resistors (VCXO_IN,PRI_REF and SEC_REF) Termination resistance (3) Single ended Ω Phase Detector Maximum charge pump f CPmax Default PFD pulse width delay 100 MHz frequency Charge Pump Charge pump 3-state ICP3St 0.5 V VCP V CC_CP 0.5 V nA current ICPA ICP absolute accuracy V CP 0.5 V CC_CP internal reference resistor VCP 0.5 V CC_CP external reference resistor ICPA ICP absolute accuracy 12k Ω (1%) Sink/source current 0.5 V VCP V CC_CP 0.5 SPI default ICPM matching settings IVCPM ICP vs VCP matching 0.5 V VCP V CC_CP 0.5 V Voltage on STATUS PIN 12-k Ω resitor to GND V I_REF_CP when configured as (External current path for accurate charge 1.24 V I_REF_CP pump current) (1) All typical values are at V CC 3.3 T A (2) 160-k Ω pull-down resistor (3) Termination resistor can vary by 20%. Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

(CONTINUED) CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 over the specified industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT LVCMOS Output Output frequency (see f clk Load pF to GND 250 MHz Figure High-level output voltage V OH V CC min to max I OH 100 µ A V CC 0.5 V for LVCMOS outputs Low-level output voltage V OL V CC min to max I OL =100 µ A 0.3 V for LVCMOS outputs I OH High-level output current V CC 3.3 V V O 1.65 V mA I OL Low-level output current V CC 3.3 V O 1.65 V mA Phase offset without VCXO at 491.52MHz, Output is divide by t pho using available delay and reference at 30.72MHz, M and N ns adjustment delays are fixed to one value (set to 0). t pd(LH) Propagation delay from Crosspoint to V CC /2, load pF, (PLL 3.3 ns tpd(HL) VCXO_IN to Outputs bypass mode) Divide by for all dividers Skew, output-to-output Divide by for all dividers t sk(o) LVCMOS single-ended ps Divide by for divider divide by for all output 1400 other dividers Output capacitance on C O V CC 3.3 V O V or V CC pF to C O Output capacitance on V CC 3.3 V O V or V CC pF 3-state LVCMOS output I OZH V O V CC µ A current 3-state LVCMOS output I OZL V O µ A current Power-down output I OPDH V O V CC µ A current Power-down output I OPDL V O µ A current Duty cycle LVCMOS 50% to 50% t slew-rate Output rise/fall slew rate 3.6 5.2 V/ns (1) All typical values are at V CC 3.3 T A Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

(CONTINUED) CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com over the specified industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT LVDS Output f clk Output frequency Open loop config. load, See Figure 800 MHz OD Differential output voltage R L 100 Ω 160 270 mV LVDS VOD magnitude Δ VOD mV change V OS Offset voltage C to C 1.24 V Δ V OS V OS magnitude change mV Short circuit V OUT+ to V OUT mA ground Short circuit V OUT to V OUT mA ground Reference to output VCXO at 491.52MHz, Output is divide by phase offset without using and reference at 30.72MHz, M and N t pho (2) ns available delay delays are fixed to one value (set to 0), PFD: adjustment 240kHz, and N 128) t pd(LH) Propagation delay time, Crosspoint to crosspoint, load, see Figure 3.0 ns t pd(HL) VCXO_IN to output Divide by for all dividers Skew, output to output Divide by for all dividers tsk(o) (3) ps LVDS output Divide by for divider 2800 Divide by for all other dividers Output capacitance on C O V CC 3.3 V O V or V CC pF to C O Output capacitance on V CC 3.3 V O V or V CC pF Power-down output I OPDH V O V CC µ A current Power-down output I OPDL V O µ A current Duty cycle t r f Rise and fall time 20% to 80% of V outpp 110 140 160 ps LVCMOS-TO-LVDS (4) Output skew between tsk P_C LVCMOS and LVDS Crosspoint to V CC 0.9 1.4 1.9 ns outputs (1) All typical values are at V CC 3.3 T A (2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). (3) The tsk(o) specification is only valid for equal loading of all outputs. (4) Operating the LVCMOS or LVDS outputs above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS. Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

(CONTINUED) CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 over the specified industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT LVDS Hi Swing Output f clk Output frequency Open loop config. load, see Figure 800 MHz OD Differential output voltage R L =100 Ω 270 550 mV LVDS VOD magnitude Δ VOD mV change V OS Offset voltage C to C 1.24 V Δ V OS V OS magnitude change mV Short Circuit V OUT+ to V OUT mA ground Short Circuit V OUT to V OUT mA ground Reference to output VCXO at 491.52MHz, Output is divide by phase offset without using and reference at 30.72MHz. M and N t pho (2) ns available delay delays are fixed to one value. (Set to PFD: adjustment 240kHz, and N 128) t pd(LH) Propagation delay time, Crosspoint to crosspoint, load Figure 3.0 ns t pd(HL) VCXO_IN to output Divide by for all dividers Divide by for all dividers t sk(o) (3) LVDS output skew ps Divide by for divider 2800 Divide by for all other dividers Output capacitance on C O V CC 3.3 V O V or V CC pF to C O Output capacitance on V CC 3.3 V O V or V CC pF Power-down output IOPDH V O V CC µ A current Power-down output IOPDL V O µ A current Duty cycle t r f Rise and fall time 20% to 80% of V outpp 110 160 190 ps LVCMOS-TO-LVDS (4) Output skew between tsk P_C LVCMOS and LVDS Crosspoint to V CC 0.9 1.4 1.9 ns outputs (1) All typical values are at V CC 3.3 T A (2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). (3) The tsk(o) specification is only valid for equal loading of all outputs. (4) Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

(CONTINUED) CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com over the specified industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT LVPECL Output f clk Output frequency Open loop config. 1500 MHz LVPECL high-level output V OH Load, see Figure V CC 1.06 V CC 0.88 V voltage LVPECL low-level output V OL Load, see Figure V CC 2.02 V CC 1.58 V voltage |VOD| Differential output voltage Load, see Figure 610 970 mV Reference to output VCXO at 491.52MHz, Output is divide by phase offset without using and reference at 30.72MHz, M and N t pho (2) ns available delay delays are fixed to one value (set to 0), PFD: adjustment 240kHz, and N 128) t pd(LH) Propagation delay time, Crosspoint to crosspoint, load, see Figure 3.4 ns t pd(HL) VCXO_IN to output Divide by for all dividers Divide by for all dividers t sk(o) (3) LVPECL output skew ps Divide by for divider 2700 Divide by for all other dividers Output capacitance on C O V CC 3.3 V O V or V CC pF to C O Output capacitance on V CC 3.3 V O V or V CC pF Power-down output IOPDH V O V CC µ A current Power-down output IOPDL V O V µ A current Duty cycle t r f Rise and fall time 20% to 80% of V outpp 135 ps LVDS-TO-LVPECL Output skew between tsk P_C LVDS and LVPECL Crosspoint to V CC /2; 0.9 1.1 1.3 ns outputs LVCMOS-TO-LVPECL Output skew between tsk P_C LVCMOS and LVPECL Crosspoint to V CC /2; 150 260 700 ps outputs (4) (1) All typical values are at V CC 3.3 T A (2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). (3) The tsk(o) specification is only valid for equal loading of all outputs. (4) Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the output signal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS. Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

(CONTINUED) CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 over the specified industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT LVPECL Hi Swing Output f clk Output frequency Open loop config. 1500 MHz LVPECL high-level V OH Load, see Figure V CC 1.11 V CC 0.87 V output voltage LVPECL low-level output V OL Load, see Figure V CC 2.06 V CC 1.73 V voltage Differential output |VOD| Load, see Figure 760 1160 mV voltage Reference to output VCXO at 491.52MHz, Output is divide by phase offset without and reference at 30.72MHz, M and N delays t pho (2) ns using available delay are fixed to one value (set to 0), PFD: adjustment 240kHz, and N 128) t pd(LH) Propagation delay time, Crosspoint to crosspoint, load, see Figure 3.4 ns t pd(HL) VCXO_IN to output Divide by for all dividers Divide by for all dividers t sk(o) (3) LVPECL output skew ps Divide by for divider 2700 Divide by for all other dividers Output capacitance on C O V CC 3.3 V O V or V CC pF to Output capacitance on C O V CC 3.3 V O V or V CC pF Power-down output IOPDH V O V CC µ A current Power-down output IOPDL V O µ A current Duty cycle t r f Rise and fall time 20% to 80% of V outpp 135 ps LVDS-TO-LVPECL Output skew between tsk P_C LVDS and LVPECL Crosspoint to V CC 0.9 1.1 1.3 ns outputs LVCMOS-TO-LVPECL Output skew between tsk P_C LVCMOS and LVPECL Crosspoint to V CC 150 260 700 ps outputs (4) (1) All typical values are at V CC 3.3 T A (2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). (3) The tsk(o) specification is only valid for equal loading of all outputs. (4) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS and LVPECL. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

5□pfLVCMOS VCC-2 Oscilloscope 50 /c8750 /c87 150 /c87 Oscilloscope 150 /c87 50 /c87 50 /c87 CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com Figure LVCMOS Output Termination Setup Figure LVDS DC Termination Setup Figure LVPECL AC Termination Setup Figure LVPECL DC Termination Setup Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

200 400 600 800 1000 1200 1400 1600 1800 (mV) T =□25□ºCA Load□50 to/c87 VCC -2C Frequency□-□□MHz V =□3.0VCC V =□3.6VCC V =□3.3VCC 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 200 400 600 800 1000 1200 1400 1600 1800 (mV) T =□25□ºCA Load□50 to/c87 V – 2VCC V =□3.0VCC V =□3.6VCC V =□3.3VCC Frequency□-□MHz 100 200 300 400 500 600 700 800 900 100 120 140 160 180 200 220 240 260 280 300 320 (mV) T =□25□ºCA Load□100 /c87V =□3.6VCC V =□3.0VCC Frequency□-□MHz V =□3.3VCC 100 140 180 220 260 300 340 380 420 460 500 100 200 300 400 500 600 700 800 900 (mV) T =□25□ºCA Load□100 /c87 Frequency□-□MHz V =□3.0VCC V =□3.3VCC V =□3.6VCC CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 LVPECL OUTPUT SWING Hi Swing LVPECL OUTPUT SWING vs vs FREQUENCY FREQUENCY Figure Figure LVDS OUTPUT SWING Hi Swing LVDS OUTPUT SWING vs vs FREQUENCY FREQUENCY Figure Figure Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 100 200 300 400 500 V =□3.3VCC VC C =□3.6V V =□3.0VCC T =□25□ºCA Load□5pF (V) Frequency□-□MHz CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) LVCMOS OUTPUT WING vs FREQUENCY Figure 10. Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Phase noise is measured in a closed loop mode of 491.52MHz VCXO and 30.72MHz reference and a 100Hz loop. Output is measured for divide by one, output for divide by and output for divide by 16. Table Phase Noise for LVPECL High Swing Phase Noise Specifications under following configuration: VCXO 491.52MHz, REF 30.72MHz, Divide by 491.52MHz, Divide by 122.88MHz, Divide by 30.72MHz, PFD Frequency 240KHz, Charge Pump Current 2mA, Loop BW 100Hz, Output 491.52 MHZ, Output Buffer: LVPECL-HS PHASE NOISE VCXO OPEN REFERENCE LVPECL-HS LVPECL-HS LVPECL-HS UNIT AT OFFSET LOOP 30.72MHz DIVIDE BY DIVIDE BY DIVIDE BY 10Hz 107 105 dBc/Hz 100Hz 123 104 116 dBc/Hz 1kHz 113 134 115 127 139 dBc/Hz 10kHz 135 153 135 145 158 dBc/Hz 100kHz 148 156 146 155 162 dBc/Hz 1MHz 148 158 146 155 162 dBc/Hz 10MHz 149 147 156 dBc/Hz Table Phase Noise for LVDS High Swing Phase Noise Specifications under following configuration: VCXO 491.52MHz, REF 30.72MHz, Divide by 491.52MHz, Divide by 122.88MHz, DIvide by 30.72MHz, PFD Frequency 240KHz, Charge Pump Current 2mA Loop BW 100Hz, Output 491.52 MHZ, Output Buffer: LVDS-HS VCXO OPEN LVDS HS LVDS-HS LVDS-HS PARAMETER REFERENCE UNIT LOOP DIVIDE BY DIVIDE BY DIVIDE BY 10Hz 107 104 dBc/Hz 100Hz 123 105 117 dBc/Hz 1kHz 113 134 114 127 139 dBc/Hz 10kHz 135 153 135 145 151 dBc/Hz 100kHz 148 156 145 152 153 dBc/Hz 1MHz 148 158 146 152 153 dBc/Hz 10MHz 149 146 152 dBc/Hz Table Phase Noise for LVCMOS Phase Noise Specifications under following configuration: VCXO 491.52MHz, REF 30.72MHz, Divide by 491.52MHz, Divide by 122.88MHz, DIvide by 30.72MHz, PFD Frequency 240KHz, Charge Pump Current 2mA, Loop BW 100Hz, Output 491.52 MHZ, Output Buffer: LVCMOS VCXO OPEN LVCMOS LVCMOS PARAMETER REFERENCE N/A UNIT LOOP DIVIDE BY DIVIDE BY 10Hz 107 105 dBc/Hz 100Hz 123 104 116 dBc/Hz 1kHz 113 134 127 139 dBc/Hz 10kHz 135 153 140 151 dBc/Hz 100kHz 148 156 151 159 dBc/Hz 1MHz 148 158 153 160 dBc/Hz 10MHz 149 154 dBc/Hz Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

Bit0 Bit1 …… Bit29 Bit30 Bit31 SPI_CLK SPI_MOSI SPI_LE t 1 t 2 t 3 t 4 t 5 t 6 t 7 SPI_CLK SPI_MOSI SPI_MISO SPI_LE t2 t3 CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com The serial interface of the CDCE72010 is a simple bidirectional SPI interface for writing and reading to and from the registers of the device. It consists of four control lines: SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_LE. There are twelve 28-bit wide registers that can be saved to the EEPROM on-chip, and one status register that is a read only register. Those registers can be addressed by the four LSBs of a transferred word (bit and bit 3). Every transmitted word must have bits, starting with LSB first. Each word can be written separately. The transfer is initiated with the falling edge of SPI_LE; as long as SPI_LE is high, no data can be transferred. During SPI_LE low, data can be written. The data has to be applied at SPI_MOSI and has to be stable before the rising edge of SPI_CLK. The transmission is finished by a rising edge of SPI_LE. Figure 11. Timing Diagram for SPI Write Command Figure 12. Timing Diagram for SPI Read Command Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Table Register Map REGISTER COMMENTS WRITE PAYLOAD DATA) ADDRESS WRITE COMMAND ON MOSI 31,30,29,28 4,3,2,1,0 Register0 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0000 Register1 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0001 Register2 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0010 Register3 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0011 Register4 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0100 Register5 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0101 Register6 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0110 Register7 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0111 Register8 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1000 Register9 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1001 Register10 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1010 Register11 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1011 Register12 Status/Control RAM Only XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1100 Register13 Reserved XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1101 Read command (address on LSBs of Instruction XXXX XXXX XXXX XXXX XXXX XXXX AAAA 1110 payload) Instruction Write configuration to EEPROM UNLOCKED XXXX XXXX XXXX XXXX XXXX XXXX 0001 1111 Instruction Write configuration to EEPROM LOCKED XXXX XXXX XXXX XXXX 1010 XXXX 0011 1111 READ COMMAND ON MISO DATA PAYLOAD IN READ COMMAND Payload after issuing a read command on DDDD DDDD DDDD DDDD DDDD DDDD DDDD XXXX (1) MOSI (1) During a SPI READ instruction the address field of the payload should be ignored since it does not represent the address of the read register. The SPI serial protocol accepts Word Write operation only. The words include the register settings of the programmable functions of the device that can be modified to the customer application by changing one or more bits. At powerup or if the Power Down PD control signal is applied, the EEPROM loads its content into the registers. When issuing an EEPROM programming (LOCKED or UNLOCKED) instruction, a wait period of 50ms has to be inserted before another instruction is written to the device or power is removed. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com The CDCE72010 on-board EEPROM has been factory preset to the default settings listed in Table Table CDCE72010 Default Configuration Settings REGISTER DEFAULT SETTING REGISTER DEFAULT SETTING REG0000 002C0040 REG0007 EB040717 REG0001 83840051 REG0008 010C0158 REG0002 83400002 REG0009 01000049 REG0003 83400003 REG0010 0BFC07CA REG0004 81800004 REG0011 C000058B REG0005 81800005 REG0012 61E09B0C REG0006 EB040006 The default configuration programmed in the EEPROM is: a 10MHz primary reference single-ended, a 491.52MHz LVPECL VCXO running at 80kHz, and PFD with a 10Hz external loop filter. Reference Auto Select is off, M divider is set for 125, N divider is set to 768, charge pump current is set to 2.2mA, and feedback divider is set to divide by Divider is set to divide by Dividers and are set to divide by Dividers and are set to divide by Dividers and are set to divide by and Divider is set to divide by 16.Output0:LVCMOS, Output1:Hi-LVPECL, Output2: Hi-LVPECL, Output3:Hi_LVPECL, Output4:LVPECL, Output5:LVPECL, Output6:Hi-LVDS, Output7:Hi-LVDS, Output8:LVCMOS and Output9:LVCMOS. Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register SPI Mode SPI RAM POWER UP BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT Bit CONDITION Address Address Address Address INBUFSELX Reference Input Primary and secondary Buffer Type Select (LVPECL,LVDS or LVCMOS) EEPROM Buffers XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive pin INBUFSELY PRISEL When REFSELCNTRL is set to the following settings apply: If RAM Bits (2,3): No input buffer is selected/active Reference Input If RAM Bits (2,3): PRI_BUF is selected, SEC_BUF is powered down EEPROM Buffer SECSEL If RAM Bits (2,3): SEC_BUF is selected, PRI_BUF is powered down (1) If RAM Bits (2,3): Auto Select (PRI then SEC). When set to PRI- or SEC-clock is selected, depending on bits and Divider START VCXOSEL (default) EEPROM DETERM-Block When set to VCXO/AUX-clock is selected, overwrites bits and Reference Select Control to select if the control of the reference is from the internal bit in Register RAM bits and or from the external select pin. When set to the external pin REF_SEL takes over the selection between Reference PRI and SEC. Autoselect is not available. REFSELCNTRL Selection EEPROM When set to The external pin REF_SEL is ignored. The table in (Register Control and describes which reference input clock is selected and available (none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing diagram. DELAY_PFD0 PFD pulse width PFD bit PFD EEPROM PFD pulse width PFD bit DELAY_PFD1 CP_MODE Selects option [0] or option [1] EEPROM Charge Pump Determines which direction CP current will regulate (Reference Clock leads to CP_DIR EEPROM Feedback Clock, Positive CP output current [0], Negative CP output current [1]) Switches the current source in the charge pump on when set to (TI CP_SRC EEPROM Test-GTME) Charge Pump CP_SNK Diagnostics Switches the current sink in the charge pump on when set to (TI Test-GTME) EEPROM CP_OPA Switches the charge pump op-amp off when set to (TI Test-GTME) EEPROM CP_PRE Preset charge pump output voltage to V CC_CP /2, on [1], off [0] EEPROM ICP0 CP current setting bit EEPROM ICP1 Charge Pump CP current setting bit EEPROM ICP2 CP current setting bit EEPROM ICP3 CP current setting bit EEPROM RESERVED EEPROM RESERVED EEPROM Charge Pump Enables the 12-k Ω pull-down resistor at I_REF_CP pin when set to (TI IREFRES EEPROM Diagnostics Test-GTME) PECL0HISWING Output High output voltage swing in LVPECL mode if set to EEPROM CMOSMODE0PX LVCMOS mode select for OUTPUT positive pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE0PY CMOSMODE0NX LVCMOS mode select for OUTPUT negative pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE0NY RAM BITS OUTPUT TYPE OUTBUFSEL0X Output EEPROM LVPECL LVDS OUTBUFSEL0Y Output LVCMOS See Settings Above (2) EEPROM All Outputs Disabled (1) This setting is only available if the Register Bit is set to (Feedback Divider clock is set to CMOS type). (2) Use 22, 23, 24, and for setting the LVCMOS outputs. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register SPI Mode SPI RAM POWER UP BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT BIT CONDITION Address Address Address Address ACDCSEL Input Buffers If set to AC Termination, If set to DC termination EEPROM HYSTEN Input Buffers If set to Input Buffers Hysteresis enabled EEPROM TERMSEL Input Buffers If set to Input Buffer Internal Termination enabled EEPROM PRIINVBB Input Buffers If set to Primary Input Negative pin biased with internal VBB voltage EEPROM SECINVBB Input Buffers If set to Secondary Input Negative pin biased with internal VBB voltage EEPROM FAILSAFE Input Buffers If set to Fail Safe is enabled for all input buffers EEPROM PH1ADJC0 PH1ADJC1 PH1ADJC2 PH1ADJC3 Output and Coarse phase adjust select for Output Divider EEPROM PH1ADJC4 PH1ADJC5 PH1ADJC6 OUT1DIVRSEL0 OUT1DIVRSEL1 OUT1DIVRSEL2 Output Divider ratio select OUT1DIVRSEL3 Output and EEPROM (see Table OUT1DIVRSEL4 OUT1DIVRSEL5 OUT1DIVRSEL6 When set to the divider is disabled EN01DIV Output and EEPROM When set to the divider is enabled PECL1HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CMOSMODE1PX LVCMOS mode select for OUTPUT Positive Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE1PY CMOSMODE1NX LVCMOS mode select for OUTPUT Negative Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE1NY RAM BITS OUTPUT TYPE OUTBUFSEL1X Output EEPROM LVPECL LVDS OUTBUFSEL1Y Output LVCMOS See Settings Above (1) EEPROM All Outputs Disabled (1) Use 22, 23, 24, and for setting the LVCMOS outputs. Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register SPI Mode SPI RAM POWER UP BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT BIT CONDITION Address Address Address Address DLYM0 Reference phase delay M bit0 DLYM1 DELAY M Reference phase delay M bit1 EEPROM DLYM2 Reference phase delay M bit2 DLYN0 Feedback phase delay N bit0 DLYN1 DELAY N Feedback phase delay N bit1 EEPROM DLYN2 Feedback phase delay N bit2 PH2ADJC0 PH2ADJC1 PH2ADJC2 PH2ADJC3 Output Coarse phase adjust select for output divider EEPROM PH2ADJC4 PH2ADJC5 PH2ADJC6 OUT2DIVRSEL0 OUT2DIVRSEL1 OUT2DIVRSEL2 Output Divider ratio select OUT2DIVRSEL3 Output EEPROM (see Table OUT2DIVRSEL4 OUT2DIVRSEL5 OUT2DIVRSEL6 When set to the divider is disabled EN2DIV Output EEPROM When set to the divider is enabled PECL2HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CMOSMODE2PX LVCMOS mode select for OUTPUT Positive Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE2PY CMOSMODE2NX LVCMOS mode select for OUTPUT Negative Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE2NY RAM BITS OUTPUT TYPE OUTBUFSEL2X Output EEPROM LVPECL LVDS OUTBUFSEL2Y Output LVCMOS See Settings Above (1) EEPROM All Outputs Disabled (1) Use 22, 23, 24, and for setting the LVCMOS outputs. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register SPI Mode SPI RAM POWER UP BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT BIT CONDITION Address Address Address Address When set to the REF-clock frequency detector is ON DIS_FDET_REF PLL Freq. Detect EEPROM When set to it is switched OFF When set to the feedback path frequency detector is switched OFF DIS_FDET_FB Diagnostics EEPROM (TI Test-GTME) BIAS_DIV01 When BIAS_DIV01 1:0 Output Divider 00, No current reduction for all output-divider EEPROM and 01, Current reduction for all output-divider by about 20% BIAS_DIV01 10, Current reduction for all output-divider by about 30% BIAS_DIV23 When BIAS_DIV23 1:0 Output Divider 00, No current reduction for all output-divider EEPROM and 01, Current reduction for all output-divider by about 20% BIAS_DIV23 10, Current reduction for all output-divider by about 30% PH3ADJC0 PH3ADJC1 PH3ADJC2 PH3ADJC3 Output Coarse phase adjust select for Output Divider EEPROM PH3ADJC4 PH3ADJC5 PH3ADJC6 OUT3DIVRSEL0 OUT3DIVRSEL1 OUT3DIVRSEL2 Output Divider ratio select OUT3DIVRSEL3 Output EEPROM (see Table OUT3DIVRSEL4 OUT3DIVRSEL5 OUT3DIVRSEL6 When set to the divider is disabled EN3DIV Output EEPROM When set to the divider is enabled PECL3HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CMOSMODE3PX LVCMOS mode select for OUTPUT Positive Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE3PY CMOSMODE3NX LVCMOS mode select for OUTPUT Negative Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE3NY RAM BITS OUTPUT TYPE OUTBUFSEL3X Output EEPROM LVPECL LVDS OUTBUFSEL3Y Output LVCMOS See Settings Above (1) EEPROM All Outputs Disabled (1) Use 22, 23, 24, and for setting the LVCMOS outputs Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register SPI Mode SPI RAM POWER UP BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT BIT CONDITION Address Address Address Address RESERVED EEPROM RESERVED EEPROM RESERVED EEPROM RESERVED EEPROM If set to it will 3-state the charge pump to act as a HOLD on Loss of HOLDONLOR HOLD-Over EEPROM Reference Clocks Primary and Secondary) RESERVED EEPROM PH4ADJC0 PH4ADJC1 PH4ADJC2 PH4ADJC3 Output Coarse phase adjust select for Output Divider EEPROM PH4ADJC4 PH4ADJC5 PH4ADJC6 OUT4DIVRSEL0 OUT4DIVRSEL1 OUT4DIVRSEL2 Output Divider ratio select OUT4DIVRSEL3 Output EEPROM (see Table OUT4DIVRSEL4 OUT4DIVRSEL5 OUT4DIVRSEL6 When set to the divider is disabled EN4DIV Output EEPROM When set to the divider is enabled PECL4HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CMOSMODE4PX LVCMOS mode select for OUTPUT Positive Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE4PY CMOSMODE4NX LVCMOS mode select for OUTPUT Negative Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE4NY RAM BITS OUTPUT TYPE OUTBUFSEL4X Output EEPROM LVPECL LVDS OUTBUFSEL4Y Output LVCMOS See Settings Above (1) EEPROM All Outputs Disabled (1) Use 22, 23, 24, and for setting the LVCMOS outputs Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register SPI Mode SPI RAM POWER UP BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT BIT CONDITION Address Address Address Address BIAS_DIV45 When BIAS_DIV45 1:0 Output Divider 00, No current reduction for all output-divider EEPROM and 01, Current reduction for all output-divider by about 20% BIAS_DIV45 10, Current reduction for all output-divider by about 30% BIAS_DIV67 When BIAS_DIV67 1:0 Output Divider 00, No current reduction for all output-divider EEPROM and 01, Current reduction for all output-divider by about 20% BIAS_DIV67 10, Current reduction for all output-divider by about 30% RESERVED EEPROM RESERVED EEPROM PH5ADJC0 PH5ADJC1 PH5ADJC2 PH5ADJC3 Output Coarse phase adjust select for Output Divider EEPROM PH5ADJC4 PH5ADJC5 PH5ADJC6 OUT5DIVRSEL0 OUT5DIVRSEL1 OUT5DIVRSEL2 Output Divider ratio select OUT5DIVRSEL3 Output EEPROM (see Table OUT5DIVRSEL4 OUT5DIVRSEL5 OUT5DIVRSEL6 When set to the divider is disabled EN5DIV Output EEPROM When set to the divider is enabled PECL5HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CMOSMODE5PX LVCMOS mode select for OUTPUT Positive Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE5PY CMOSMODE5NX LVCMOS mode select for OUTPUT Negative Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE5NY RAM BITS OUTPUT TYPE OUTBUFSEL5X Output EEPROM LVPECL LVDS OUTBUFSEL5Y Output LVCMOS See Settings Above (1) EEPROM All Outputs Disabled (1) Use 22, 23, 24, and for setting the LVCMOS outputs Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register SPI Mode SPI RAM POWER UP BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT BIT CONDITION Address Address Address Address Feedback Frequency Detector is connected to the Lock Detector FB_FD_DESEL Feedback Frequency Detector is disconnected from the Lock Detector LOCK-DET EEPROM RESERVED Set to FB-Deterministic Clock divided by FBDETERM_DIV_SEL FB- Deterministic Clock divided by FB- FB-Deterministic-DIV2-Block in normal operation FBDETERM_DIV2_DIS Divider/Deterministi EEPROM FB-Deterministic-DIV2 reset (here REG6_RB c Blocks FB-Divider started with delay block (RC), normal operation FB_START_BYPASS FB-Divider can be started with external REF_SEL-signal (pin) All Output Dividers Output-Dividers started with delay block (RC), normal operation DET_START_BYPASS EEPROM Output-Dividers can be started with external NRESET-signal (pin) PH6ADJC0 Output PH6ADJC1 PH6ADJC2 PH6ADJC3 Coarse phase adjust select for Output Divider EEPROM PH6ADJC4 PH6ADJC5 PH6ADJC6 OUT6DIVRSEL0 OUT6DIVRSEL1 OUT6DIVRSEL2 Output Divider ratio select OUT6DIVRSEL3 Output EEPROM (see Table OUT6DIVRSEL4 OUT6DIVRSEL5 OUT6DIVRSEL6 When set to the divider is disabled EN6DIV Output EEPROM When set to the divider is enabled PECL6HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CMOSMODE6PX LVCMOS mode select for OUTPUT Positive Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE6PY CMOSMODE6NX LVCMOS mode select for OUTPUT Negative Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE6NY RAM BITS OUTPUT TYPE OUTBUFSEL6X Output EEPROM LVPECL LVDS OUTBUFSEL6Y Output LVCMOS See Settings Above (1) EEPROM All Outputs Disabled (1) Use 22,23,24, and for setting the LVCMOS outputs Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register SPI Mode SPI RAM POWER UP BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT BIT CONDITION Address Address Address Address LOCKW Lock-detect window Bit (Refer to Reg RAM Bits and EEPROM LOCKW Lock-detect window Bit (Refer to Reg RAM Bits and RESERVED Set to LOCK-DET LOCKC0 Number of coherent lock events Bit EEPROM LOCKC1 Number of coherent lock events Bit ADLOCK Selects Digital PLL_LOCK Selects Analog PLL_LOCK PH7ADJC0 PH7ADJC1 PH7ADJC2 PH7ADJC3 Output Coarse phase adjust select for Output Divider EEPROM PH7ADJC4 PH7ADJC5 PH7ADJC6 OUT7DIVRSEL0 OUT7DIVRSEL1 OUT7DIVRSEL2 Output Divider ratio select OUT7DIVRSEL3 Output EEPROM (see Table OUT7DIVRSEL4 OUT7DIVRSEL5 OUT7DIVRSEL6 When set to the divider is disabled EN7DIV Output EEPROM When set to the divider is enabled PECL7HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CMOSMODE7PX LVCMOS mode select for OUTPUT Positive Pin Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE7PY CMOSMODE7NX LVCMOS mode select for OUTPUT Negative Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE7NY RAM BITS OUTPUT TYPE OUTBUFSEL7X Output EEPROM LVPECL LVDS OUTBUFSEL7Y Output LVCMOS See Settings Above (1) EEPROM All Outputs Disabled (1) Use 22, 23, 24, and for setting the LVCMOS outputs Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register SPI Mode SPI RAM POWER UP BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT BIT CONDITION Address Address Address Address VCXOBUFSELX VCXO and AUX Input Buffer Type Select (LVPECL,LVDS or LVCMOS) XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin VCXOBUFSELY VCXO and AUX VCXOACDCSEL If Set to AC Termination, If set to DC Termination EEPROM Input Buffers VCXOHYSTEN If Set to Input Buffers Hysteresis enabled VCXOTERMSEL If Set to Input Buffer Internal Termination enabled VCXOINVBB VCXO Input Buffer If Set to It Biases VCXO Input negative pin with internal VCXOVBB Voltage EEPROM PH8ADJC0 PH8ADJC1 PH8ADJC2 PH8ADJC3 Output and Coarse phase adjust select for Output Divider EEPROM PH8ADJC4 PH8ADJC5 PH8ADJC6 OUT8DIVRSEL0 OUT8DIVRSEL1 OUT8DIVRSEL2 Output Divider ratio select OUT8DIVRSEL3 Output and EEPROM (see Table OUT8DIVRSEL4 OUT8DIVRSEL5 OUT8DIVRSEL6 When set to the divider is disabled EN89DIV Output and EEPROM When set to the divider is enabled PECL8HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CMOSMODE8PX LVCMOS mode select for OUTPUT Positive Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE8PY CMOSMODE8NX LVCMOS mode select for OUTPUT Negative Pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE8NY RAM BITS OUTPUT TYPE OUTBUFSEL8X Output EEPROM LVPECL LVDS OUTBUFSEL8Y Output LVCMOS See Settings Above (1) EEPROM All Outputs Disabled (1) Use 22, 23, 24, and for setting the LVCMOS outputs Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register SPI Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address Enables the Frequency Hold-Over (External Hold Over Function based on the HOLDF external circuitry) on off RESERVED HOLD 3-State Charge Pump (equal to HOLD pin function) HOLD function always activated (recommended for test purposes, only) HOLD-Over EEPROM Triggered by analog PLL Lock detect outputs HOLDTR If analog PLL Lock Signal is [1] (PLL locked), HOLD is activated If analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated HOLD_CNT0 HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by (HOLD_CNT0,HOLD_CNT1) X Number of Clock Cycles. HOLD_CNT1 For (00) X 64, (01) X 128, (10) X 256, (11) X 512 Clock Cycles LOCKW Extended Lock-detect window Bit (also refer to Reg RAM Bits and LOCK-DET EEPROM LOCKW Extended Lock-detect window Bit (also refer to Reg RAM Bits and When set to SPI/HOLD_INT and SPI/RESET_INT inverted (default) NOINV_RESHOL_INT Chip CORE EEPROM When set to SPI/HOLD_INT and SPI/RESET_INT not inverted When GTME this Bit has no functionality, But when GTME then: Diagnostic: PLL DIVSYNC_DIS When set to START-Signal is synchronized to N/M Divider Input Clocks EEPROM N/M Divider When set to START-Sync N/M Divider in PLL are bypassed Divider START When set to START-Signal is synchronized to VCXO-Clock START_BYPASS EEPROM DETERM-Block When set to START-Sync Block is bypassed Divider START When set to Sync Logic active when VCXO/AUX-Clocks are available INDET_BP EEPROM DETERM-Block When set to Sync Logic is independent from VCXO- and/or AUX-Clocks Divider START When set to Sync Logic waits for 1st PLL_LOCK state PLL_LOCK_BP EEPROM DETERM-Block When set to Sync Logic independent from 1st PLL_LOCK When set to Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD) Divider START LOW_FD_FB_EN When set to Sync Logic is started for VCXO/DIV_FB ~600KHz, stopped for EEPROM DETERM-Block VCXO/DIV_FB ~600KHz PLL When set to M-Divider uses NHOLD as NPRESET NPRESET_MDIV EEPROM M/FB-Divider When set to M-Divider NOT preseted by NHOLD BIAS_DIV_FB When BIAS_DIV_FB 1:0 Feedback 00, No current reduction for FB-Divider EEPROM Divider 01, Current reduction for FB-Divider by about 20% BIAS_DIV_FB 10, Current reduction for FB-Divider by about 30% BIAS_DIV89 When BIAS_DIV89 1:0 Output Divider 00, No current reduction for all output-rivider EEPROM and 01, Current reduction for all output-divider by about 20% BIAS_DIV89 10, Current reduction for all output-divider by about 30% AUXINVBB If set to it biases AUX Input Negative pin with internal VCXOVBB voltage. AUX Input EEPROM If set to AUX in Input Mode Buffer Is disabled. If set to it follows the behavior of Buffer DIS_AUX_Y9 FB_MUX_SEL and OUT_MUX_SEL bits settings. PECL9HISWING Output High output voltage swing in LVPECL Mode if set to EEPROM CMOSMODE9PX LVCMOS mode select for OUTPUT Positive pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE9PY CMOSMODE9NX LVCMOS mode select for OUTPUT Negative pin. Output EEPROM (X,Y) 00: Active, 10: Inverting, 11: Low, 01: 3-State CMOSMODE9NY RAM BITS OUTPUT TYPE OUTBUFSEL9X Output EEPROM LVPECL LVDS OUTBUFSEL9Y Output LVCMOS See Settings Above (1) EEPROM All Outputs Disabled (1) Use 22, 23, 24, and for setting the LVCMOS outputs Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register 10: SPI Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address Reference Divider M Bit Reference Divider M Bit Reference Divider M Bit Reference Divider M Bit Reference Divider M Bit Reference Divider M Bit Reference Reference Divider M Bit (PRI/SEC) Divider EEPROM Reference Divider M Bit M Reference Divider M Bit Reference Divider M Bit M10 Reference Divider M Bit M11 Reference Divider M Bit M12 Reference Divider M Bit M13 Reference Divider M Bit VCXO Divider N Bit VCXO Divider N Bit VCXO Divider N Bit VCXO Divider N Bit VCXO Divider N Bit VCXO Divider N Bit VCXO Divider N Bit VCXO/AUX/SEC EEPROM Divider N VCXO Divider N Bit VCXO Divider N Bit VCXO Divider N Bit N10 VCXO Divider N Bit N11 VCXO Divider N Bit N12 VCXO Divider N Bit N13 VCXO Divider N Bit Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register 11: SPI Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address PRI_DIV2 Input Buffers If set to enables Primary Reference Divide by EEPROM SEC_DIV2 Input Buffers If set to enables Secondary Reference Divide by EEPROM FB Path Integer When set to FB divider is active FB_DIS EEPROM Counter When set to FB divider is disabled FB Path Integer When set to FB clock is CMOS type (1) FB_CML_SEL EEPROM Counter When set to FB clock is CML type and uses CML2CMOS converter in PLL FB-Divider/ When set to Input clock for FB not inverted (normal mode, low speed) FB_INCLK_INV Deterministic EEPROM When set to Input clock for FB inverted (higher speed mode) Blocks FB_COUNT32_0 Feedback Counter Bit0 FB_COUNT32_1 Feedback Counter Bit1 FB_COUNT32_2 Feedback Counter Bit2 FB Path Integer FB_COUNT32_3 Feedback Counter Bit3 EEPROM Counter FB_COUNT32_4 Feedback Counter Bit4 FB_COUNT32_5 Feedback Counter Bit5 FB_COUNT32_6 Feedback Counter Bit6 FB_PHASE0 Feedback Phase Adjust Bit0 FB_PHASE1 Feedback Phase Adjust Bit1 FB_PHASE2 Feedback Phase Adjust Bit2 FB Path Integer FB_PHASE3 Feedback Phase Adjust Bit3 EEPROM Counter FB_PHASE4 Feedback Phase Adjust Bit4 FB_PHASE5 Feedback Phase Adjust Bit5 FB_PHASE6 Feedback Phase Adjust Bit6 If set to PLL is in normal mode PD_PLL PLL EEPROM If set to PLL is powered down When set to the VCXO Clock is selected for the Clock Tree and FB-Div and Clock Tree and FB_MUX_SEL Det Deterministic EEPROM See Table When set to the AUX Clock is selected for the Clock Tree and FB-Div and Block Det OUT_MUX_SEL Clock Tree If Set to it selects the VCXO Clock and if Set to it selects the AUX Clock EEPROM See Table Feed Back Path Selects FB/VCXO-Path when set to (TI Test-GTME) FB_SEL Diagnostics EEPROM The Secondary Reference clock input is selected when set to (TI Test-GTME) NRESHAPE1 Reshapes the Reference Clock Signal Disable Reshape EEPROM Reference If set to it enables short delay for fast operation Selection Control SEL_DEL1 EEPROM If Set to Long Delay recommended for Input References below 150Mhz RESET_HOLD Reset Circuitry If set to the RESET or HOLD pin acts as HOLD set to it acts as RESET EEPROM Read only. If EPLOCK reads a the EEPROM is unlocked. If EPLOCK reads a EPLOCK Status EEPROM then the EEPROM is locked. EPSTATUS Status EEPROM Status EEPROM (1) When Feedback Divider clock is set to CMOS type, only feedback divider values greater than are available. Table Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT Selection FB_MUX_SEL OUT_MUX_SEL PLL FEED AND OUTPUTS FEED AUX INPUT OR OUTPUT VCXO::PLL, VCXO::Y0 and Deterministic Block OUTPUT is enabled AUXIN::PLL, VCXO::Y0 and Deterministic Block AUX IN is enabled VCXO::PLL, AUXIN::Y0 and Deterministic Block AUX IN is enabled AUXIN::PLL, AUXIN::Y0 and Deterministic Block AUX IN is enabled Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register 12: SPI Mode (RAM only Register) SPI RAM RELATED POR BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK DEFAULT Address Address Address Address RESERVED RAM RESERVED RAM RESERVED RAM RESERVED RAM Status INDET_AUX It indicates that a clock is present at AUX-input (Y9) when set to RAM (Read Only) Status INDET_VCXO It indicates that a clock is present at VCXO-input when set to RAM (Read Only) Status PLL_LOCK It indicates that the PLL is locked when set to RAM (Read Only) PD Power Down Power-down mode on when set to Off when set to RAM If set to this bit forces RESET or HOLD depending on the setting of RESET or Reset RESET_HOLD bit in Register 11. If set to RESET or HOLD are asserted. RAM HOLD Set for for normal operation. General Test Mode Enable, Test Mode is only enabled, if this bit is set to GTME Diagnostics RAM This bit controls many test modes on the device. REVISION0 Status Read only: Revision Control Bit RAM REVISION1 Status Read only: Revision Control Bit RAM REVISION2 Status Read only: Revision Control Bit RAM When set to all blocks are on. (TI Test-GTME) When set to the VCXO Input, AUX Input and all output buffers and divider PD_IO Diagnostics RAM blocks are disabled. This test is done to measure the effect of the I/O circuitry on the Charge Pump. (TI Test-GTME) If set to that Status pin is used as CMOS output to enable TI test modes. SXOIREF Diagnostics Set to when IREFRES is set to and 12-K Ω resistor is connected. (TI RAM Test-GTME) SHOLD Diagnostics Routes the HOLD signal to the PLL_LOCK pin when set to (TI Test-GTME) RAM RESERVED RAM STATUS0 TI test registers. For TI use only STATUS1 Route internal signals to external STATUS pin. Diagnostics RAM STATUS3, STATUS2, STATUS1, STATUS0 (S3, S2, S1, S0) will select that STATUS2 internal status signal that will be routed to the external STATUS pin. STATUS3 TITSTCFG0 Diagnostics TI test registers. For TI use only RAM TITSTCFG1 Diagnostics TI test registers. For TI use only RAM TITSTCFG2 Diagnostics TI test registers. For TI use only RAM TITSTCFG3 Diagnostics TI test registers. For TI use only RAM PRIACTIVITY Status It indicates activity on the Primary when set to (read only bit) RAM SECACTIVITY Status It indicates activity on the Secondary when set to (read only bit) RAM RESERVED RAM NOTE: If TI test bits (Register RAM bits 17,18,19, are set to 1000, Reference Select from the Smart Mux will show on the STATUS pin High Primary REF is selected and Low Secondary REF is selected). When TI test bits are set to 0000 the Reference Clock Frequency Detector shows up on the STATUS pin. In this mode the STATUS pin goes high if a clock is detected and low if a clock is not detected. In this configuration Register Bit should be set to Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com The CDCE72010 has a complex multi stage output divider. The table below describes the setting of Bits 13:19 of Register to and the setting for the feedback divider bits 5:11 of register 11. The table below describes divider settings and the phase relation of the outputs with respect to divide by one clock. To calculate the phase relation between different dividers see Output Divider and Phase Adjust Section in this document. Table Output Dividers and Feedback Divide Settings and Phase Output FOR REGISTER TO RAM BITS {19[BIT6] TO DIVIDE BY 13[BIT0]} PHASE LAG FROM DIVIDE BY TOTAL FOR REGISTER RAM BITS {11[BIT6] TO 5[BIT0]} [Bit [Bit [Bit [Bit [Bit [Bit [Bit Cycle Degree 0.5 180 0.5 180 14.5 5220 7560 28.5 10260 12600 16.5 5940 8640 32.5 11700 14400 12' 18.5 6660 9720 36.5 13140 16200 16' 20.5 7380 24' 10800 40.5 14580 18000 20' 22.5 8100 30' 11880 40' 44.5 16020 19800 24' 24.5 8820 12960 48.5 17460 21600 26.5 9540 14040 52.5 18900 23400 32' 28.5 10260 48' 15120 56.5 20340 25200 Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

PLL_LOCK REF_SEL POWER□DOWN RESET HOLDor MODE_SEL AUX_SEL SPI_MISO SPI_LE□(CD1) SPI_CLK□(CD2) SPI_MOSI□(CD3) Interface &□Control RAM□Resistors PLL_LOCK REF_SEL POWER□DOWN RESET HOLDor MODE_SEL AUX_SEL CD1 CD2 CD3 EEPROM Interface &□Control RAM□Resistors CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 The CDCE72010 has two modes of operation, SPI Interface and Configuration Default Mode. The Configuration Default mode is selected when MODE_SELECT Pin is driven low and it is used where SPI interface is not available. In the CD Mode configuration, the SPI interface Pins become static control pins CD1, CD2, CD3 and AUX_SEL as shown in the Pin description. The CD Mode signals are sampled only at power up or after Power Down are asserted. In CD Mode BYPASS, CD1 and CD2 are used to switch between EEPROM saved configurations. -CD1 allows swapping Divider and Phase Adjust value between output couples. CD2 allows changing the output type for each output. AUX_SEL Controls the Output Mux between VCXO and AUX Input. CD3 must be grounded in CD Mode. Without any interface a single device with a single program can have multiple configurations that can be implemented on more than one socket. Figure 13. Writing to EEPROM via SPI Bus in Figure 14. Using CD1, CD2 to Control What is Copied Manufacutring, From EEPROM Into RAM Registers at Power Up 3rd Party Vendor or at TI Test Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address INBUFSELX Reference Input Primary and Secondary Buffer Type Select (LVPECL,LVDS or LVCMOS) EEPROM Buffers XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin INBUFSELY PRISEL When REFSELCNTRL is set to the following settings apply: If RAM Bit (2,3): no Input Buffer is selected/active Reference Input If RAM Bit (2,3): PRI_BUF is selected, SEC_BUF is powered down EEPROM Buffer SECSEL If RAM Bit (2,3): SEC_BUF is selected, PRI_BUF is powered down (1) If RAM Bit (2,3): Auto Select (PRI then SEC). When set to PRI- or SEC-Clocks are selected, depending on Bits and Divider START VCXOSEL (default) EEPROM DETERM-Block When set to VCXO/AUX-clock selected, overwrites Bits and Reference Select Control to select if the control of the reference is from the internal bit in Register RAM bits and or from the external select pin. When set to The external pin REF_SEL takes over the selection between Reference REFSELCNTRL PRI and SEC. Autoselect is not available. EEPROM Selection Control When set to The external pin REF_SEL is ignored. The Table in (Register and describes, which reference input clock is selected and available at (none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing diagram DELAY_PFD0 PFD PFD Pulse Width PFD Bit EEPROM DELAY_PFD1 PFD PFD Pulse Width PFD Bit EEPROM CP_MODE Selects option [0] or option [1] EEPROM Charge Pump Determines in which direction CP current will regulate (Reference Clock leads to CP_DIR EEPROM Feedback Clock; Positive CP output current [0]; Negative CP output current [1] Switches the current source in the Charge Pump on when set to (TI CP_SRC EEPROM Test-GTME) Diagnostics CP_SNK Switches the current sink in the Charge Pump on when set to (TI Test-GTME) EEPROM CP_OPA Switches the Charge Pump op-amp off when set to (TI Test-GTME) EEPROM CP_PRE Preset Charge Pump output voltage to V CC_CP /2, on [1], off [0] EEPROM ICP0 CP Current Setting Bit EEPROM ICP1 Charge Pump CP Current Setting Bit EEPROM ICP2 CP Current Setting Bit EEPROM ICP3 CP Current Setting Bit EEPROM RESERVED EEPROM RESERVED EEPROM Enables the 12k pull-down resistor at I_REF_CP Pin when set to (TI IREFRES Diagnostics EEPROM Test-GTME) PECL0HISWING Output High output voltage swing in LVPECL Mode if set to EEPROM RESERVED EEPROM RESERVED EEPROM OUTBUF0CD2LX Output Buffer Signaling Selection when CD2 In low CD2 Low EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF0CD2LY OUTBUF0CD2HX Output Buffer Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: output disable OUTBUF0CD2HY (1) This setting is only avaiable if the Register Bit is set to (Feedback Divider clock is set to CMOS type). Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address ACDCSEL Input Buffers If Set to AC Termination, If set to DC termination EEPROM HYSTEN Input Buffers If Set to Input Buffers Hysteresis enabled EEPROM TERMSEL Input Buffers If Set to Input Buffer Internal Termination enabled EEPROM PRIINVBB Input Buffers If Set to Primary Input Negative Pin biased with internal VBB voltage. EEPROM SECINVBB Input Buffers If Set to Secondary Input Negative Pin biased with internal VBB voltage EEPROM FAILSAFE Input Buffers If Set to Fail Safe is enabled for all input buffers. EEPROM PH1ADJC0 PH1ADJC1 PH1ADJC2 PH1ADJC3 Output and Coarse phase adjust select for output divider EEPROM PH1ADJC4 PH1ADJC5 PH1ADJC6 OUT1DIVRSEL0 OUT1DIVRSEL1 OUT1DIVRSEL2 OUTPUT DIVIDER Ratio Select OUT1DIVRSEL3 Output and EEPROM (See Table OUT1DIVRSEL4 OUT1DIVRSEL5 OUT1DIVRSEL6 When set to the divider is disabled EN01DIV Output and EEPROM When set to the divider is enabled PECL1HISWING Output High output voltage swing in LVPECL Mode if set to EEPROM CD1 PIN is high and DIVPHA1CD1H is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA1CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA1CD1H is set to high Loads Output Divider and Phase Adjust into OUTPUT CD1 PIN is low and DIVPHA1CD1L is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA1CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA1CD1L is set to high Loads Output Divider and Phase Adjust into OUTPUT OUTBUF1CD2LX EEPROM Output Buffer Signaling Selection when CD2 in low CD2 Low (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF1CD2LY OUTBUF1CD2HX EEPROM Output Buffer Signaling Selection when CD2 in high CD2 High (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF1CD2HY Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address DLYM0 Reference Phase Delay M Bit0 DLYM1 DELAY M Reference Phase Delay M Bit1 EEPROM DLYM2 Reference Phase Delay M Bit2 DLYN0 Feedback Phase Delay N Bit0 DLYN1 DELAY N Feedback Phase Delay N Bit1 EEPROM DLYN2 Feedback Phase Delay N Bit2 PH2ADJC0 PH2ADJC1 PH2ADJC2 PH2ADJC3 Output Coarse phase adjust select for output divider EEPROM PH2ADJC4 PH2ADJC5 PH2ADJC6 OUT2DIVRSEL0 OUT2DIVRSEL1 OUT2DIVRSEL2 OUTPUT DIVIDER Ratio Select OUT2DIVRSEL3 Output EEPROM (See Table OUT2DIVRSEL4 OUT2DIVRSEL5 OUT2DIVRSEL6 When set to the divider is disabled EN2DIV Output EEPROM When set to the divider is enabled PECL2HISWING Output High output voltage swing in LVPECL Mode if set to EEPROM CD1 PIN is high and DIVPHA2CD1H is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA2CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA2CD1H is set to high Loads Output Divider and Phase Adjust into OUTPUT CD1 PIN is low and DIVPHA2CD1L is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA2CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA2CD1L is set to high Loads Output Divider and Phase Adjust into OUTPUT OUTBUF2CD2LX Output Buffer Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF2CD2LY OUTBUF2CD2HX Output Buffer Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF2CD2HY Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address When set to the REF-clock frequency detector is ON DIS_FDET_REF PLL Freq. Detect EEPROM When set to it is switched OFF When set to the feedback path frequency detector is switched OFF DIS_FDET_FB Diagnostics EEPROM (TI Test-GTME) BIAS_DIV01 When BIAS_DIV01 1:0 EEPROM Output Divider 00, No current reduction for all output-divider and 01, Current reduction for all output-divider by about 20% BIAS_DIV01 EEPROM 10, Current reduction for all output-divider by about 30% BIAS_DIV23 When BIAS_DIV23 1:0 EEPROM Output Divider 00, No current reduction for all output-divider and 01, Current reduction for all output-divider by about 20% BIAS_DIV23 EEPROM 10, Current reduction for all output-divider by about 30% PH3ADJC0 PH3ADJC1 PH3ADJC2 PH3ADJC3 Output Coarse phase adjust select for output divider EEPROM PH3ADJC4 PH3ADJC5 PH3ADJC6 OUT3DIVRSEL0 OUT3DIVRSEL1 OUT3DIVRSEL2 OUTPUT DIVIDER Ratio Select OUT3DIVRSEL3 Output EEPROM (See Table OUT3DIVRSEL4 OUT3DIVRSEL5 OUT3DIVRSEL6 When set to the divider is disabled EN3DIV Output EEPROM When set to the divider is enabled PECL3HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CD1 PIN is high and DIVPHA3CD1H is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA3CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA3CD1H is set to high Loads Output Divider and Phase Adjust into OUTPUT CD1 PIN is Low and DIVPHA3CD1L is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA3CD1L CD1 Low EEPROM CD1 PIN is Low and DIVPHA3CD1L is set to high Loads Output Divider and Phase Adjust into OUTPUT OUTBUF3CD2LX Output Buffer Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) 01:LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF3CD2LY OUTBUF3CD2HX Output Buffer Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF3CD2HY Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address RESERVED EEPROM RESERVED EEPROM RESERVED EEPROM RESERVED EEPROM If set to it will 3-state the charge pump to act as a HOLD on Loss of Reference HOLDONLOR HOLD- Over EEPROM Clocks Primary and Secondary) RESERVED EEPROM PH4ADJC0 PH4ADJC1 PH4ADJC2 PH4ADJC3 Output Coarse phase adjust select for output divider EEPROM PH4ADJC4 PH4ADJC5 PH4ADJC6 OUT4DIVRSEL0 OUT4DIVRSEL1 OUT4DIVRSEL2 OUTPUT DIVIDER Ratio Select OUT4DIVRSEL3 Output EEPROM (See Table OUT4DIVRSEL4 OUT4DIVRSEL5 OUT4DIVRSEL6 When set to the divider is disabled EN4DIV Output EEPROM When set to the divider is enabled PECL4HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CD1 PIN is high and DIVPHA4CD1H is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA4CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA4CD1H is set to high Loads Output Divider and Phase Adjust into OUTPUT CD1 PIN is low and DIVPHA4CD1L is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA4CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA4CD1L is set to high Loads Output Divider and Phase Adjust into OUTPUT OUTBUF4CD2LX Output Buffer Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF4CD2LY OUTBUF4CD2HX Output Buffer Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF4CD2HY Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address BIAS_DIV45 When BIAS_DIV45 1:0 Output Divider 00, No current reduction for all output-divider EEPROM and 01, Current reduction for all output-divider by about 20% BIAS_DIV45 10, Current reduction for all output-divider by about 30% BIAS_DIV67 When BIAS_DIV67 1:0 Output Divider 00, No current reduction for all output-divider EEPROM and 01, Current reduction for all output-divider by about 20% BIAS_DIV67 10, Current reduction for all output-divider by about 30% RESERVED EEPROM RESERVED EEPROM PH5ADJC0 PH5ADJC1 PH5ADJC2 PH5ADJC3 Output Coarse phase adjust select for output divider EEPROM PH5ADJC4 PH5ADJC5 PH5ADJC6 OUT5DIVRSEL0 OUT5DIVRSEL1 OUT5DIVRSEL2 OUTPUT DIVIDER Ratio Select OUT5DIVRSEL3 Output EEPROM (See Table OUT5DIVRSEL4 OUT5DIVRSEL5 OUT5DIVRSEL6 When set to the divider is disabled EN5DIV Output EEPROM When set to the divider is enabled PECL5HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CD1 PIN is high and DIVPHA5CD1H is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA5CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA5CD1H is set to high Loads Output Divider and Phase Adjust into OUTPUT CD1 PIN is low and DIVPHA5CD1L is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA5CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA5CD1L is set to high Loads Output Divider and Phase Adjust into OUTPUT OUTBUF5CD2LX Output Buffer Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF5CD2LY OUTBUF5CD2HX Output Buffer Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF5CD2HY Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address Feedback Frequency Detector is connected to the Lock Detector FB_FD_DESEL Feedback Frequency Detector is disconnected from the Lock Detector LOCK-DET EEPROM RESERVED Set to FB-Deterministic Clock divided by FBDETERM_DIV_SEL FB- Deterministic Clock divided by FB-Divider FB-Deterministic-DIV2-Block in normal operation FBDETERM_DIV2_DIS Deterministic EEPROM FB-Deterministic-DIV2 reset (here REG6_RB Blocks FB-Divider started with delay block (RC), normal operation FB_START_BYPASS FB-Divider can be started with external REF_SEL-signal (pin) All Output Output-Dividers started with delay block (RC), normal operation DET_START_BYPASS EEPROM Dividers Output-Dividers can be started with external NRESET-signal (pin) PH6ADJC0 PH6ADJC1 PH6ADJC2 PH6ADJC3 Output Coarse phase adjust select for output divider EEPROM PH6ADJC4 PH6ADJC5 PH6ADJC6 OUT6DIVRSEL0 OUT6DIVRSEL1 OUT6DIVRSEL2 OUTPUT DIVIDER Ratio Select OUT6DIVRSEL3 Output EEPROM (See Table OUT6DIVRSEL4 OUT6DIVRSEL5 OUT6DIVRSEL6 When set to the divider is disabled EN6DIV Output EEPROM When set to the divider is enabled PECL6HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CD1 PIN is high and DIVPHA6CD1H is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA6CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA6CD1H is set to high Loads Output Divider and Phase Adjust into OUTPUT CD1 PIN is low and DIVPHA6CD1L is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA6CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA6CD1L is set to high Loads Output Divider and Phase Adjust into OUTPUT OUTBUF6CD2LX Output Buffer Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF6CD2LY OUTBUF6CD2HX Output Buffer Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF6CD2HY Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address LOCKW Lock-detect window bit (Refer to Reg RAM Bits and LOCKW Lock-detect window bit (Refer to Reg RAM Bits and RESERVED Set to LOCK-DET EEPROM LOCKC0 Number of coherent lock events bit LOCKC1 Number of coherent lock events bit ADLOCK Selects Digital PLL_LOCK ,Selects Analog PLL_LOCK PH7ADJC0 PH7ADJC1 PH7ADJC2 PH7ADJC3 Output Coarse phase adjust select for output divider EEPROM PH7ADJC4 PH7ADJC5 PH7ADJC6 OUT7DIVRSEL0 OUT7DIVRSEL1 OUT7DIVRSEL2 OUTPUT DIVIDER Ratio Select OUT7DIVRSEL3 Output EEPROM (See Table OUT7DIVRSEL4 OUT7DIVRSEL5 OUT7DIVRSEL6 When set to the divider is disabled EN7DIV Output EEPROM When set to the divider is enabled PECL7HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CD1 PIN is high and DIVPHA7CD1H is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA7CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA7CD1H is set to high Loads Output Divider and Phase Adjust into OUTPUT CD1 PIN is low and DIVPHA7CD1L is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA7CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA7CD1L is set to high Loads Output Divider and Phase Adjust into OUTPUT OUTBUF7CD2LX Output Buffer Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF7CD2LY OUTBUF7CD2HX Output Buffer Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF7CD2HY Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address VCXOBUFSELX VCXO and AUX Input Buffer Type Select (LVPECL,LVDS or LVCMOS) VCXOBUFSELY XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin VCXO and AUX VCXOACDCSEL Input Buffers If Set to AC Termination, If set to DC Termination EEPROM VCXO Input Buffer VCXOHYSTEN If Set to Input Buffers Hysteresis enabled VCXOTERMSEL If Set to Input Buffer Internal Termination enabled VCXOINVBB VCXO Input Buffer If Set to It biases VCXO Input negative pin with internal VCXOVBB voltage EEPROM PH8ADJC0 PH8ADJC1 PH8ADJC2 PH8ADJC3 Output and Coarse phase adjust select for output divider and EEPROM PH8ADJC4 PH8ADJC5 PH8ADJC6 OUT8DIVRSEL0 OUT8DIVRSEL1 OUT8DIVRSEL2 OUTPUT DIVIDER and Ratio Select OUT8DIVRSEL3 Output and EEPROM (See Table OUT8DIVRSEL4 OUT8DIVRSEL5 OUT8DIVRSEL6 When set to the divider is disabled EN89DIV Output and EEPROM When set to the divider is enabled PECL8HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM CD1 PIN is high and DIVPHA8CD1H is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA8CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA8CD1H is set to high Loads Output Divider and Phase Adjust into OUTPUT CD1 PIN is low and DIVPHA8CD1L is set to low Loads Output Divider and Phase Adjust into OUTPUT DIVPHA8CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA8CD1L is set to high Loads Output Divider and Phase Adjust into OUTPUT OUTBUF8CD2LX Output Buffer Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF8CD2LY OUTBUF8CD2HX Output Buffer Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF8CD2HY Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address HOLDF1 Enables the Frequency Hold-Over Function on off HOLDF2 Enables the Frequency Hold-Over Function on off HOLD 3-State Charge Pump (equal to HOLD -Pin function) HOLD function always activated (recommended for test purposes, only) HOLD- Over EEPROM Triggered by analog PLL Lock detect outputs HOLDTR If analog PLL Lock Signal is [1] (PLL locked), HOLD is activated If analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated HOLD_CNT0 HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by (HOLD_CNT0,HOLD_CNT1)::X= Number of Clock Cycles. HOLD_CNT1 For (00)::X=64, (01) ::X=128, (10)::X=256, (11)::X=512 Clock Cycles. LOCKW Extended Lock-detect window Bit (Also refer to Reg RAM Bits and LOCK-DET EEPROM LOCKW Extended Lock-detect window Bit (Also refer to Reg RAM Bits and NOINV_RESHOL_IN When set to SPI/HOLD_INT and SPI/RESET_INT inverted (default) Chip CORE EEPROM T When set to SPI/HOLD_INT and SPI/RESET_INT not inverted When GTME this bit has no functionality, But when GTME then: Diagnostic: PLL DIVSYNC_DIS When set to START-Signal is synchronized to N/M Divider Input Clocks EEPROM N/M Divider When set to START-Sync N/M Divider in PLL are bypassed Divider START When set to START-Signal is synchronized to VCXO-Clock START_BYPASS EEPROM DETERM-Block When set to START-Sync Block is bypassed Divider START When set to Sync Logic active when VCXO/AUX-Clocks are available INDET_BP EEPROM DETERM-Block When set to Sync Logic is independent from VCXO- and/or AUX-Clocks Divider START When set to Sync Logic waits for 1st PLL_LOCK state PLL_LOCK_BP EEPROM DETERM-Block When set to Sync Logic independent from 1st PLL_LOCK When set to Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD) Divider START LOW_FD_FB_EN When set to Sync Logic is started for VCXO/DIV_FB ~600KHz, EEPROM DETERM-Block stopped for VCXO/DIV_FB ~600KHz PLL When set to M-Divider uses NHOLD1 as NPRESET NPRESET_MDIV EEPROM M/FB-Divider When set to M-Divider NOT preseted by NHOLD1 BIAS_DIV_FB When BIAS_DIV_FB 1:0 Feedback 00, No current reduction for FB-Divider EEPROM Divider 01, Current reduction for FB-Divider by about 20% BIAS_DIV_FB 10, Current reduction for FB-Divider by about 30% BIAS_DIV89 When BIAS_DIV89 1:0 Output Divider 00, No current reduction for all output-divider EEPROM and 01, Current reduction for all output-divider by about 20% BIAS_DIV89 10, Current reduction for all output-divider by about 30% AUXINVBB If Set to it Biases AUX Input Negative Pin with internal VCXOVBB voltage. AUX Buffer EEPROM If Set to AUX in input Mode Buffer is disabled. If Set to it follows the DIS_AUX_Y9 behavior of FB_MUX_SEL and OUT_MUX_SEL bits settings. PECL9HISWING Output High Output Voltage Swing in LVPECL Mode if set to EEPROM RESERVED EEPROM RESERVED EEPROM OUTBUF9CD2LX Output Buffer Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF9CD2LY OUTBUF9CD2HX Output Buffer Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable OUTBUF9CD2HY Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com Register 10: CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address Reference Divider M bit Reference Divider M bit Reference Divider M bit Reference Divider M bit Reference Divider M bit Reference Divider M bit Reference Reference Divider M bit (PRI/SEC) EEPROM Reference Divider M bit Divider M Reference Divider M bit Reference Divider M bit M10 Reference Divider M bit M11 Reference Divider M bit M12 Reference Divider M bit M13 Reference Divider M bit VCXO Divider N bit VCXO Divider N bit VCXO Divider N bit VCXO Divider N bit VCXO Divider N bit VCXO Divider N Bit VCXO Divider N Bit VCXO/AUX/SEC EEPROM Divider N VCXO Divider N Bit VCXO Divider N Bit VCXO Divider N Bit N10 VCXO Divider N Bit N11 VCXO Divider N Bit N12 VCXO Divider N Bit N13 VCXO Divider N Bit Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Register11: CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION Address Address Address Address PRI_DIV2 Input Buffers If set to Enables Primary Reference Divide by EEPROM SEC_DIV2 Input Buffers If set to Enables Secondary Reference Divide by EEPROM FB Path Integer When set to FB divider is active FB_DIS EEPROM Counter When set to FB divider is disabled FB Path Integer When set to FB clock is CMOS type FB_CML_SEL EEPROM Counter When set to FB clock is CML type and uses CML2CMOS converter in PLL FB-Divider When set to Input clock for FB not inverted (normal mode, low speed) FB_INCLK_INV Deterministic EEPROM When set to Input clock for FB inverted (higher speed mode) Blocks FB_COUNT32_0 Feedback Counter Bit0 FB_COUNT32_1 Feedback Counter Bit1 FB_COUNT32_2 Feedback Counter Bit2 FB Path Integer FB_COUNT32_3 Counter Feedback Counter Bit3 EEPROM divider) FB_COUNT32_4 Feedback Counter Bit4 FB_COUNT32_5 Feedback Counter Bit5 FB_COUNT32_6 Feedback Counter Bit6 FB_PHASE0 Feedback Phase Adjust Bit0 FB_PHASE1 Feedback Phase Adjust Bit1 FB_PHASE2 Feedback Phase Adjust Bit2 FB Path Integer FB_PHASE3 Counter Feedback Phase Adjust Bit3 EEPROM Divider) FB_PHASE4 Feedback Phase Adjust Bit4 FB_PHASE5 Feedback Phase Adjust Bit5 FB_PHASE6 Feedback Phase Adjust Bit6 If set to PLL is in normal mode PD_PLL PLL EEPROM If set to PLL is powered down Clock Tree and FB_MUX_SEL When set to the VCXO Clock is selected for the Clock Tree and FB-Div/Det Deterministic EEPROM Table When set to the AUX Clock is selected for the Clock Tree and FB-Div/Det. Block OUT_MUX_SEL If Set to it selects the VCXO Clock and if Set to it selects the AUX Clock EEPROM Table Feed Back Path Selects FB/VCXO-Path when set to (TI Test-GTME) FB_SEL Diagnostics EEPROM The Secondary Reference clock input is selected when set to (TI Test-GTME) NRESHAPE1 Reshapes the Reference Clock Signal Disable Reshape Reference EEPROM If set to it enables short delay for fast operation Selection Control SEL_DEL1 If Set to Long Delay recommended for input references below 150Mhz. RESET_HOLD Reset Circuitry If set to the RESET or HOLD pin acts as HOLD set to it acts as RESET EEPROM Read only. If EPLOCK reads a the EEPROM is unlocked. If EPLOCK reads a EPLOCK Status EEPROM then the EEPROM is locked. EPSTATUS Status EEPROM Status EEPROM Table Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT Selection FB_MUX_SEL OUT_MUX_SEL PLL FEED AND OUTPUT FEED AUX INPUT OR OUTPUT VCXO::PLL, VCXO::Y0 and Deterministic Block OUTPUT is Enabled (1) AUXIN::PLL, VCXO::Y0 and Deterministic Block AUX IN is Enabled VCXO::PLL, AUXIN::Y0 and Deterministic Block AUX IN is Enabled AUXIN::PLL, AUXIN::Y0 and Deterministic Block AUX IN is Enabled (1) Default Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

INTERFACE, CONFIGURATION, AND CONTROL RAM□Registers EEPROM□Cells Interface□&□Control Control□Signals SPI UNIVERSAL INPUT AND REFERENCE CLOCK BUFFERS 50/c87 50/c87 PRI_REF Input 50/c87 VBB P N INV 50/c87 SEC_REF Input P N INV --External--L VDSONX11X11 1.2VInternalDCL VDSON001111 1.2VInternalACL VDSON001011 --External--LVPECLONX11X01 1.2VInternalDCLVPECLON001101 1.9VInternalACLVPECLON001001 --N/ADCL VCMOSONXX1X00 ConfigurationSettings OCC101X CCC001X OOOX1XX OOOXX00 INVNP1.31.20.10.0 Register / Bits Switch OCC101X CCC001X OOOX1XX OOOXX00 INVNP1.41.20.10.0 Register / Bits Switch PRI_REF & SEC_REF Input Buffer Settings PRI_REF Buffer Settings SEC_REF Buffer Settings CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com The CDCE72010 is designed to support various without. In the case where systems lack the SPI bus or a Boot up configuration is required at start up before the management layer is up the built in EEPROM is used to provide this function. The Interface bus takes the serialized address and data and writes to the specified RAM bits. The content of the RAM bits are connected to logical functions in the device. Changing the content of the RAM bits (high or low) instantly changes the logical functions inside the device. At power up or after power down is de-asserted the

contents

bits. After that the content of RAM can be changed via the SPI bus. When writing to EEPROM commands are detected on the SPI bus the control logic begins writing the content of the RAM bits into the corresponding EEPROM bits. This process takes about 50ms. During this time the power supply should be above 3.2V. The on-chip EEPROM can be operated in its unlocked or locked mode. An unlocked EEPROM indicates that the stored bit values can be changed on another EEPROM write sequence (available for up to a 100 EEPROM write sequences). A locked EEPROM indicates that the stored bit values cannot be changed on another EEPROM write sequence. Figure 15. Interface Control The CDCE72010 is designed to support what is referred to as a Universal Input Buffer structure. This type of buffer is designed to accept Differential or single ended inputs and it is sensitive enough to act as a LVPECL or LVDS in differential mode and LVCMOS in Single ended mode. With the proper external termination various types of inputs signals can be supported. Those inputs will be discussed in a separate document (application Notes). The CDCE72010 has two internal voltage biasing circuitries. One to set the termination voltage for references (PRI_REF and SEC_REF) and the second biasing circuitry is to set the termination voltage to the VCXO_IN and AUX_IN. This means that we can only have one type of differential signal on PRI_REF and SEC_REF and only one type of differential signal on VCXO_IN and AUX_IN. Figure 16. PRI_REF and SEC_REF Voltage Biasing Circuitry Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

--External--L VDSONX11X11 1.2VInternalDCL VDSON001111 1.2VInternalACL VDSON001011 --External--LVPECLONX11X01 1.2VInternalDCLVPECLON001101 1.9VInternalACLVPECLON001001 --N/ADCL VCMOSONXX1X00 ConfigurationSettings OCC101X CCC001X OOOX1XX OOOXX00 INVNP8.58.48.18.0 Register / Bits Switch VCXO & AUX Input Buffer Settings VCXO Input Buffer Settings AUTOMATIC/MANUAL REFERENCE CLOCK SWITCHING (SMART MUX) PRI_REF SEC_REF Internal Reference□Clock VCXO□With 100Hz□Loop Auto-Reference 1 2 1 2 3 4 primary secondary primary CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Figure 17. VCXO_IN and AUX_IN Voltage Biasing Circuitry The CDCE72010 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary clock input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected by the dedicated SPI register. In the manual mode the external REF_SEL signal selects one of the two input clocks In the automatic mode the primary clock is selected by default even if both clocks are available. In case the primary clock is not available or fails, then the input switches to the secondary clock until the primary clock is back. The figure below shows the automatic clock selection. Figure 18. Automatic Clock Select Timing In the automatic mode the frequencies of both clock signals has to be similar but may differ by up to 20%. There is no limitation placed on the phase relationship between the two inputs. The clock input circuitry is designed to suppress glitches during switching between the primary and secondary clock in the manual and automatic mode. This insures that the clock outputs continue to clock reliably when a transition from a clock input occurs. The phase of the output clock will slowly follow the new input phase. The speed of this transition is determined by the loop bandwidth. However, there is no phase build-out function supported (like in SONET/SDH applications). Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

(Register RAM Bits [7:6]) M□Divider□(14□Bits) Feedback□Divider Smart□Mux Feedback□Mux PFD□Out□to Charge□Pump P Divider Div□1,2 Div□1,2 PRI_REF SEC_REF R’ Divider Register□11:: Divide□Function□Register□11:: Phase□Function□Register□11:: 15 ::Register□10 ::Register□10 VCXO_IN AUX_IN M□Delay N□Delay Register□2 RAM□Bit□5:0 14 16 17 181312 87 9 10 1165 N□Divider□(14□Bits) 0 1 15 16 17 1814 87 9 10 1165 13 1232 410 2221 23 24 252019 2726 Maximum□Frequency□=□250□MHz Maximum□Frequency□=□250□MHz CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com The main function of the CDCE72010 device is to synchronize a Voltage Control Oscillator (VCO) or a Voltage Control Crystal Oscillator (VCXO) output to a reference clock input. The phase detector compares signals and outputs the difference between them. It is symbolized by an XOR. The compared signals are derived from the Reference clock and from the VCO/VCXO clocks. The Reference clock is divided by the R Divider or and M divider (14 Bits) and presented to the PFD. The VCO/VCXO clock is divided by the Feedback Divider P to 80) and the N Divider (14 Bits) and presented to the PFD. Frequency (VCXO_IN or AUX_IN) Frequency (PRI_REF or SEC_REF) (P*N)/(R*M) The PFD is a classical style with UP and DOWN signals generating flip-flops and a common reset path. Some special functions were implemented: Bit CP_DIR (register RAM bit can swap internally the REF- and FB-CLK inputs to the PFD flip-flops. The reset path can be typically delayed with the bits DELAY_PFD 1:0 (register RAM bit 7:6 from 1.5ns to 6.0ns. The PFD pulse width delay gets around the dead zone of the PFD transfer function and reduces phase noise and reference spurs. Table PFD Pulse Width Delay PFD1 PFD0 PFD PULSE WIDTH DELAY 1.5ns (1) 3.0ns 4.5ns 6.0ns (1) Default The PFD receives two clocks of the similar frequencies and decides if one is lagging or leading. This Lagging/Leading signals are feed to the Charge Pump. The Charge Pump in its turn takes the Lagging/Leading signals and translate them into current pulses that are feed to the external filter. The Output of the external filter is a DC level that controls the Voltage reference of the VCO/VCXO sitting outside and feeding the CDCE72010 at the VCXO Input. The VCO/VCXO drifts its outputs frequency with respect to the voltage applied to its Voltage Control pin. This is how the loop is closed. Figure 19. Phase Frequency Detection Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 Table 10. Feedback Divider Settings FEEDBACK DIVIDER SETTINGS (REGISTER 11: BITS) DIVIDER SETTING 12' 16' 24' 20' 30' 40' 24' 32' 48' Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

M AND N Delay Block in M/N Path CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com Table 11. Reference Delay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment (Register RAM Bits [5:0]) (1) DLYM2/DLYN2 DLYM1/DLYN1 DLYM0/DLYN0 PHASE OFFSET 0ps (2) 160ps 320ps 480ps 830ps 1130ps 1450ps 1750ps (1) If Progr Delay M is set, all Yx outputs are lagging to the Reference Clock according to the value set. If Progr Delay N is set, all Yx outputs are leading to the Reference Clock according to the value set. Above are typical values at V CC 3.3 T A PECL-output relate to Div4 mode. (2) Default Table 12. Reference Divider M/N 14-Bit (Register RAM Bits [13:0] for M and RAM Bits [27:14] for N13 N12 N11 N10 DIV BY (1) 128 (2) 16382 16383 16384 (1) If the divider value is then the code will be the binary value of 1). (2) Default Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 The Charge Pump drives the loop filter that controls the external VCO/VCXO. The Charge pump frequency is determined by the PFD frequency since the function of the charge pump is to translate the UP DOWN signals of the PFD into current pulses that drives the external filter. The Charge pump current is set by the control vector ICP [3:0]. The error amplifier operates from 0.7V to the V DD supply voltage. See the table below for ICP settings. Table 13. CP, Charge Pump Current (Register RAM Bits [17:14]) TYPICAL CHARGE PUMP ICP3 ICP2 ICP1 ICP0 CURRENT µ A (3-State) 200 µ A 400 µ A 600 µ A 800 µ A 1.0 mA 1.2 mA 1.4 mA 1.6 mA 1.8 mA 2.0 mA 2.2 mA (1) 2.4 mA 2.6 mA 2.8 mA 3.0 mA (1) Default The Preset Charge-Pump to V CC_CP is a useful feature to quickly set the center frequency of the VC(X)O after Power-up or Reset. The adequate control voltage for the VC(X)O will be provided to the Charge-Pump output by an internal voltage divider of Ω /1K Ω to V CC_CP and GND CC_CP /2). This feature helps to get the initial frequency accuracy, i.e. required at CPRI (Common Public Radio Interface) or OBSAI (Open Base Station Architecture Initiative). The Preset Charge-Pump to V CC_CP can be set and reset by SPI register. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

p . V(PFD2)□(Internal□Signal) V(PFD1)□(Internal□Signal) Charge□Pump□Output Current□Icp Charge□Pump□Output Current□Icp□(Inverted) Reference□Clock After the□N□Divider□and□Delay Reference□Clock After the□M□Divider□and□Delay PFD□pulse□width□delay□improves□spurious□suppression. CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com Charge-Pump Current Direction The direction of the charge-pump (CP) current pulse can be changed by the SPI register settings. It determines in which direction CP current will regulate (Reference Clock leads to Feedback Clock). Most (power-up condition) because of the use of a passive loop filter. The negative CP current is useful when using an active loop filter concept with inverting operational amplifier. The Figure below shows the internal PFD signal and the corresponding CP current. Figure 20. Charge Pump Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

t(lockdetect) Selected□REF□at□PFD (clock□fed□through□M□Divider and□M□Delay VCXO_IN□at□PFD (clock□fed□through□N□Divider and□N□Delay) CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 The CDCE72010 supports two PLL Lock indications: the digital lock signal or the analog lock signal. Both signals indicate logic high-level at PLL_LOCK if the PLL locks according the selected lock condition. The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and Feedback Clock (VCXO_IN clock) at the PFD (Phase Frequency Detect) are inside a predefined lock detect window for a pre-defined number of successive clock cycles. The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and Feedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window. Both, the lock detect window and the number of successive clock cycles are user definable in the SPI register settings. Figure 21. PLL Lock The lock detect window describes the maximum allowed time difference for lock detect between the rising edge of PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. The rising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lock detect window, if there is a phase displacement of more than +0.5*t (lockdetect) or -0.5*t (lockdetect) Table 14. Lock-Detect Window (Register RAM Bits [1:0] and Register RAM Bits [7:6]) LOCKW3 LOCKW2 LOCKW1 LOCKW0 PHASE-OFFSET AT PFD-INPUT (1) [7] [6] [1] [0] 1.5 ns 5.8 ns (2) 15.1 ns Reserved 3.4 ns 7.7 ns 17.0 ns Reserved 5.4 ns 9.7 ns 19.0 ns Reserved 15.0 ns 19.3 ns 28.6 ns Reserved (1) Typical values at V CC 3.3 T A C (2) Default Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

Power_Down Lock_Out Lock_In 160□k/c87 5pF PLL_LOCK Output V =□0.6□Vhigh CC V =□0.4□Vlow CC Lock t Digital□Lock□Detection Out-of-Lock VOut CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com Table 15. Number of Successive Lock Events Inside the Lock Detect Window (Register RAM Bits [4:3]) the PLL Lock Signal is Delayed for Number of FB_CLK Events NO. OF SUCCESSIVE LOCK LOCKC1 LOCKC0 EVENTS (1) 256 (1) Default When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out of lock until a stable lock is detected. A single low-to-high step can be reached with a wide lock detect window and high number of successive clock cycles. PLL_LOCK will return to out of lock if just one cycle is outside the lock detect window. Figure 22. Digital Lock Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

160□k/c87 5pF 110□µA (Lock) VCC C VOut t V =□0.55□Vhigh CC V =□0.35□Vlow CC Example: CC high Out CC Power_Down 110□µA (Out-of-Lock) Lock_Out Lock_In PLL_LOCK (Output) FREQUENCY HOLD-OVER MODE CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110 µ A current source until logic high-level is reached. Therefore, more time is needed to detect logic high level, but jittering of PLL_LOCK will be suppressed like possible in case of digital lock. The time PLL_LOCK needs to return to out of lock depends on the level of V OUT when the current source starts to unload the external capacitor. Figure 23. Analog Lock The HOLD-Function is a CDCE72010 feature that helps to improve system reliability. The HOLD-Function holds the output frequency in case the input reference clock fails or is disrupted. During HOLD, the Charge-Pump is switched off (3-State) freezing the last valid output frequency. The Hold-Function will be released after a valid reference clock is reapplied to the clock input and detected by the CDCE72010. For proper HOLD function, the Analog PLL-Lock-Detect mode has to be active. The following settings are involved with the HOLD Function: Lock Detect Window: Defines the window in ns inwhich the Lock is valid. The size is 3.5ns, 8.5ns, 18.5ns. Lock is set if Reference Clock and Feedback Clock are inside this predefined Lock-Detect Window for a pre-selected number of successive cycles. Out-of-Lock: Defines the out-of-lock condition: If the Reference Clock and the Feedback Clock at the PFD are outside the predefined Lock Detect Window. Number of Clock Cycles: Defines the number of successive PFD cycles which have to occur inside the lock window to set Lock detect. This does not apply for Out-of-Lock condition. Hold-Function: Selects HOLD-Function (see more details below). Hold-Trigger: Defines whether the HOLD-Function is always activated or whether it is dependent on the state of the analog PLL Lock detect output. In the latter case, HOLD is activated if Lock is set (high) and de-activated if Lock is reset (low). Analog PLL Lock Detect: Analog Lock output charges or discharges an external capacitor with every valid Lock cycle. The time constant for Lock detect can be set by the value of the capacitor. The CDCE72010 supports two types of HOLD functions, one external controllable HOLD mode and one internal mode, HOLD. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

Charge□Pump yes yes no PLL Out-of-Lock PLL-Lock Output□Set no 64□PFD Lock□Cycles Ref.□Clock is□Back no no Start PLL is□out-of-lock□if□the□phase difference□of Reference□Clock and Feedback□Clock at□PFD□are□outside□the predefined□Lock-Detect-Window□or□if□a Cycle-Slip□occurs. Frequency□Hold-Over□Function□works□in combination□with□the Analog□Lock -Detect Charge-Pump□is□switched□into 3-State. PLL has□to□be□in□LOCK□to□start HOLD-Function. (The Analog□Lock□output□is□not□reset□by□the□first□□Out-of- Lock□event. It□stays ‘High’ depending□on□the□analog□time delay (output□C-load). The□time□delay□must□be□long□enough to□guarantee□proper□HOLD□function ) The□Charge-Pump□remains□into 3-State until□the Reference□Clock is□back. The 1st valid Reference□Clock at□the□PFD□releases the□Charge-Pump. The□PLL acquire 64 lock□cycles□to□phase align□to□the□input□clock. CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com The Charge Pump can directly be switched into 3-State. This function is also available via SPI register. If logic low is applied to HOLD pin the Charge Pump will be switched to 3-State. After HOLD pin is released, the charge pump is switched back in to normal operation, with the next valid reference clock cycle at PRI_REF or SEC_REF and the next valid feedback clock cycle at the PFD. During HOLD all divider and all outputs are at normal operation. In Internal HOLD Function or HOLD-Over-Function the PLL has to be in lock to start the HOLD function. It switches the Charge Pump in to 3-State when an out-of-lock event occurs. It leaves the 3-State Charge Pump state when the Reference Clock is back. Then it starts a locking sequence of cycles before it goes back to the beginning of the HOLD-Over loop. Figure 24. Frequency Hold Over Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

Start□Divider (OUT#DIVSEL#) (PH#ADJC#) Output□Divider Coarse□Phase Adjust□Select Phase Adjust□Period CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 The CDCE72010 is designed with individual Output Dividers for Outputs to Output Divider drives Output and Output and Output Divider drives Output and Output Each output divider has a bypass function or it is referred to as divide by one Since divide by one bypasses the divider block it can address higher operating frequencies. The output divider is designed to address divide by 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 48, 50, 56, 60, 64, and 80.The output divider includes a coarse phase adjust that shifts the divided clock signal. The phase adjust resolution is a function of the divide function. The maximum number of phase steps equals to the divider setting. If the output is divide by then two phase adjustment settings and 180 degrees) are available. The resolution of phase adjustment is related to the output divider setting by the following: Phase adjust resolution (1/Output Divider settings) X 360 Degrees. Example: For a 491.52MHz VCXO where one of the outputs of the device is set to divide by for a 30.72MHz desired output, this will mean that the 30.72MHz clock will have (1/16) X 360 22.5 Degrees of phase adjustment resolution. Output Divide Select (OUT#DIVSEL#) and Coarse Phase Adjust Select (PH#ADJC#) registers are located in Register thought for Output thought respectively. The Phase difference between divider settings on different output can be calculated using the following formula and referring to the Phase Lag number in the Output Divider Table see Table Integer Remainder of [(Phase Lag X Phase Lag Y)/ Divide X as an example if we need to calculate the phase difference between divide by and divide by with respect to divide by clock. The Integer Remainder [(28.5 0.5)/4] This means there is Cycle phase delay between Divide by and Divide by with respect to Divide by Clock. If we need to do the same calculation with respect to Divide by we will have Intger Remainder [(28.5 0.5)/8] 0.5 that means that there is 0.5 Cycles between Divide by and divide by with respect to a divide by clock. Figure 25. Maximum Output Frequency With Phase Alighment For a complete listing of the coarse phase adjust settings, refer to the "CDCE72010 Coarse Phase Adjust" document. Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

Only□two□capacitors□are□illustrated. Top□Side□Thermal□PAD□Layout Bottom□Side□Thermal□PAD□Layout Only□two□capacitors□are□illustrated. CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com The CDCE72010 is a high performance device packaged in a QFN-64. The die has all the ground pins bounded to the thermal PAD on the bottom of the package. Therefore it is essential that the connection from the thermal PAD to the ground layers should be low impedance. In addition, the thermal path in a QFN package is via the thermal PAD on the bottom of the package. Therefore, the layout of the PAD is very important and it will affect the thermal performance as well as the overall performance of the device. The illustration shown provides optimal performance in terms of thermal issues, inductance and power supply bypassing. The X Filled VIA pattern recommended allows for a low inductance connection between the thermal ground pad and the ground plane of the board. This pattern forms a low thermal resistive path for the heat generated by the die to get dissipated through the ground plane and to the exposed bottom side ground pad. It is recommended that solder mask not be used on this bottom side pad to maximize its effectiveness as a thermal heat sink. The recommended layout drives the thermal conductivity to 22.8 C/W in still air and 13.8 C/W in a 100LFM air flow if implemented on a JEDEC compliant test thermal board. Figure 26. Device Layout Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

Power□(W) 100 125 0 1 2 3 4 Power□(W) Die□Temp□(C) JEDEC□0□LFM□25□C JEDEC□100□LFM□25□C RL 0□LFM□25□C RL 100□LFM□25□C JEDEC□0□LFM□85□C JEDEC□100□LFM□85□C RL 0□LFM□85□C RL 100□LFM□85□C Max□Die□Temp CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 The CDCE72010 is designed as a high performance device, therefore careful attention must be paid to device configuration with respect to power consumption. Total power consumption of the device can be estimated by adding up the total power consumed by each block in the device. The Table below describes the blocks used and power consumed per block. The total power of the device can be calculated by multiplying the number of blocks used by the power consumption per block. Table 16. Device Power INTERNAL BLOCK POWER AT 3.3V (Typ) POWER DISSIPATED BLOCK NUMBER OF BLOCKS DEVICE PLL Core and Input and Feedback Circuitries 530mW Output Dividers 180mW Output Buffers LVPECL-HISWING) (1) 150mW Output Buffers (LVDS-HISWING) (1) 75mW Output Buffers (LVCMOS at 122 MHz) (1) 50mW (1) Output buffers can be a total of LVDS, LVPECL, or LVCMOS. Figure 27. Die Temperature Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

Clock□Out VccCP CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com The CDCE72010 is designed to control an external Voltage Controlled Oscillator (VCO) or a Voltage Controlled Crystal Oscillator (VCXO) and to synchronize the controlled oscillators to the input reference. Controlling the Oscillator happens via a DC voltage that is applied to the Voltage control pin. This DC voltage is generated by the CDCE72010 in the form of AC pulses that get filtered by the external loop filter. Figure 28. Loop Filter Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

Register□(0□to□9) RAM□Bits:: 21 22 23 24 25 26 27 CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 The CDCE72010 is designed to drive three types of clock signaling, LVPECL, LVDS, and LVCMOS from each of the ten outputs. This super buffer that contains all three drivers is refered to as the Universal Output Buffer. Only one driver can be enabled at one time. Each universal output buffer is made from four independent buffers in parallel. When LVPECL mode is selected, only the LVPECL Buffer is enabled and the rest of the buffers are 3-stated and in low power mode. When Selecting LVDS, only the LVDS Buffer is enabled and the rest of the buffers are 3-stated and in low power mode. When LVCMOS mode is selected, both LVCMOS drivers are enabled. One LVCMOS buffer drives the negative side and the other buffer drives the positive pin. The LVCMOS drivers are driven from the same output divider but have separate control bits. In SPI Mode, bits 22, 23, 24, and of Registers to are used to put the LVCMOS buffer in active, inverting, low, or 3-state. In CD Mode, those bits are used for different functions and the LVCMOS buffer can be active when selected or 3-state when their not. Figure 29. Universal Output Buffer Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

REG0<Bit4> VCXOSEL DET_ST ART_BYP ASSREG6<Bit2> FB_DETERM_DIV_SEL “0” Feedback Divider Clock “1” Divide by 2 Feedback Clock Any of the Conditions will Produce a Conditional SYNC Start Signal: 1- REG9 <Bit11> INDET_BP is set to “0” & VCXO or AUX_CLK is avai lable 2- REG9<Bit12> PLL_LOCK_BP is set to “0” & we have 1 st Lock State 3- REG1 1<Bit19> PD_PLL is set to “0”& the PLL is ON 4- REG9<Bit13> LOW_FD_FB_EN is set to “1” N Divider Input Fre quency above 600KHz 5- Write Activity to the Output Divider (s) 6- REG12<Bit8> Set to 1 ( /RESET Bit is Set to “1”) 7- REG12<Bit7> Set to 1 ( /Power Down Bit is Set to “1”) /RESET Pin ST ARTBYPASS Feedback Clock “0” “1” OUTPUT DIVIDERS SYNC SIGNAL Synchronizing Output Divider SYNC Signal If the value of the bits described as inverted the function associated with it will be ignored with respect to the sync start signal generation. CDCE72010 SCAS858A JUNE 2008 REVISED JULY 2009 www.ti.com The CDCE72010 is a output clock device with output dividers and to insure that all the outputs are synchronous a synchronization startup circuitry is used. The synchronization circuitry generates a pulse to reset all the dividers in a way, that a predictable synchronous output is generated. The Synchronization signal can be generated from different sources and can be synchronized to a specific clock. The Block diagram below illustrates the signal path of the Output Divider Sync Signal. This function is assured up to 500 MHz. NOTE: The minimum frequency required for the output synchronization block to work properly is MHz. Figure 30. Output Divider Synchronization Block Diagram Submit Documentation Feedback Copyright 2008 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

RESET, POWER DOWN MODE AND RESET OR HOLD POR VCC PD□or Sleep Reset or Hold Reset□SPI□Interface□and□Register□12□to□Default Power All□Clocking□Circuitry□Down -□Shut□Down All Analog□Circuitry□(/PD□=□0□or□Sleep□=□0) -□Shut□Down All□Digital□Circuitry□(/PD□=□0□or□Sleep□=□0) -□Disable All□Output□Buffers□(/PD□=□0□or□Sleep□=□0) -□Load□EEPROM□Into□RAM□When□Released□(at□Rising□Edge□of□/PD) Reset□Digital□Circuitry -□Disable All□Output□Buffers□(When□/RESET□=□0) -□Reset□PLL (Load□With□RAM□Content□Values□at□Rising□Edge) -□Reset□Output□Dividers□and□Phase Adjust□Circuitry□(at□Rising□Edge) When□Hold□Function□Is Asserted -□Tri-state□the□Charge□Pump□Output□When□/HOLD□=□0 Hold□Function□Is□Deasserted□When -□/HOLD□=□1□and□We□Have□Valid□Reference□Clock Reset Hold /PD /Reset_Hold REG12: REG11: REG4: (Force□Sleep/PD□and□/RESET□or□/HOLD) Loss□of□Reference Sleep CDCE72010 www.ti.com SCAS858A JUNE 2008 REVISED JULY 2009 The CDCE72010 is designed to address various clock synchronization applications. Some functions can be set to be in automatic and manual mode or some functions can be controlled by software or by the internal circuitry. Figure below explains the various functionalities of power up reset internal circuitry functionality, power down functionality and reset functionality. The hold function shares the same block with Reset and one bit in the EEPROM will select either function. Figure 31. Powerup, Reset, and Powerdown Block Diagram Copyright 2008 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE72010

www.ti.com REVISION HISTORY Changes from Original (June 2008) to Revision A Page Changed Frequency equation result from (R*M)/(P*N) to (P*N)/(R*M) Added table note to Table Added table note to Register SPI Mode table 12: SPI Mode (RAM only Register) Note Added table note to Register 0:CD Mode table INTERFACE, CONFIGURATION, AND CONTROL P to PHASE FREQUENCY DETECTOR feedback divider (R*M)/(P*N) to (P*N)/(R*M) Deleted P is the product of X Divider and FB Divider R and X Divider is set to be divide by or Changed Figure by adding maximum frequency 250 MHz Added note to Output Dividers Synchronization 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCE72010RGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCE72010RGCRG4 ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCE72010RGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCE72010RGCTG4 ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 10-Jul-2009 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2009 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCE72010RGCR VQFN RGC 64 2000 333.2 345.9 28.6 CDCE72010RGCT VQFN RGC 64 250 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2009 Pack Materials-Page 2

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DLP® Products www.dlp.com Communications and www.ti.com/communications Telecom DSP dsp.ti.com Computers and www.ti.com/computers Peripherals Clocks and Timers www.ti.com/clocks Consumer Electronics www.ti.com/consumer-apps Interface interface.ti.com Energy www.ti.com/energy Logic logic.ti.com Industrial www.ti.com/industrial Power Mgmt power.ti.com Medical www.ti.com/medical Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Space, Avionics & www.ti.com/space-avionics-defense Defense RF/IF and ZigBee® Solutionswww.ti.com/lprf Video and Imaging www.ti.com/video Wireless www.ti.com/wireless-apps Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2010, Texas Instruments Incorporated