CDCE62005RGZR

CDCE62005 TI | Alldatasheet

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FEATURES

APPLICATIONS

www.ti.com SCAS862 NOVEMBER 2008 Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs Frequency Synthesizer With PLL/VCO and Flexible Inputs With Innovative Smart Partially Integrated Loop Filter. Multiplexer Feature: Fully Configurable Outputs Including Two Universal Differential Inputs Accept Frequency, Output Format, and Output Skew. Frequencies up to 1500 MHz (LVPECL), 800 MHz (LVDS), or 250 MHz (LVCMOS). Smart Input Multiplexer Automatically Switches Between One of Three Reference One Auxiliary Input Accepts Single Ended Inputs. Clock Source or Crystal. Auxiliary Input Accepts Crystals in the Range of MHz Multiple Operational Modes Include Clock MHz or an LVCMOS Input up to MHz. Generation via Crystal, SERDES Startup Mode, Jitter Cleaning, and Oscillator Holdover Mode Clock Generator Mode Using Crystal Input. Integrated EEPROM Determines Device Smart Input Multiplexer can be Configured Configuration at Power-up to Automatically Switch Between Highest Priority Clock Source Available Allowing Excellent Jitter Performance for Fail-safe Operation and Holdover Integrated Frequency Synthesizer including Modes. PLL, Multiple VCOs, and Loop Filter: Typical Power Consumption 1.7W Full Programmability Facilitates Phase (See Table at 3.3V Noise Performance Optimization Enabling Integrated EEPROM Stores Default Settings; Jitter Cleaner Mode. Therefore, The Device Can Power up in a Programmable Charge Pump Gain and Known, Predefined State. Loop Filter Settings Offered in QFN-48 Package Unique Dual-VCO Architecture Supports a ESD Protection Exceeds 2kV HBM Wide Tuning Range 1.750 GHz 2.356 GHz Industrial Temperature Range C to C Universal Output Blocks Support up to Differential, Single-ended, or Combinations of Differential or Single-ended: Data Converter and Data Aggregation Clocking ps RMS (10 kHz to MHz) Output Jitter Wireless Infrastructure Performance Switches and Routers Low Output Phase Noise: 130 dBc/Hz at Medical Electronics MHz offset, F c 491.52 MHz Military and Aerospace Output Frequency Ranges from 4.25 MHz to Industrial 1.175 GHz in Synthesizer Mode Clock Generation and Jitter Cleaning Output Frequency up to 1.5 GHz in Fan-out Mode LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes Independent Output Dividers Support Divide Ratios from (1) Independent Coarse Skew Control on all Outputs (1) Non-continuous values supported. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DESCRIPTION

SerDes Cleaned□Clock Data DSP CDCE62005Recovered□Clock DSP Clock ADC□Clock ADC□Clock DAC□Clock DEVICE INFORMATION CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under ps RMS (1) It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 800 kHz to 1.5 GHz (2) and skew relationship via a programmable delay block. If all outputs are configured in single-ended mode (e.g., LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies up to 500 MHz and an auxiliary single ended input that can be connected to a CMOS level clock or configured to connect to an external crystal via an on board oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available. Figure CDCE62005 Application Example (1) kHz to MHz integration bandwidth. (2) Frequency range depends on operational mode and output format selected. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

www.ti.com SCAS862 NOVEMBER 2008 The CDCE62005 is packaged in a 48-Pin Plastic Quad Flatpack Package with enhanced bottom thermal pad for heat dissipation. The Texas Instruments Package Designator is: RGZ (S-PQFP-N48) Figure 48-Pin QFN Package Outline PIN FUNCTIONS PIN TYPE VCC_OUT 11, Power 3.3V Supply for the Output Buffers 18, 21, 26, 29, VCC_AUXOUT Power 3.3V to Power the AUX_OUT circuitry VCC1_PLL Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required) VCC2_PLL 39, Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required) VCC_VCO 34, Power 3.3V VCO Input Buffer and Circuitry Supply Voltage. (Filter Required) VCC_IN_PRI Power 3.3V References Input Buffer and Circuitry Supply Voltage. VCC_IN_SEC Power 3.3V References Input Buffer and Circuitry Supply Voltage. VCC_AUXIN Power 3.3V Crystal Oscillator Input Circuitry. GND_VCO Ground Ground that connects to VCO Ground. (VCO_GND is shorted to GND) GND PAD Ground Ground is on Thermal PAD. See Layout recommendation SPI_MISO OD In SPI Mode it is an Open Drain Output and it functions as a Master In Slave Out as a serial Control Data Output to CDCE62005 SPI_LE I LVCMOS input, control Latch Enable for Serial Programmable Interface (SPI), with Hysteresis in SPI Mode. The input has an internal 150-k Ω pull-up resistor if left unconnected it will default to logic level SPI_CLK I LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. The input has an internal 150-k Ω pull-up resistor if left unconnected it will default to logic level SPI_MOSI I LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62005 for the SPI bus interface. The input has an internal 150-k Ω pull-up resistor if left unconnected it will default to logic level TEST_MODE I This pin should be tied high or left unconnected. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com PIN FUNCTIONS (continued) PIN TYPE REF_SEL I If Auto Reference Select Mode is OFF this Pin acts as External Input Reference Select Pin; The REF_SEL signal selects one of the two input clocks: REF_SEL [1]: PRI_IN is selected; REF_SEL [0]: SEC_IN is selected; The input has an internal 150-k Ω pull-up resistor if left unconnected it will default to logic level If Auto Reference Select Mode in ON this Pin not used. Power_Down I Active Low. Power down mode can be activated via this pin. See Table for more details. The input has an internal 150-k Ω pull-up resistor if left unconnected it will default to logic level SPI_LE has to be HIGH in order for the rising edge of Power_Down signal to load the EEPROM. SYNC I Active Low. Sync mode can be activated via this pin. See Table for more details. The input has an internal 150-k Ω pull-up resistor if left unconnected it will default to logic level AUX IN I Auxiliary Input is a single ended input including an on-board oscillator circuit so that a crystal may be connected. AUX OUT O Auxiliary Output LVCMOS level that can be programmed via SPI interface to be driven by Output or Output PRI REF+ I Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference Clock, PRI REF I Universal Input Buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In case of LVCMOS signaling Ground this pin. SEC REF+ I Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary Reference Clock, SEC REF I Universal Input Buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock. In case of LVCMOS signaling Ground this pin. TESTOUTA Analog Analog Test Point for Use for TI Internal Testing. Pull Down to GND Via a Ω s Resistor. REG_CAP1 Analog Capacitor for the internal Regulator. Connect to a 10uF Capacitor (Y5V) REG_CAP2 Analog Capacitor for the internal Regulator. Connect to a 10uF Capacitor (Y5V) VBB Analog Capacitor for the internal termination Voltage. Connect to a 1uF Capacitor (Y5V) EXT_LFP Analog External Loop Filter Input Positive EXT_LFN Analog External Loop Filter Input Negative. PLL_LOCK AI/O Output that indicates PLL Lock Status. See Figure U0P:U0N 27, O The Main outputs of CDCE62005 are user definable and can be any combination of up to LVPECL outputs, LVDS outputs or up to LVCMOS outputs. The outputs are selectable via U1P:U1N: 19, SPI interface. The power-up setting is EEPROM configurable. U2P:U2N 16,17 U3P:U3N U4P:U4N Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Divider□□0 U0P U0N U1P U1N U2P U2N U3P U3N U4P U4N PFD□/ CP /1:/2:HiZ /1:/2:HiZ Prescaler Feedback Divder Input Divider Reference Divider AUX OUT PRI_IN SEC_IN XTAL / AUX_IN EEPROM Interface Control REF_SELECT /Power_down /SYNC SPI_LE SPI_CLK SPI_MISO SPI_MOSI EXT_LFP EXT_LFN Output Divider□□1 Output Divider□□2 Output Divider□□3 Output Divider□□4 CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Figure CDCE62005 Block Diagram The CDCE62005 comprises of four primary blocks: the interface and control block, the input block, the output block, and the synthesizer block. In order to determine which settings are appropriate for any specific combination of input/output frequencies, a basic understanding of these blocks is required. The interface and control block determines the state of the CDCE62005 at power-up based on the

contents

EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE62005 by writing directly to the device registers after power-up. The input block selects which of the three input ports is available for use by the synthesizer block and buffers all clock inputs. The output block provides five separate clock channels that are fully programmable and configurable to select and condition one of four internal clock sources. The synthesizer block multiplies and filters the input clock selected by the input block. NOTE: This Section of the data sheet provides a high-level capabilities. For a complete I/O, please refer to the Device Configuration Section. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

REF_SELECT /Power_Down /SYNC EEPROM□(Default□Configuration) Device HardwareSPI_LE SPI_CLK SPI_MISO SPI_MOSI Register□0 Static□RAM□(Device□Registers) Register□1 Register□2 Register□3 Register□4 Register□5 Register□6 Register□7 Register□8 Register□0 Register□1 Register□2 Register□3 Register□4 Register□5 Register□6 Register□7 CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com The CDCE62005 is a highly flexible and configurable architecture and as such contains a number of registers so that the user may specify device operation. The times. On power-up, the CDCE62005 copies the EEPROM. Systems that do not have a host system to communicate with the CDCE62005 use this method for device configuration. The CDCE62005 provides the ability to lock the EEPROM; enabling the designer to implement a fault tolerant design. After power-up, the host system may overwrite the (Serial Peripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62005 during system operation. Finally, the device offers the ability to copy the EEPROM, if the EEPROM is unlocked. Figure CDCE62005 Interface and Control Block Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

/1:/2:HiZ /1:/2:HiZ Reference□Divider /1□-□/8 PRI_IN SEC_IN XTAL/ AUX_IN 1500□MHz LVPECL:□1500□MHz LVDS:□800□MHz LVCMOS:□250□MHz 1500□MHz Smart MUX1 Smart MUX2 Smart□MUX ControlREF_SEL Internal□Clock□Distribution□Bus CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 The Input Block includes a pair of Universal Input Buffers and an Auxiliary Input. The Input Block buffers the incoming signals and facilitates signal routing to the Internal Clock Distribution bus and the Synthesizer Block via the smart multiplexer (called the Smart MUX). The Internal Clock Distribution Bus connects to all output blocks discussed in the next section. Therefore, a clock signal present on the Internal Clock Distribution bus can appear on any or all of the device outputs. The CDCE62005 routes the PRI_IN and SEC_IN inputs directly to the Internal Clock Distribution Bus. Additionally, it can divide these signals via the dividers present on the inputs and output of the first stage of the Smart MUX. Figure CDCE62005 Input Block Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

/1,2,3,4,5 UxP UxN /1 - /8 /2 Digital□Phase Adjust (7-bits )PRI_IN SEC_IN SMART_MUX SYNTH Sync Pulse Enable LVDSClock□Divider□Module□0□-□4 LVPECL Output MUX Control Output□Buffer□Control Internal□Clock□Distribution□Bus Digital□Phase Adjust□□(7-bits) Sync□Pulse (internally□generated) EnableFrom Output MUX To Output Buffer CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Each of the five identical output blocks incorporates an output multiplexer, a clock divider module, and a universal output array as shown. Figure CDCE62005 Output Block of Clock Divider Module The following shows a simplified version of a Clock Divider Module (CDM). If an individual clock output channel is not used, then the user should disable the CDM and Output Buffer for the unused channel to save device power. Each channel includes two 7-bit registers to control the divide ratio used and the clock phase for each output. The output divider supports divide ratios from divide by (bypass the divider) to divide by 80; the divider does not support all integer values between and 80. Refer to Table for a complete list of divide ratios supported. Figure CDCE62005 Output Divider Module of Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

/2,/3,/4,/5 Input□Divider /1□-□/256 Internal Clock Distribution Bus SMART_MUX SYNTH Internal Clock Distribution Bus 50 kHz – 400 kHz /8□-□/1280 Feedback□Divider

1.750 GHz –

2.356 GHz

Feedback□Divider Feedback□Bypass□Divider CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Figure presents a high-level overview of the Synthesizer Block on the CDCE62005. Figure CDCE62005 Synthesizer Block Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Divider□0 U0P U0N Output Divider□1 U1P U1N Output Divider□2 U2P U2N Output Divider□3 U3P U3N Output Divider□4 U4P U4N PFD/ CP /1:/2:HiZ Prescaler Feedback Divider Input Divider Reference Divider AUX OUT FIN EXT_LFP EXT_LFN F R I P O FOUT /1:/2:HiZ /c61 /c180 /c180 /c180OUT IN FF F R I O (1) /c61 /c180 IN COMP FF R I (2) CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Figure presents the block diagram of the CDCE62005 in synthesizer mode highlighting the clock path for a single output. It also identifies the following regions containing dividers comprising the complete clock path Includes the cumulative divider values of all dividers included from the Input Ports to the output of the Smart Multiplexer (see Input Block for more details) The output divider value (see Output Block for more details) The input divider value (see Synthesizer Block for more details) The Prescaler divider value (see Synthesizer Block of more details) The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for more details) Figure CDCE62005 Clock Path Synthesizer Mode With respect to Figure any output frequency generated by the CDCE62005 relates to the input frequency connected to the Synthesizer Block by Equation Equation holds true when subject to the following constraints: 1.750 Ghz O x P x F OUT 2.356 GHz And the comparison frequency F COMP kHz F COMP MHz Where: Note: This device cannot output the frequencies between 780 MHz to 880 MHz Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

www.ti.com SCAS862 NOVEMBER 2008 over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT V CC Supply voltage range (2) -0.5 to 4.6 V V I Input voltage range (3) 0.5 to VCC 0.5 V V O Output voltage range (3) 0.5 to VCC 0.5 V Input Current I V I V CC mA Output current for LVPECL/LVCMOS Outputs V O V CC mA T J Maximum junction temperature 125 C T stg Storage temperature range to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) All supply voltages have to be supplied simultaneously. (3) The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Package Thermal Resistance for QFN (RGZ) Package (1) (2) AIRFLOW (lfm) θ JP C/W) (3) θ JA C/W) JEDEC Compliant Board (6X6 VIAs on PAD) 28.9 100 JEDEC Compliant Board (6X6 VIAs on PAD) 20.4 Recommended Layout (7X7 VIAs on PAD) 27.3 100 Recommended Layout (7X7 VIAs on PAD) 20.3 (1) The package thermal impedance is calculated in accordance with JESD and JEDEC2S2P (high-k board). (2) Connected to GND with thermal vias (0,3 mm diameter). (3) θ JP (Junction Pad) is used for the QFN Package, because the main heat flow is from the Junction to the GND-Pad of the QFN. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY V CC Supply voltage 3.3 3.6 V V CC_PLL V CC_IN Analog supply voltage 3.3 3.6 V CC_VCO V CCA P LVPECL REF at 30.72,MHz, Outputs are LVPECL Output 491.52 MHz 1.9 W Output 245.76 MHz P LVDS REF at 30.72 MHz, Outputs are LVDS 1.65 W Output 122.88 MHz Output 61.44 MHz Output 30.72 MHz P LVCMOS REF at 30.72 MHz, Outputs are LVCMOS 1.8 W In case of LVCMOS Outputs 245.76 MHz Dividers are disabled. Outputs are P OFF REF at 30.72 MHz 0.75 W disabled. P PD Device is powered down mW DIFFERENTIAL INPUT MODE (PRI_IN, SEC_IN) V INPP Input amplitude _IN V /IN (1) 0.1 1.3 V V IC Common-mode input voltage 1.0 V CC 0.3 V Differential input current high (no internal I IH V I V CC V CC 3.6 V µ A termination) Differential input current low (no internal I IL V I V CC 3.6 V µ A termination) Input Capacitance on PRI_IN, SEC_IN pF LVCMOS INPUT MODE (AUX_IN) V IL Low-level input voltage LVCMOS 0.3 x V CC V V IH High-level input voltage LVCMOS 0.7 x V CC V CC V VIK LVCMOS input clamp voltage V CC I I mA 1.2 V I IH LVCMOS input current V I V CC V CC 3.6 V 300 µ A I IL LVCMOS input V I V CC 3.6 V µ A C I Input capacitance (LVCMOS signals) V I V or V CC pF CRYSTAL INPUT SPECIFICATIONS Crystal shunt capacitance pF Equivalent series resistance (ESR) Ω LVCMOS INPUT MODE (SPI_CLK,SPI_MOSI,SPI_LE,PD,SYNC,REF_SEL, PRI_IN, SEC_IN Low-level input voltage LVCMOS, 0.3 x V CC V High-level input voltage LVCMOS 0.7 x V CC V CC V V IK LVCMOS input clamp voltage V CC I I mA 1.2 V I IH LVCMOS input current V I V CC V CC 3.6 V µ A LVCMOS input (Except PRI_IN and I IL V I V CC 3.6 V µ A SEC_IN) I IL LVCMOS input (PRI_IN and SEC_IN) V I V CC 3.6 V µ A C I Input capacitance (LVCMOS signals) V I V or V CC pF (1) V INPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum V INPP of 100mV. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

(Continued) CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT SPI OUTPUT (MISO) PLL DIGITAL (OUTPUT MODE) I OH High-level output current V CC 3.3 V O 1.65 V mA I OL Low-level output current V CC 3.3 V O 1.65 V mA V OH High-level output voltage for LVCMOS outputs V CC I OH 100 µ A V CC 0.5 V V OL Low-level output voltage for LVCMOS outputs V CC I OL 100 µ A 0.3 V C O Output capacitance on MISO VCC 3.3 VO V or VCC pF I OZH V O V CC 3-state output current µ A V O V I OZL PLL ANALOG INPUT MODE) High-impedance state output current for PLL I OZH LOCK V O 3.6 V PD is set low) µ A LOCK output (2) High-impedance state output current for PLL I OZL LOCK V O V PD is set low) µ A LOCK output Positive input threshold voltage V CC min to V V CC 0.55 V max Negative input threshold voltage V CC min to V T V CC 0.35 V max VBB I BB 0.2 mA, Depending on the VBB Termination voltage for reference inputs. 0.9 1.9 V setting. INPUT BUFFERS INTERNAL TERMINATION RESISTORS (PRI_IN and SEC_IN) Termination resistance Single ended Ω PHASE DETECTOR f CPmax Charge pump frequency 0.04 MHz (1) All typical values are at V CC 3.3 temperature C (2) Lock output has a 80k Ω pull-down resistor. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

(Continued) 5 pFL VCMOS CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT LVCMOS OUTPUT OR AUXILIARY OUTPUT f clk Output frequency, see Figure Below Load pF to GND 250 MHz High-level output voltage for LVCMOS V OH V CC min to max I OH 100 µ A V CC 0.5 outputs Low-level output voltage for LVCMOS V OL V CC min to max I OL =100 A 0.3 V outputs I OH High-level output current V CC 3.3 V V O 1.65 V mA I OL Low-level output current V CC 3.3 V V O 1.65 V mA Reference (PRI_IN or SEC_IN) to Output Outputs are set to 122.88 MHz, Reference t pho 0.35 ns Phase offset at 30.72 MHz t pd(LH)/ Propagation delay from PRI_IN or SEC_IN Crosspoint to V CC /2, load In Bypass Mode ns to Outputs t pd(HL) All Outputs set at 200 MHz in bypass mode t sk(o) Skew, output to output For to ps only, Reference 200 MHz C O Output capacitance on to V CC 3.3 V O V or V CC pF I OZH V O V CC µ A 3-State LVCMOS output current I OZL V O V µ A I OPDH V O V CC µ A Power Down output current I OPDL V O V µ A Duty cycle LVCMOS 45% 55% t slew-rate Output rise/fall slew rate 3.6 5.2 V/ns (1) All typical values are at V CC 3.3 temperature C Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

(Continued) (1) (2) (3) (4) LVDS□DC Termination Test Oscilloscope100 Ω CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (5) MAX UNIT LVDS OUTPUT f clk Output frequency Configuration Load 800 MHz OD Differential output voltage R L 100 Ω 270 550 mV Δ V OD LVDS VOD magnitude change mV V OS Offset Voltage C to C 1.24 V Δ V OS VOS magnitude change mV Short circuit Vout+ to ground VOUT mA Short circuit Vout to ground VOUT mA t pho Reference (PRI_IN or SEC_IN) to output Outputs are set to 491.52 MHz 1.65 ns phase offset Reference at 30.72 MHz t pd(LH) pd(HL) Propagation delay from PRI_IN or SEC_IN to Crosspoint to Crosspoint, load In Bypass 3.1 ns outputs Mode All Outputs set at 200 MHz t sk(o) (6) Skew, output to output For to In Bypass Mode Only ps Reference 200 MHz C O Output capacitance on to V CC 3.3 V O V or V CC pF I OPDH Power down output current V O V CC µ A I OPDL Power down output current V O V µ A Duty cycle 45% 55% t r t f Rise and fall time 20% to 80% of V OUT(PP) 110 160 190 ps LVCMOS-TO-LVDS t skP_c Output skew between LVCMOS and LVDS V CC to Crosspoint 0.9 1.4 1.9 ns outputs (7) (1) This is valid only for same REF_IN clock and Y output clock frequency (2) VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP of 100mV. (3) Lock output has a k Ω pull-down resistor. (4) The phase of LVCMOS is lagging in reference to the phase of LVDS. (5) All typical values are at V CC 3.3 temperature C (6) The t sk(o) specification is only valid for equal loading of all outputs. (7) Operating the LVCMOS or LVDS output above the maximum frequency will not cause a malfunction to the device, but the output signal swing might no longer meet the output specification Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

(Continued) L VPECL DC T ermination T est 50 Ω 50 Ω Oscilloscope L VPECL AC T ermination T est 50 Ω 50 Ω Oscilloscope 150 Ω 150 Ω Vcc-2 CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of C to C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT LVPECL OUTPUT f clk Output frequency, Configuration load 1500 MHz V OH LVPECL high-level output voltage load V CC 1.06 V CC 0.88 V V OL LVPECL low-level output voltage load V CC 2.02 V CC 1.58 V OD Differential output voltage 610 970 mV Outputs are set to 491.52 MHz, t pho Reference to Output Phase offset 1.47 ns Reference at 30.72 MHz t pd(LH) Crosspoint to Crosspoint, load In Propagation delay from PRI_IN or SEC_IN to outputs 3.4 ns Bypass Mode t pd(HL) All Outputs set at 200 MHz t sk(o) Skew, output to output For to In Bypass Mode Only ps Reference 200MHz C O Output capacitance on to V CC 3.3 V O V or V CC pF I OPDH V O V CC µ A Power Down output current I OPDL V O V µ A Duty Cycle 45% 55% t r t f Rise and fall time 20% to 80% of V OUT(PP) 135 ps LVDS-TO-LVPECL t skP_C Output skew between LVDS and LVPECL outputs Crosspoint to Crosspoint 0.9 1.1 1.3 ns LVCMOS-TO-LVPECL t skP_C Output skew between LVCMOS and LVPECL outputs V CC to Crosspoint 150 260 700 ps LVPECL HI-PERFORMANCE OUTPUT V OH LVPECL high-level output voltage load V CC 1.11 V CC 0.87 V V OL LVPECL low-level output voltage load V CC 2.06 V CC 1.73 V OD Differential output voltage 760 1160 mV t r t f Rise and fall time 20% to 80% of V OUT(PP) 135 ps (1) All typical values are at V CC 3.3 temperature C Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

V CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 LVPECL OUTPUT SWING HI SWING LVPECL OUTPUT SWING vs vs FREQUENCY FREQUENCY Figure 10. Figure 11. LVDS OUTPUT SWING LVCMOS OUTPUT SWING vs vs FREQUENCY FREQUENCY Figure 12. Figure 13. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com over recommended ranges of supply voltage, load and operating free air temperature (unless otherwise noted) PARAMETER MIN TYP MAX UNIT PRI_IN/SEC_IN_IN REQUIREMENTS Maximum Clock Frequency Applied to PRI_IN SEC_IN in fan-out mode 1500 MHz Maximum Clock Frequency Applied to Smart Multiplexer input Divider 500 MHz f max Maximum Clock Frequency Applied to Reference Divider 250 MHz For Single ended Inputs LVCMOS) on PRI_IN and SEC_IN 250 MHz Single duty cycle of PRI_IN or SEC_IN at V CC 40% 60% Differential duty cycle of PRI_IN or SEC_IN at V CC 40% 60% AUXILARY_IN REQUIREMENTS f REF Single ended Inputs (LVCMOS) on AUX_IN MHz f REF Crystal single ended Inputs (AT-Cut Crystal Input) MHz PD SYNC REF_SEL REQUIREMENTS t r t f Rise and fall time of the PD, SYNC, REF_SEL signal from 20% to 80% of V CC ns Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

www.ti.com SCAS862 NOVEMBER 2008 Table Device Output Phase Noise for 30.72 MHz External Reference Phase Noise Specifications under following configuration: VCO 1966.08 MHz, REF 30.72 MHz, PFD Frequency 30.72 MHz, Charge Pump Current 1.5 mA Loop BW 400 kHz at 3.3 V and C Phase Noise Reference 30.72 LVPECL 491.52 LVDS LVCMOS Unit MHz MHz 122.88 491.52 MHz MHz Hz -108 dBc/Hz 100 Hz -130 108 dBc/Hz kHz -134 106 106 118 dBc/Hz kHz -152 119 119 132 dBc/Hz 100 kHz -156 121 122 134 dBc/Hz MHz -157 131 131 143 dBc/Hz MHz 145 144 150 dBc/Hz MHz 145 144 150 dBc/Hz Jitter(RMS) 193 307 315 377 fs 10k~20 MHz Table Device Output Phase Noise for MHz Crystal Reference Phase Noise Specifications under following configuration: VCO 2000.00 MHz, AUX-REF 25.00 MHz, PFD Frequency 25.00 MHz, Charge Pump Current 1.5 mA Loop BW 400 kHz at 3.3 V and C Phase Noise Referenc LVPECL 500 MHz LVDS 250 MHz LVCMOS 125 MHz Unit e MHz Hz -57 -62 -68 dBc/Hz 100 Hz -90 -95 -102 dBc/Hz kHz -107 -113 -119 dBc/Hz kHz -115 -122 -128 dBc/Hz 100 kHz -118 -124 -130 dBc/Hz MHz -130 -137 -143 dBc/Hz MHz -145 -147 -150 dBc/Hz MHz -145 -147 -150 dBc/Hz Jitter(RMS) 389 405 437 fs 10k~20 MHz Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com Connect output to a spectrum analyzer. Disable Outputs Measure spurious on Output Enable aggressor channels individually per Table Measure spurious on Output The difference between the spurious levels of Output before and after enabling the aggressor channels determine the output-to-output isolation performance recorded. Table Output to Output Isolation M SPUR Unit The Output to Output Isolation was tested under following settings are C Output Measured Channel In LVPECL Signaling 15.5 MHz db Output Measured Channel In LVPECL Signaling MHz db Output Measured Channel In LVPECL Signaling 930 MHz db Output Aggressor Channel LVPECL 22.14 MHz Output Aggressor Channel LVPECL 22.14 MHz Output Aggressor Channel LVPECL 22.14 MHz Output Aggressor Channel LVPECL 22.14 MHz Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

SPI _ CLK Bit0 Bit1 Bit29 Bit30 Bit31 SPI _ LE SPI _ MOSI t4 t5 t2 t3 SPI _ CLK SPI _ MOSI SPI _ MISO SPI _ LE Bit30 Bit31 Bit0 Bit1 Bit2 t4 t5 t2 t3 t6 t8 CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Figure 14. Timing Diagram for SPI Write Command Figure 15. Timing Diagram for SPI Read Command SPI Bus Timing Characteristics PARAMETER MIN TYP MAX UNIT f Clock Clock Frequency for the SPI_CLK MHz t SPI_LE to SPI_CLK setup time ns t SPI_MOSI to SPI_CLK setup time ns t SPI_MOSI to SPI_CLK hold time ns t SPI_CLK high duration ns t SPI_CLK low duration ns t SPI_CLK to SPI_LE Setup time ns t SPI_LE Pulse Width ns t SPI_MISO to SPI_CLK Data Valid (First Valid Bit after LE) ns Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Channel□1 Output Channel□2 Output Channel□3 Output Channel□4 Output Channel□0 EEPROM Input Block Synthesizer Block Output□Blocks Interface Control Block 5 4 3 2 Register 5 Register□Number (s) RAM□Bit□Number (s) 5.2 CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com The Functional CDCE62005. Figure depicts these blocks along with a high-level functional block diagram of the circuit elements comprising each block. The balance of this section focuses on a detailed discussion of each functional block from the perspective of how to configure them. Figure 16. CDCE62005 Circuit Blocks Throughout this section, references to Device Register memory locations follow the following convention: Figure 17. Device Register Reference Convention Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

REF_SELECT /Power_Down /SYNC EEPROM□(Default□Configuration) Device HardwareSPI_LE SPI_CLK SPI_MISO SPI_MOSI Register□0 Static□RAM□(Device□Registers) Register□1 Register□2 Register□3 Register□4 Register□5 Register□6 Register□7 Register□8 Register□0 Register□1 Register□2 Register□3 Register□4 Register□5 Register□6 Register□7 SPI (Serial Peripheral Interface) CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 The Interface Control Block includes a SPI interface, four control pins, a non-volatile memory array in which the device stores default configuration data, and an array of device registers implemented in Static RAM. This RAM, also called the device registers, configures all hardware within the CDCE62005. Figure 18. CDCE62005 Interface and Control Block The serial interface of CDCE62005 is a simple bidirectional SPI interface for writing and reading to and from the device registers. It implements a low speed serial communications link in a master/slave topology in which the CDCE62005 is a slave. The SPI consists of four signals: SPI_CLK: Serial Clock (Output from Master) the CDCE62005 clocks data in and out on the rising edge of SPI_CLK. Data transitions therefore occur on the falling edge of the clock. SPI_MOSI: Master Output Slave Input (Output from Master) SPI_MISO: Master Input Slave Output (Output from Slave) SPI_LE: Latch Enable (Output from Master). The falling edge of SPI_LE initiates a transfer. If SPI_LE is high, no data transfer can take place. The CDCE62005 implements data fields that are 28-bits wide. In addition, it contains registers, each comprising a bit data field. Therefore, accessing the CDCE62005 requires that the host program append a 4-bit address field to the front of the data field as follows: Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

0123456789101112131415161718192021222324252627 0123 0123456789101112131415161718192021222324252627 0123 Address Bits (4) Last□in / Last□out First□In/ First□Out SPI_LE SPI_CLK SPI_MOSI SPI_MISO SPI_LE SPI_CLK SPI_MOSI SPI_MISO SPI□Master (Host) SPI_LE SPI_CLK SPI_MOSI SPI_MISO SPI□Slave (CDCE62005) Device□Register□N 0123456789101112131415161718192021222324252627 SPI□Register Data□Bits (28) CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Figure 19. CDCE62005 SPI Communications Format CDCE62005 SPI Command Structure The CDCE62005 supports four commands issued by the Master via the SPI: Write to RAM Read Command Copy RAM to EEPROM unlock Copy RAM to EEPROM lock Table provides a summary of the CDCE62005 SPI command structure. The host (master) constructs a Write to RAM command by specifying the appropriate register address in the address field and appends this value to the beginning of the data field. Therefore, a valid command stream must include bits, transmitted LSB first. The host must issue a Read Command to initiate a data transfer from the CDCE62005 back to the host. This command specifies the address of the register of interest in the data field. Table CDCE62005 SPI Command Structure Data Field (28 Bits) Addr Field Bits) Register Operation NVM Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X Status/Control No X X X X X X X X X X X X X X X X X X X X X X X X X X X X Instruction Read Command No A A A A Instruction RAM EEPROM Unlock Instruction RAM EEPROM Lock (1) (1) CAUTION: After execution of this command, the EEPROM is permanently locked. After locking the EEPROM, device configuration can only be changed via Write to RAM after power-up; however, the EEPROM can no longer be changed Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

www.ti.com SCAS862 NOVEMBER 2008 The CDCE62005 on-board EEPROM has been factory preset to the default settings listed in the table below. REGISTER DEFAULT SETTING REG0000 8184032 REG0001 8184030 REG0002 8186030 REG0003 EB86030 REG0004 0186031 REG0005 101C0BE REG0006 04BE19A REG0007 BD0037F REG0008 (RAM) 80005DD The Default configurations programmed in the device is set to: Primary and Secondary are set to LVPECL AC termination and the Auxiliary input is enabled. The Smart Mux is set to auto select among Primary, Secondary and Auxiliary. Reference is set at 25MHz and the dividers are selected to run the VCO at 1875MHz. Output are set to output 156.25MHz with LVPECL signaling Output is set to output 125MHz/ LVPECL Output is set to output 125MHz/ LVDS Output is set to output 125MHz/ LVCMOS Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

SPI_CLK Bit0 Bit1 Bit29 Bit30 Bit31 SPI_LE SPI_MOSI SPI_ CLK SPI_ MOSI SPI_ MISO SPI _LE Bit Bit 0 Bit 1 Bit 2 Bit30 31 CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Writing to the CDCE62005 Figure illustrates a Write to RAM operation. Notice that the latching of the first data bit in the data stream (Bit occurs on the first rising edge of SPI_CLK after SPI_LE transitions from a high to a low. For the CDCE62005, data transitions occur on the falling edge of SPI_CLK. A rising edge on SPI_LE signals to the CDCE62005 that the transmission of the last bit in the stream (Bit 31) has occurred. Figure 20. CDCE62005 SPI Write Operation Reading from the CDCE62005 Figure shows how the CDCE62005 executes a Read Command. The SPI master first issues a Read Command to initiate a data transfer from the CDCE62005 back to the host (see Table 6). This command specifies the address of the register of interest. By transitioning SPI_LE from a low to a high, the CDCE62005 resolves the address specified in the appropriate bits of the data field. The host drives SPI_LE low and the CDCE62005 presents the data present in the register specified in the Read Command on SPI_MISO. Figure 21. CDCE62005 Read Operation Writing to EEPROM After the CDCE62005 detects a power-up and completes a reset cycle, it copies the Registers. Therefore, the CDCE62005 initializes into a known state pre-defined by the user. The host issues one of two special commands shown in Table to copy the bits) into EERPOM. They include: Copy RAM to EEPROM Unlock, Execution of this command can happen many times. Copy RAM to EEPROM Lock: Execution of this command can happen only once; after which the EEPROM is permanently locked After either command is initiated, power must remain stable and the host must not access the CDCE62005 for at least ms to allow the EEPROM to complete the write cycle and to avoid the possibility of EEPROM corruption. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Registers: Register CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Table CDCE62005 Register Bit Definitions SPI RAM BIT NAME RELATED DESCRIPTION/FUNCTION BIT BIT BLOCK Address Address Address Address DIV2PRIX Pre-Divider Selection for the Primary Reference EEPROM Primary (X,Y)=00:3-state, 01:Divide by 10:Divide by 11:Reserved Reference DIV2PRIY EEPROM RESERVED Used in Test Mode EEPROM RESERVED Used in Test Mode EEPROM OUTMUX0SELX Output OUTPUT MUX Select. Selects the Signal driving Output Divider EEPROM (X,Y) 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE OUTMUX0SELY Output EEPROM PH0ADJC0 Output EEPROM PH0ADJC1 Output EEPROM PH0ADJC2 Output EEPROM PH0ADJC3 Output Coarse phase adjust select for output divider EEPROM PH0ADJC4 Output EEPROM PH0ADJC5 Output EEPROM PH0ADJC6 Output EEPROM OUT0DIVRSEL0 Output EEPROM OUT0DIVRSEL1 Output EEPROM OUT0DIVRSEL2 Output EEPROM OUT0DIVRSEL3 Output OUTPUT DIVIDER Ratio Select EEPROM OUT0DIVRSEL4 Output EEPROM OUT0DIVRSEL5 Output EEPROM OUT0DIVRSEL6 Output EEPROM When set to the divider is disabled OUT0DIVSEL Output EEPROM When set to the divider is enabled High Swing LVPECL When set to and Normal Swing when set to If LVCMOS or LVDS is selected the Output swing will stay at the same level. HiSWINGLVPECL0 Output EEPROM If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to and Normal LVPECL if it is set to CMOSMODE0PX Output LVCMOS mode select for OUTPUT Positive Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE0PY Output EEPROM CMOSMODE0NX Output LVCMOS mode select for OUTPUT Negative Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE0NY Output EEPROM OUTBUFSEL0X Output OUTPUT TYPE RAM BITS EEPROM LVPECL LVDS OUTBUFSEL0Y Output EEPROM LVCMOS See Settings Above* Output Disabled Use 22,23,24 and for setting the LVCMOS Outputs Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Registers: Register CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Table CDCE62005 Register Bit Definitions SPI RA BIT NAME RELATED DESCRIPTION/FUNCTION BIT M BLOCK BIT Address Address Address Address DIV2SECX Pre-Divider Selection for the Secondary Reference EEPROM Secondary (X,Y)=00:3-state, 01:Divide by 10:Divide by 11:Reserved Reference DIV2SECY EEPROM RESERVED Used in Test Mode EEPROM RESERVED Used in Test Mode EEPROM OUTMUX1SELX Output OUTPUT MUX Select. Selects the Signal driving Output Divider EEPROM (X,Y) 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE OUTMUX1SELY Output EEPROM PH1ADJC0 Output EEPROM PH1ADJC1 Output EEPROM PH1ADJC2 Output EEPROM PH1ADJC3 Output Coarse phase adjust select for output divider EEPROM PH1ADJC4 Output EEPROM PH1ADJC5 Output EEPROM PH1ADJC6 Output EEPROM OUT1DIVRSEL0 Output EEPROM OUT1DIVRSEL1 Output EEPROM OUT1DIVRSEL2 Output EEPROM OUT1DIVRSEL3 Output OUTPUT DIVIDER Ratio Select EEPROM OUT1DIVRSEL4 Output EEPROM OUT1DIVRSEL5 Output EEPROM OUT1DIVRSEL6 Output EEPROM When set to the divider is disabled OUT1DIVSEL Output EEPROM When set to the divider is enabled High Swing LVPECL When set to and Normal Swing when set to If LVCMOS or LVDS is selected the Output swing will stay at the same level. HiSWINGLVPECL1 Output EEPROM If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to and Normal LVPECL if it is set to CMOSMODE1PX Output LVCMOS mode select for OUTPUT Positive Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE1PY Output EEPROM CMOSMODE1NX Output LVCMOS mode select for OUTPUT Negative Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE1NY Output EEPROM OUTBUFSEL1X Output OUTPUT TYPE RAM BITS EEPROM LVPECL LVDS OUTBUFSEL1Y Output EEPROM LVCMOS See Settings Above* Output Disabled Use 22,23,24 and for setting the LVCMOS Outputs Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Registers: Register CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Table CDCE62005 Register Bit Definitions SPI RA BIT NAME RELATED DESCRIPTION/FUNCTION BIT M BLOCK BIT Address Address Address Address REFDIV0 Reference Divider Bit EEPROM Reference Divider REFDIV1 Reference Divider Bit EEPROM RESERVED Used in Test Mode EEPROM RESERVED Used in Test Mode EEPROM OUTMUX2SELX Output OUTPUT MUX Select. Selects the Signal driving Output Divider EEPROM (X,Y) 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE OUTMUX2SELY Output EEPROM PH2ADJC0 Output EEPROM PH2ADJC1 Output EEPROM PH2ADJC2 Output EEPROM PH2ADJC3 Output Coarse phase adjust select for output divider EEPROM PH2ADJC4 Output EEPROM PH2ADJC5 Output EEPROM PH2ADJC6 Output EEPROM OUT2DIVRSEL0 Output EEPROM OUT2DIVRSEL1 Output EEPROM OUT2DIVRSEL2 Output EEPROM OUT2DIVRSEL3 Output OUTPUT DIVIDER Ratio Select EEPROM OUT2DIVRSEL4 Output EEPROM OUT2DIVRSEL5 Output EEPROM OUT2DIVRSEL6 Output EEPROM When set to the divider is disabled OUT2DIVSEL Output EEPROM When set to the divider is enabled High Swing LVPECL When set to and Normal Swing when set to If LVCMOS or LVDS is selected the Output swing will stay at the same level. HiSWINGLVPEC2 Output EEPROM If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to and Normal LVPECL if it is set to CMOSMODE2PX Output LVCMOS mode select for OUTPUT Positive Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE2PY Output EEPROM CMOSMODE2NX Output LVCMOS mode select for OUTPUT Negative Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE2NY Output EEPROM OUTBUFSEL2X Output OUTPUT TYPE RAM BITS EEPROM LVPECL LVDS OUTBUFSEL2Y Output EEPROM LVCMOS See Settings Above* Output Disabled Use 22,23,24 and for setting the LVCMOS Outputs Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Registers: Register CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Table CDCE62005 Register Bit Definitions SPI RAM BIT NAME RELATED DESCRIPTION/FUNCTION BIT BIT BLOCK Address Address Address Address Reference REFDIV2 Reference Divider Bit EEPROM Divider RESERVED EEPROM RESERVED Used in Test Mode EEPROM RESERVED Used in Test Mode EEPROM OUTMUX3SELX Output OUTPUT MUX Select. Selects the Signal driving Output Divider EEPROM (X,Y) 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE OUTMUX3SELY Output EEPROM PH3ADJC0 Output EEPROM PH3ADJC1 Output EEPROM PH3ADJC2 Output EEPROM PH3ADJC3 Output Coarse phase adjust select for output divider EEPROM PH3ADJC4 Output EEPROM PH3ADJC5 Output EEPROM PH3ADJC6 Output EEPROM OUT3DIVRSEL0 Output EEPROM OUT3DIVRSEL1 Output EEPROM OUT3DIVRSEL2 Output EEPROM OUT3DIVRSEL3 Output OUTPUT DIVIDER Ratio Select EEPROM OUT3DIVRSEL4 Output EEPROM OUT3DIVRSEL5 Output EEPROM OUT3DIVRSEL6 Output EEPROM When set to the divider is disabled OUT3DIVSEL Output EEPROM When set to the divider is enabled High Swing LVPECL When set to and Normal Swing when set to If LVCMOS or LVDS is selected the Output swing will stay at the same level. HiSWINGLVPEC3 Output EEPROM If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to and Normal LVPECL if it is set to CMOSMODE3PX Output LVCMOS mode select for OUTPUT Positive Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE3PY Output EEPROM CMOSMODE3NX Output LVCMOS mode select for OUTPUT Negative Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE3NY Output EEPROM OUTBUFSEL3X Output OUTPUT TYPE RAM BITS EEPROM LVPECL LVDS OUTBUFSEL3Y Output EEPROM LVCMOS See Settings Above* Output Disabled Use 22,23,24 and for setting the LVCMOS Outputs Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Registers: Register CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Table CDCE62005 Register Bit Definitions SPI RAM BIT NAME RELATED DESCRIPTION/FUNCTION BIT BIT BLOCK Address Address Address Address RESERVED This bit must be set to a EEPROM (default): normal operation, ATETEST TI Test Bit EEPROM outputs have deterministic delay relative to low-to-high edge of SYNC pin RESERVED Used in Test Mode EEPROM RESERVED Used in Test Mode EEPROM OUTMUX4SELX Output OUTPUT MUX Select. Selects the Signal driving Output Divider EEPROM (X,Y) 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE OUTMUX4SELY Output EEPROM PH4ADJC0 Output EEPROM PH4ADJC1 Output EEPROM PH4ADJC2 Output EEPROM PH4ADJC3 Output Coarse phase adjust select for output divider EEPROM PH4ADJC4 Output EEPROM PH4ADJC5 Output EEPROM PH4ADJC6 Output EEPROM OUT4DIVRSEL0 Output EEPROM OUT4DIVRSEL1 Output EEPROM OUT4DIVRSEL2 Output EEPROM OUT4DIVRSEL3 Output OUTPUT DIVIDER Ratio Select EEPROM OUT4DIVRSEL4 Output EEPROM OUT4DIVRSEL5 Output EEPROM OUT4DIVRSEL6 Output EEPROM When set to the divider is disabled OUT4DIVSEL Output EEPROM When set to the divider is enabled High Swing LVPECL When set to and Normal Swing when set to If LVCMOS or LVDS is selected the Output swing will stay at the same level. HiSWINGLVPEC4 Output EEPROM If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to and Normal LVPECL if it is set to CMOSMODE4PX Output LVCMOS mode select for OUTPUT Positive Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE4PY Output EEPROM CMOSMODE4NX Output LVCMOS mode select for OUTPUT Negative Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State CMOSMODE4NY Output EEPROM OUTBUFSEL4X Output OUTPUT TYPE RAM BITS EEPROM LVPECL LVDS OUTBUFSEL4Y Output EEPROM LVCMOS See Settings Above* Output Disabled Use 22,23,24 and for setting the LVCMOS Outputs Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Registers: Register CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Table 10. CDCE62005 Register Bit Definitions SPI RAM BIT NAME RELATED DESCRIPTION/FUNCTION BIT BIT BLOCK Address Address Address Address Input Buffer Select (LVPECL,LVDS or LVCMOS) INBUFSELX INBUFSELX EEPROM XY(01 LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin INBUFSELY INBUFSELY EEPROM PRISEL WHEN EECLKSEL EEPROM Bit (6,7,8) 100 PRISEL, 010 SECSEL 001 AUXSEL SECSEL EEPROM 110 Auto Select PRI then SEC) Smart MUX 111 Auto Select PRI then SEC and then AUX) AUXSEL EEPROM When EECLKSEL REF_SEL pin determines the Reference Input to the Smart Mux circuitry. If EEPROM Clock Select Input is set to The Clock selections follows internal EEPROM EECLKSEL Smart MUX settings and ignores REF_SEL Pin status, when Set to REF_SEL is used to control EEPROM the Mux, Auto Select Function is not available and AUXSEL is not available. ACDCSEL Input Buffers If Set to DC Termination, If set to AC Termination EEPROM Input Buffers If Set to Input Buffers Hysteresis Enabled. It is not recommended that Hysteresis be HYSTEN EEPROM disabled. If Set to Primary Input Buffer Internal Termination Enabled PRI_TERMSEL Input Buffers EEPROM If set to Primary Internal Termination circuitry Disabled PRIINVBB Input Buffers If Set to Primary Input Negative Pin Biased with Internal VBB Voltage. EEPROM SECINVBB Input Buffers If Set to Secondary Input Negative Pin Biased with Internal VBB Voltage EEPROM If Set to Fail Safe is Enabled for all Input Buffers configured as LVDS, DC Coupling FAILSAFE Input Buffers EEPROM only. RESERVED Must be set to EEPROM RESERVED Must be set to EEPROM SELINDIV0 VCO Core EEPROM SELINDIV1 VCO Core EEPROM SELINDIV2 VCO Core EEPROM SELINDIV3 VCO Core EEPROM INPUT DIVIDER Settings SELINDIV4 VCO Core EEPROM SELINDIV5 VCO Core EEPROM SELINDIV6 VCO Core EEPROM SELINDIV7 VCO Core EEPROM LOCKW(0) PLL Lock LOCKW(3:0): Lock-detect Window Width EEPROM 0000 (narrow window), LOCKW(1) EEPROM 0001,0010,0100,0101 LOCKW(2) EEPROM 1110 (widest window) LOCKW(3) EEPROM XX11 (RESERVED) Number of coherent lock events. If set to it triggers after the first lock detection if set to LOCKDET PLL Lock EEPROM it triggers lock after cycles of lock detections. ADLOCK PLL Lock Selects Digital PLL_LOCK ,Selects Analog PLL_LOCK EEPROM Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Registers: Register CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Table 11. CDCE62005 Register Bit Definitions SPI RAM BIT NAME RELATED DESCRIPTION/FUNCTION BIT BIT BLOCK Address Address Address Address SELVCO VCO Core VCO Select, 0:VCO1(low range), 1:VCO2(high range) EEPROM SELPRESCA VCO Core EEPROM PRESCALER Setting. SELPRESCB VCO Core EEPROM SELFBDIV0 VCO Core EEPROM SELFBDIV1 VCO Core EEPROM SELFBDIV2 VCO Core EEPROM SELFBDIV3 VCO Core EEPROM FEEDBACK DIVIDER Setting SELFBDIV4 VCO Core EEPROM SELFBDIV5 VCO Core EEPROM SELFBDIV6 VCO Core EEPROM SELFBDIV7 VCO Core EEPROM RESERVED Must be set to EEPROM If Set to Secondary Input Buffer Internal Termination Enabled SEC_TERMSEL Input Buffers EEPROM If set to Secondary Internal Termination circuitry Disabled SELBPDIV0 VCO Core EEPROM SELBPDIV1 VCO Core BYPASS DIVIDER Setting settings Disable Enable) EEPROM SELBPDIV2 VCO Core EEPROM ICPSEL0 VCO Core EEPROM ICPSEL1 VCO Core EEPROM CHARGE PUMP Current Select ICPSEL2 VCO Core EEPROM ICPSEL3 VCO Core EEPROM RESERVED VCO Core Must be set to EEPROM CPPULSEWIDTH VCO Core If set to 1=wide pulse, 0=narrow pulse EEPROM Enable VCO Calibration Command. To execute this command a rising edge must be generated (i.e. Write a LOW followed by a high to this bit location). This will initiate a ENCAL VCO Core EEPROM VCO calibration sequence only if Calibration Mode Manual Mode (i.e. Register bit is HIGH). RESERVED Must be set to EEPROM AUXOUTEN Output AUX Enable Auxiliary Output when set to EEPROM Select the Output that will driving the AUX Output; AUXFEEDSEL Output AUX EEPROM Low for Selecting Output Divider and High for Selecting Output Divider When Set to External Loop filter is used. EXLFSEL VCO Core EEPROM When Set to Internal Loop Filter is used. Calibration Mode Manual Mode. In this mode, a calibration will be initiated if a rising PLL edge is asserted on ENCAL (Register Bit 22). ENCAL_MODE EEPROM Calibration Calibration Mode Startup Mode. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Registers: Register CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Table 12. CDCE62005 Register Bit Definitions SPI RAM BIT NAME RELATED DESCRIPTION/FUNCTION BIT BIT BLOCK Address Address Address Address LFRCSEL0 VCO Core Loop Filter Control Setting EEPROM LFRCSEL1 VCO Core Loop Filter Control Setting EEPROM LFRCSEL2 VCO Core Loop Filter Control Setting EEPROM LFRCSEL3 VCO Core Loop Filter Control Setting EEPROM LFRCSEL4 VCO Core Loop Filter Control Setting EEPROM LFRCSEL5 VCO Core Loop Filter Control Setting EEPROM LFRCSEL6 VCO Core Loop Filter Control Setting EEPROM LFRCSEL7 VCO Core Loop Filter Control Setting EEPROM LFRCSEL8 VCO Core Loop Filter Control Setting EEPROM LFRCSEL9 VCO Core Loop Filter Control Setting EEPROM LFRCSEL10 VCO Core Loop Filter Control Setting EEPROM LFRCSEL11 VCO Core Loop Filter Control Setting EEPROM LFRCSEL12 VCO Core Loop Filter Control Setting EEPROM LFRCSEL13 VCO Core Loop Filter Control Setting EEPROM LFRCSEL14 VCO Core Loop Filter Control Setting EEPROM LFRCSEL15 VCO Core Loop Filter Control Setting EEPROM LFRCSEL16 VCO Core Loop Filter Control Setting EEPROM LFRCSEL17 VCO Core Loop Filter Control Setting EEPROM LFRCSEL18 VCO Core Loop Filter Control Setting EEPROM LFRCSEL19 VCO Core Loop Filter Control Setting EEPROM LFRCSEL20 VCO Core Loop Filter Control Setting EEPROM RESERVED Must be set to "0" EEPROM TESTMUX1 Diagnostics Set to EEPROM If set to it enables short delay for fast operation SEL_DEL2 Smart Mux EEPROM If Set to Long Delay recommended for Input References below 150MHz. TEXTMUX2 Diagnostics Set to EEPROM If set to it enables short delay for fast operation SEL_DEL1 Smart Mux EEPROM If Set to Long Delay recommended for Input References below 150MHz. Read Only If EPLOCK reads EEPROM is unlocked. If EPLOCK reads then the EPLOCK Status EEPROM EEPROM is locked (see Table for how to lock the EEPROM this can only be executed once after which the EEPROM is locked permanently RESERVED Status Read Only Always reads EEPROM Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Registers: Register CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Table 13. CDCE62005 Register Bit Definitions SPI RAM BIT NAME RELATED DESCRIPTION/FUNCTION BIT BIT BLOCK Address Address Address Address CALWORD0 Status RAM CALWORD1 Status RAM CALWORD2 Status RAM VCO Calibration Word read back from device CALWORD3 Status RAM CALWORD4 Status RAM CALWORD5 Status RAM PLLLOCKPIN Status Read Only: Status of the PLL Lock Pin Driven by the device. RAM /SLEEP Status Set Device Sleep mode On when set to Normal Mode when set to RAM If set to this bit forces /SYNC Set to to exit the Synchronization /SYNC Status RAM State. RESERVED RAM VERSION0 Silicon Revision RAM VERSION1 Silicon Revision RAM VERSION2 Silicon Revision RAM RESERVED Must be set to RAM CALWORD_IN0 Diagnostics RAM CALWORD_IN1 Diagnostics RAM CALWORD_IN2 Diagnostics RAM TI Test Registers. For TI Use Only CALWORD_IN3 Diagnostics RAM CALWORD_IN4 Diagnostics RAM CALWORD_IN5 Diagnostics RAM RESERVED Must be set to RAM TITSTCFG0 Diagnostics RAM TITSTCFG1 Diagnostics RAM TI Test Registers. For TI Use Only TITSTCFG2 Diagnostics RAM TITSTCFG3 Diagnostics RAM PRIACTIVITY Status Synthesizer Source Indicator (27:25) RAM Primary Input SECACTIVITY Status RAM Secondary Input AUXACTIVITY Status RAM Auxiliary Input Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Active□Mode Power□ON Reset Power□Down Sync Calibration Hold Delay□Finished CAL_Enabled Sleep = ON Sleep = OFF CAL Done Power□Down□=□ON Power Down = OFF Sync□=□ON Sync□=□OFF Power Down = ON Manual Recalibration□=□ON Device OFF Power Applied CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Figure provides a conceptual explanation of the CDCE62005 Device operation. Table defines how the device behaves in each of the operational states. Figure 22. CDCE62005 Device State Control Diagram Table 14. CDCE62005 Device State Definitions Status State Device Behavior Entered Via Exited Via Output Output SPI Port PLL Divider Buffer After device power supply reaches Power applied to the device or upon Power On Reset and EEPROM loading OFF Disabled Disabled OFF approximately 2.35 the Power_Down Power-On of EEPROM are copied into the Power_Down pin set HIGH. pin is set LOW. Reset (1) Device Registers, thereby initializing the device hardware. The device waits until either Delay process in the Power-On Reset The device waits until either ON Enabled Disabled OFF ENCAL_MODE (Device Register State is finished or Sleep Mode Sleep ENCAL_MODE (Device Register bit 27) bit 27) is low (Start up calibration bit is in Register bit is turned OFF is low (Start up calibration enabled) or Calibration enabled) or both ENCAL_MODE is while in the Sleep State. Power Down both ENCAL_MODE is high (Manual Hold high (Manual Calibration Enabled) must be OFF to enter the Calibration Calibration Enabled) AND ENCAL (Device AND ENCAL (Device Register bit Hold State. Register bit 22) transitions from a low to 22) transitions from a low to a high a high signaling the device signaling the device. The voltage controlled oscillator is Calibration Hold: CAL Enabled Calibration Process in completed ON Enabled Disabled OFF calibrated based on the PLL settings becomes true when either and the incoming reference clock. ENCAL_MODE (Device Register bit After the VCO has been calibrated, 27) is low or both ENCAL_MODE is the device enters Active Mode high AND ENCAL (Device Register automatically. bit 22) transitions from a low to a high. VCO CAL Active Mode: A Manual Recalibration is requested. This is initiated by setting ENCAL_MODE to HIGH (Manual Calibration Enabled) AND initiating a calibration sequence by applying a LOW to HIGH transition on ENCAL. Normal Operation CAL Done (VCO calibration process Sync, Power Down, Sleep, or Manual ON Enabled Disabled Disabled Active Mode finished) or Sync OFF (from Sync Recalibration activated. or or State). Enabled Enabled (1) To ensure proper operation, independently from power supply ramp up, Power_Down pin should be held LOW for µ s after power supply is stable. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

www.ti.com SCAS862 NOVEMBER 2008 Table 14. CDCE62005 Device State Definitions (continued) Status State Device Behavior Entered Via Exited Via Output Output SPI Port PLL Divider Buffer Used to shut down all hardware and Power_Down pin is pulled LOW. Power_Down pin is pulled HIGH. ON Disabled Disabled Disabled Resets the device after exiting the Power Power Down State. Therefore, the Down EEPROM exited. Identical to the Power Down State Sleep bit in device register bit is Sleep bit in device register bit is set ON Disabled Disabled Disabled Sleep except the EEPROM LOW. HIGH. not copied into RAM. Sync synchronizes all output Sync Bit in device register bit is Sync Bit in device register bit is set ON Enabled Disabled Disabled dividers so that they begin counting set LOW or Sync pin is pulled LOW HIGH or Sync pin is pulled HIGH at the same time. Note: this Sync operation is performed automatically each time a divider register is accessed. REF_SEL REF_SEL provides a way to switch between the primary and secondary reference inputs (PRI_IN and SEC_IN) via an external signal. It works in conjunction with the smart multiplexer discussed in the Input Block section. Power_Down The Power_Down pin places the CDCE62005 into the power down state Additionally, the CDCE62005 loads the Power_Down pin is de-asserted; therefore, it is used to initialize the device after power is applied. SPI_LE signal has to be HIGH in order for EEPROM to load correctly during the rising edge of Power_Down SYNC The SYNC pin (Active LOW) has a complementary register location located in Device Register bit When enabled, Sync synchronizes all output dividers so that they begin counting simultaneously. Further, SYNC disables all outputs when in the active. State. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

/1:/2:HiZ /1:/2:HiZ Reference□Divider /1 - /8 PRI_IN SEC_IN XTAL / AUX_IN Internal Clock Distribution Bus

1500 MHz

LVPECL : 1500 MHz LVDS : 800 MHz LVCMOS : 250 MHz Crystal : 2 MHz – 42 MHz Single□Ended : 2□MHz – 75□MHz Smart MUX1 Smart MUX2 Smart□MUX Control 5 4 3 2 Register 5 REF_SEL 6 1 0 Register 5 1 0 Register 0 1 0 Register 1 8912 Register 6 Universal□Input□Buffers Smart□Multiplexer Auxiliary□Input 0 1 0 Register 2Register 3 250□MHz 250□MHz CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com The Input Block includes two Universal Input Buffers, an Auxiliary Input, and a Smart Multiplexer. The Input Block drives three different clock signals onto the Internal Clock Distribution Bus: buffered versions of both the primary and secondary inputs (PRI_IN and SEC_IN) and the output of the Smart Multiplexer. Figure 23. CDCE62005 Input Block With References to Registers Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Universal□Input□Control PN PP 6 1 0 Register 5 10 9 8 Register 6 SN SP PINV PRI_IN SINV SEC_IN 5.1 5.0 5.6 INBUFSELY INBUFSELX ACDCSEL 1 0 0 1.9V 1 0 1 1.2V 1 1 0 1.2V 1 1 1 1.2V Nominal Vbb Settings Vbb 1 /c109F Vbb INBUFSELX INBUFSELY TERMSEL INVBB P N INV 0 0 X X OFF OFF OFF X X 1 X OFF OFF OFF X 1 0 0 ON ON ON X 1 0 1 ON ON OFF SWITCH□StatusSettings 50 Ω50 Ω 50 Ω50 Ω CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Universal Input Buffers (UIB) Figure shows the key elements of a universal input buffer. A UIB supports multiple formats along with different termination and coupling schemes. The CDCE62005 implements the UIB by including on board switched termination, a programmable bias voltage generator, and an output multiplexer. The CDCE62005 provides a high degree of configurability on the UIB to facilitate most existing clock input formats. Figure 24. CDCE62005 Universal Input Buffer Table lists several settings for many possible clock input scenarios. Note that the two universal input buffers share the Vbb generator. Therefore, if both inputs use internal termination, they must use the same configuration mode (LVDS, LVPECL, or LVCMOS). If the application requires different modes (e.g. LVDS and LVPECL) then one of the two inputs must implement external termination. Table 15. CDCE62005 Universal Input Buffer Configuration Matrix PRI_IN CONFIGURATION MATRIX SETTINGS CONFIGURATION Register.Bit 5.7 5.1 5.0 5.8 5.9 5.6 Bit Name HYSTEN INBUFSELY INBUFSELX PRI_TERMSEL PRIINVBB ACDCSEL Hysteresis Mode Coupling Termination Vbb X X X ENABLED LVCMOS DC N/A ENABLED LVPECL AC Internal 1.9V ENABLED LVPECL DC Internal 1.2V X X ENABLED LVPECL External ENABLED LVDS AC Internal 1.2V ENABLED LVDS DC Internal 1.2V X X ENABLED LVDS External X X X X X OFF X X X X X ENABLED SEC_IN CONFIGURATION MATRIX SETTINGS CONFIGURATION Register.Bit 5.7 5.1 5.0 6.12 5.10 5.6 Bit Name HYSTEN INBUFSELY INBUFSELX SEC_TERMSEL SECINVBB ACDCSEL Hysteresis Mode Coupling Termination Vbb X X X ENABLED LVCMOS DC N/A Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com Table 15. CDCE62005 Universal Input Buffer Configuration Matrix (continued) PRI_IN CONFIGURATION MATRIX SETTINGS CONFIGURATION Register.Bit 5.7 5.1 5.0 5.8 5.9 5.6 Bit Name HYSTEN INBUFSELY INBUFSELX PRI_TERMSEL PRIINVBB ACDCSEL Hysteresis Mode Coupling Termination Vbb ENABLED LVPECL AC Internal 1.9V ENABLED LVPECL DC Internal 1.2V X X ENABLED LVPECL External ENABLED LVDS AC Internal 1.2V ENABLED LVDS DC Internal 1.2V X X ENABLED LVDS External X X X X X OFF X X X X X ENABLED LVDS Fail Safe Mode Differential data line receivers can switch on noise in the absence of an input signal. This occurs when the bus driver is turned off or the interconnect is damaged or missing. Traditionally the solution to this problem involves incorporating an external resistor network on the receiver input. This network applies a steady-state bias voltage to the input pins. The additional cost of the external components notwithstanding, the use of such a network lowers input signal magnitude and thus reduces the differential noise margin. The CDCE62005 provides internal failsafe circuitry on all LVDS inputs if enabled as shown in Table for DC termination only. Table 16. LVDS Failsafe Settings Bit Name FAILSAFE LVDS Failsafe Register.Bit 5.11 Disabled for all inputs Enabled for all inputs Smart Multiplexer Controls The smart multiplexer implements a configurable switching mechanism suitable for many a design consideration. It includes the multiplexer itself along with three dividers. With respect to the multiplexer control, Table provides an overview of the configurations supported by the CDCE62005. Table 17. CDCE62005 Smart Multiplexer Settings REGISTER SETTINGS EECLKSEL AUXSEL SECSEL PRISEL SMART MULTIPLEXER MODE 5.5 5.4 5.3 5.2 Manual Mode: PRI_IN selected Manual Mode: SEC_IN selected Manual Mode: AUX_IN selected Auto MOde: PRI_IN then SEC_IN Auto Mode: PRI_IN then SEC_IN then AUX_IN X REF_SEL pin selects PRI_IN or SEC_IN Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

PRI _ REF SEC _ REF Internal Reference□Clock Primary□Clock Secondary□Clock Primary□Clock /1:/2:HiZ /1:/2:HiZ Reference□Divider /1 - /8 PRI_IN SEC_IN XTAL/ AUX_IN Internal Clock Distribution Bus Smart MUX1 Smart MUX2 Smart□MUX ControlREF_SEL 1 0 Register 0 1 0 Register 1 Smart□Multiplexer Auxiliary□Input 0 1 0 Register 2Register 3 Universal□Input□Buffers 5 4 3 2 Register 5 CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Smart Multiplexer Auto Mode Smart Multiplexer Auto Mode switches automatically between clock inputs based on a prioritization scheme shown in Table If using the Smart Multiplexer Auto Mode, the frequencies of the clock inputs may differ by up to 20%. The phase relationship between clock inputs has no restriction. The smart multiplexer includes signal conditioning that provides glitch suppression (1) Upon the detection of a loss of signal on the highest priority clock, the smart multiplex switches its output to the next highest priority clock on the first incoming rising edge of the next highest priority clock. During this switching operation, the output of the smart multiplexer is low. Upon restoration of the higher priority clock, the smart multiplexer waits until it detects four complete cycles from the higher priority clock prior to switching the output of the smart multiplexer back to the higher priority clock. During this switching operation, the output of the smart multiplexer remains high until the next falling edge as shown in Figure Figure 25. CDCE62005 Smart Multiplexer Timing Diagram Smart Multiplexer Dividers Figure 26. CDCE62005 Smart Multiplexer The CDCE62005 Smart Multiplexer Block provides the ability to divide the primary and secondary UIB or to disconnect a UIB from the first state of the smart multiplexer altogether. Table 18. CDCE62005 Pre-Divider Settings Primary Pre-Divider Secondary Pre-Divider Bit Name DIV2PRIY DIV2PRIX Bit Name DIV2SECY DIV2SECX Register.Bit 0.1 0.0 Divide Ratio Register.Bit 1.1 1.0 Divide Ratio Hi-Z Hi-Z (1) This implementation does not include a phase build-out mechanism. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

CL 8□pF CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Table 18. CDCE62005 Pre-Divider Settings (continued) Primary Pre-Divider Secondary Pre-Divider Bit Name DIV2PRIY DIV2PRIX Bit Name DIV2SECY DIV2SECX Register.Bit 0.1 0.0 Divide Ratio Register.Bit 1.1 1.0 Divide Ratio Reserved Reserved The CDCE62005 provides a Reference Divider that divides the clock exiting the first multiplexer stage; thus dividing the primary (PRI_IN) or the secondary input (SEC_IN). Table 19. CDCE62005 Reference Divider Settings Reference Divider Bit Name REFDIV2 REFDIV1 REFDIV0 Divide Ratio Register.Bit 3.0 2.1 2.0 Auxiliary Input Port The auxiliary input on the CDCE62005 is designed to connect to an AT-Cut Crystal with a total load capacitance(C L of to 10pF. One side of the crystal connects to Ground while the other side connects to the Auxiliary input of the device. The circuit works optimally between to 40MHz but it can accept crystals from to 42MHz. Since the Auxiliary input operates between and V with a crystal, it can accept single-ended signals (e.g. LVCMOS). Electrically, it is equivalent to an LVCMOS input buffer with 10pf of input capacitance. Figure 27. CDCE62005 Auxiliary Input Port Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Internal Clock Distribution Bus PRI_IN SEC_IN SMART _MUX SYNTH Sync Pulse Enable LVDSClock□Divider□Module 0 - 4 LVPECL Output MUX Control Output□Buffer□Control 5 4 Registers 0 - 4 22 21 Registers 0 - 4 2324252627 CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 The output block includes five identical output channels. Each output channel comprises an output multiplexer, a clock divider module, and a universal output buffer as shown in Figure Figure 28. CDCE62005 Output Channel Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com Output Multiplexer Control The Clock Divider Module receives the clock selected by the output multiplexer. The output multiplexer selects from one of four clock sources available on the Internal Clock Distribution. For a PRI_IN, SEC_IN, and SMART_MUX, see Figure For a SYNTH, see Figure Table 20. CDCE62005 Output Multiplexer Control Settings OUTPUT MULTIPLEXER CONTROL Register n 0,1,2,3,4) OUTMUXnSELX OUTMUXnSELY n.4 n.5 CLOCK SOURCE SELECTED PRI_IN SEC_IN SMART_MUX SYNTH Output Buffer Control Each of the five output channels includes a programmable output buffer; supporting LVPECL, LVDS, and LVCMOS modes. Table lists the settings required to configure the CDCE62005 for each output type. Registers through correspond to Output Channels through respectively. Table 21. CDCE62005 Output Buffer Control Settings OUTPUT BUFFER CONTROL Register n 0,1,2,3,4) OUTPUT TYPE CMOSMODEnPX CMOSMODEnPY CMOSMODEnNX CMOSMODEnNY OUTBUFSELnX OUTBUFSELnY n.22 n.23 n.24 n.25 n.26 n.27 LVPECL LVDS See LVCMOS Output Buffer Configuration Settings LVCMOS OFF Output Buffer Control LVCMOS Configurations A LVCMOS output configuration requires additional configuration data. In the single ended configuration, each Output Channel provides a pair of outputs. The CDCE62005 supports four modes of operation for single ended outputs as listed in Table Table 22. LVCMOS Output Buffer Configuration Settings OUTPUT BUFFER CONTROL LVCMOS CONFIGURATION Register n 0,1,2,3,4) Output Pin Output Mode Type CMOSMODEnPX CMOSMODEnPY CMOSMODEnNX CMOSMODEnNY OUTBUFSELnX OUTBUFSELnY n.22 n.23 n.24 n.25 n.26 n.27 X X LVCMOS Negative Active Non-inverted X X LVCMOS Negative Hi-Z X X LVCMOS Negative Active Non-inverted X X LVCMOS Negative Low X X LVCMOS Positive Active Non-inverted X X LVCMOS Positive Hi-Z X X LVCMOS Positive Active Non-inverted X X LVCMOS Positive Low Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Output□Divider (7-bits) Digital□Phase Adjust (7-bits) Sync Pulse (internally□generated ) Enable From Output MUX To Output Buffer Registers 0 - 4 Registers 0 - 4 789101112 Registers 0 - 4 141516171819 /2-/5 /1 - /8 /2 From Output MUX To Output Buffer Registers 0 - 4 Registers 0 - 4 1819 0□1 1□0 0□0 Prescaler Integer□Divider 151713 Registers 0 - 4 CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Output Dividers Figure shows that each output channel provides a 7-bit divider and digital phase adjust block. Table lists the divide ratios supported by the output divider for each output channel. Figure illustrates the output divider architecture in detail. The Prescaler provides an array of low noise dividers with duty cycle correction. The Integer Divider includes a final divide by two stage which is used to correct the duty cycle of the stage. The output divider s maximum input frequency is limited to 1.175GHz. If the divider is bypassed (divide ratio then the maximum frequency of the output channel is 1.5GHz. Figure 29. CDCE62005 Output Divider and Phase Adjust Figure 30. CDCE62005 Output Divider Architecture Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com Table23. CDCE62005 Output Divider Settings OUTPUT DIVIDER n SETTINGSRegister n 0,1,2,3,4) Output Phase* Output Divide Ratio Multiplexer Integer Divider Prescaler OUTnDIVSEL OutnDIVSEL0 OUTnDIVSEL6 OUTnDIVSEL5 OUTnDIVSEL4 OUTnDIVSEL3 OUTnDIVSEL2 OUTnDIVSEL1 Output Channels Auxiliary n.19 n.18 n.17 n.16 n.15 n.14 n.13 n.20 Prescaler Setting Integer Divider Setting Cycles Degree 0-4 Output X X X X X X X OFF OFF OFF OFF 0.5 180 2 3 0.5 180 7560 28.5 10260 12500 8640 32.5 11700 14400 9720 36.5 13140 16200 40.5 14580 18000 19800 12960 48.5 17460 21600 25.5 9540 14040 52.5 18900 23400 56.5 20340 25200 *These columns show that the output divider generates a unique phase lag in the output clock (relative to the clock from the output multiplexer) determined by the divide ratio used. **Output channel or determine the auxiliary output divide ratio. For example, if the auxiliary output is programmed to drive via output and output divider is programmed to divide by then the divide ratio for the auxiliary output will be Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

360( ) /c61 degreesStepsize deg OutputDivide Ratio (3) ( ) f/c61 ClockINStepsize sec OutputDivide Ratio (4) /1 - /80 Digital□Phase Adjust (7-bits) Clock IN (from□Smart□MUX ) To□Output□Buffer Clock□IN Output□Divider (no□adjust ) Output□Divider (phase□adjust ) Start□Divider 360( ) 11.25 /32/c61 /c61 /c176Stepsize deg Step (5) CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Digital Phase Adjust Figure provides an overview of the Digital Phase Adjust feature. The output divider includes a coarse phase adjust that shifts the divided clock signal that drives the output buffer. Essentially, the Digital Phase Adjust timer delays when the output divider starts dividing; thereby shifting the phase of the output clock. The phase adjust resolution is a function of the divide function. Coarse phase adjust parameters include: Number of Phase Delay Steps the number of phase delay steps available is equal to the divide ratio selected. For example, if a Divide by is selected, then the Digital Phase Adjust can be programmed to select when the output divider changes state based upon selecting one of the four counts on the input. Figure shows an example of divide by in which there are rising edges of Clock IN at which the output divider changes state (this particular example shows the fourth edge shifting the output by one fourth of the period of the output). Phase Delay Step Size the step size is determined by the number of phase delay steps according to the following equations: Figure 31. CDCE62005 Phase Adjust Phase Adjust example Given: Output Frequency: 30.72 MHz VCO Operating Frequency: 1966.08 MHz Prescaler Divider Setting: Output Divider Setting: The tables that follow provide a list of valid register settings for the digital phase adjust blocks. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay 1 0 0 0 0 0 0 0 0 18 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (2π/18) 0 0 0 0 0 0 1 (2π/2) 0 0 0 0 0 1 0 2(2π/18) 3 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3(2π/18) 0 0 0 0 0 0 1 (2π/3) 0 0 0 1 0 0 1 4(2π/18) 0 0 0 0 0 1 0 2(2π/3) 0 0 0 1 0 1 0 5(2π/18) 4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 6(2π/18) 0 0 0 0 0 0 1 (2π/4) 0 0 1 0 0 0 1 7(2π/18) 0 0 0 0 0 1 0 2(2π/4) 0 0 1 0 0 1 0 8(2π/18) 0 0 0 0 0 1 1 3(2π/4) 0 0 1 1 0 0 0 9(2π/18) 5 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 10(2π/18) 0 0 0 0 0 0 1 (2π/5) 0 0 1 1 0 1 0 1 1(2π/18) 0 0 0 0 0 1 0 2(2π/5) 0 1 0 0 0 0 0 12(2π/18) 0 0 0 0 0 1 1 3(2π/5) 0 1 0 0 0 0 1 13(2π/18) 0 0 0 0 1 0 0 4(2π/5) 0 1 0 0 0 1 0 14(2π/18) 6 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 15(2π/18) 0 0 0 0 0 0 1 (2π/6) 0 1 0 1 0 0 1 16(2π/18) 0 0 0 0 0 1 0 2(2π/6) 0 1 0 1 0 1 0 17(2π/18) 1 0 0 0 0 0 0 3(2π/6) 20 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 4(2π/6) 0 0 0 0 0 0 1 (2π/20) 1 0 0 0 0 1 0 5(2π/6) 0 0 0 0 0 1 0 2(2π/20) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3(2π/20) 0 0 0 0 0 0 1 (2π/8) 0 0 0 0 1 0 0 4(2π/20) 0 0 0 0 0 1 0 2(2π/8) 0 0 0 1 0 0 0 5(2π/20) 0 0 0 0 0 1 1 3(2π/8) 0 0 0 1 0 0 1 6(2π/20) 1 0 0 0 0 0 0 4(2π/8) 0 0 0 1 0 1 0 7(2π/20) 1 0 0 0 0 0 1 5(2π/8) 0 0 0 1 0 1 1 8(2π/20) 1 0 0 0 0 1 0 6(2π/8) 0 0 0 1 1 0 0 9(2π/20) 1 0 0 0 0 1 1 7(2π/8) 0 0 1 0 0 0 0 10(2π/20) 10 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1(2π/20) 0 0 0 0 0 0 1 (2π/10) 0 0 1 0 0 1 0 12(2π/20) 0 0 0 0 0 1 0 2(2π/10) 0 0 1 0 0 1 1 13(2π/20) 0 0 0 0 0 1 1 3(2π/10) 0 0 1 0 1 0 0 14(2π/20) 0 0 0 0 1 0 0 4(2π/10) 0 0 1 1 0 0 0 15(2π/20) 1 0 0 0 0 0 0 5(2π/10) 0 0 1 1 0 0 1 16(2π/20) 1 0 0 0 0 0 1 6(2π/10) 0 0 1 1 0 1 0 17(2π/20) 1 0 0 0 0 1 0 7(2π/10) 0 0 1 1 0 1 1 18(2π/20) 1 0 0 0 0 1 1 8(2π/10) 0 0 1 1 1 0 0 19(2π/20) 1 0 0 0 1 0 0 9(2π/10) 24 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (2π/24) 0 0 0 0 0 0 1 (2π/12) 0 0 0 0 0 1 0 2(2π/24) 0 0 0 0 0 1 0 2(2π/12) 0 0 0 0 0 1 1 3(2π/24) 0 0 0 1 0 0 0 3(2π/12) 0 0 0 1 0 0 0 4(2π/24) 0 0 0 1 0 0 1 4(2π/12) 0 0 0 1 0 0 1 5(2π/24) 0 0 0 1 0 1 0 5(2π/12) 0 0 0 1 0 1 0 6(2π/24) 0 0 1 0 0 0 0 6(2π/12) 0 0 0 1 0 1 1 7(2π/24) 0 0 1 0 0 0 1 7(2π/12) 0 0 1 0 0 0 0 8(2π/24) 0 0 1 0 0 1 0 8(2π/12) 0 0 1 0 0 0 1 9(2π/24) 0 0 1 1 0 0 0 9(2π/12) 0 0 1 0 0 1 0 10(2π/24) 0 0 1 1 0 0 1 10(2π/12) 0 0 1 0 0 1 1 1 1(2π/24) 0 0 1 1 0 1 0 1 1(2π/12) 0 0 1 1 0 0 0 12(2π/24) 16 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 13(2π/24) 0 0 0 0 0 0 1 (2π/16) 0 0 1 1 0 1 0 14(2π/24) 0 0 0 0 0 1 0 2(2π/16) 0 0 1 1 0 1 1 15(2π/24) 0 0 0 0 0 1 1 3(2π/16) 0 1 0 0 0 0 0 16(2π/24) 0 0 0 1 0 0 0 4(2π/16) 0 1 0 0 0 0 1 17(2π/24) 0 0 0 1 0 0 1 5(2π/16) 0 1 0 0 0 1 0 18(2π/24) 0 0 0 1 0 1 0 6(2π/16) 0 1 0 0 0 1 1 19(2π/24) 0 0 0 1 0 1 1 7(2π/16) 0 1 0 1 0 0 0 20(2π/24) 0 0 1 0 0 0 0 8(2π/16) 0 1 0 1 0 0 1 21(2π/24) 0 0 1 0 0 0 1 9(2π/16) 0 1 0 1 0 1 0 22(2π/24) 0 0 1 0 0 1 0 10(2π/16) 0 1 0 1 0 1 1 23(2π/24) 0 0 1 0 0 1 1 1 1(2π/16) 0 0 1 1 0 0 0 12(2π/16) 0 0 1 1 0 0 1 13(2π/16) 0 0 1 1 0 1 0 14(2π/16) 0 0 1 1 0 1 1 15(2π/16) CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Table 24. CDCE62005 Output Coarse Phase Adjust Settings (1) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay 28 0 0 0 0 0 0 0 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (2π/28) 0 0 0 0 0 0 1 (2π/32) 0 0 0 1 0 0 0 2(2π/28) 0 0 0 0 0 1 0 2(2π/32) 0 0 0 1 0 0 1 3(2π/28) 0 0 0 0 0 1 1 3(2π/32) 0 0 1 0 0 0 0 4(2π/28) 0 0 0 1 0 0 0 4(2π/32) 0 0 1 0 0 0 1 5(2π/28) 0 0 0 1 0 0 1 5(2π/32) 0 0 1 1 0 0 0 6(2π/28) 0 0 0 1 0 1 0 6(2π/32) 0 0 1 1 0 0 1 7(2π/28) 0 0 0 1 0 1 1 7(2π/32) 0 1 0 0 0 0 0 8(2π/28) 0 0 1 0 0 0 0 8(2π/32) 0 1 0 0 0 0 1 9(2π/28) 0 0 1 0 0 0 1 9(2π/32) 0 1 0 1 0 0 0 10(2π/28) 0 0 1 0 0 1 0 10(2π/32) 0 1 0 1 0 0 1 1 1(2π/28) 0 0 1 0 0 1 1 1 1(2π/32) 0 1 1 0 0 0 0 12(2π/28) 0 0 1 1 0 0 0 12(2π/32) 0 1 1 0 0 0 1 13(2π/28) 0 0 1 1 0 0 1 13(2π/32) 1 0 0 0 0 0 0 14(2π/28) 0 0 1 1 0 1 0 14(2π/32) 1 0 0 0 0 0 1 15(2π/28) 0 0 1 1 0 1 1 15(2π/32) 1 0 0 1 0 0 0 16(2π/28) 0 1 0 0 0 0 0 16(2π/32) 1 0 0 1 0 0 1 17(2π/28) 0 1 0 0 0 0 1 17(2π/32) 1 0 1 0 0 0 0 18(2π/28) 0 1 0 0 0 1 0 18(2π/32) 1 0 1 0 0 0 1 19(2π/28) 0 1 0 0 0 1 1 19(2π/32) 1 0 1 1 0 0 0 20(2π/28) 0 1 0 1 0 0 0 20(2π/32) 1 0 1 1 0 0 1 21(2π/28) 0 1 0 1 0 0 1 21(2π/32) 1 1 0 0 0 0 0 22(2π/28) 0 1 0 1 0 1 0 22(2π/32) 1 1 0 0 0 0 1 23(2π/28) 0 1 0 1 0 1 1 23(2π/32) 1 1 0 1 0 0 0 24(2π/28) 0 1 1 0 0 0 0 24(2π/32) 1 1 0 1 0 0 1 25(2π/28) 0 1 1 0 0 0 1 25(2π/32) 1 1 1 0 0 0 0 26(2π/28) 0 1 1 0 0 1 0 26(2π/32) 1 1 1 0 0 0 1 27(2π/28) 0 1 1 0 0 1 1 27(2π/32) 30 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 28(2π/32) 0 0 0 0 0 0 1 (2π/30) 0 1 1 1 0 0 1 29(2π/32) 0 0 0 0 0 1 0 2(2π/30) 0 1 1 1 0 1 0 30(2π/32) 0 0 0 0 0 1 1 3(2π/30) 0 1 1 1 0 1 1 31(2π/32) 0 0 0 0 1 0 0 4(2π/30) 36 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5(2π/30) 0 0 0 0 0 0 1 (2π/36) 0 0 0 1 0 0 1 6(2π/30) 0 0 0 0 0 1 0 2(2π/36) 0 0 0 1 0 1 0 7(2π/30) 0 0 0 1 0 0 0 3(2π/36) 0 0 0 1 0 1 1 8(2π/30) 0 0 0 1 0 0 1 4(2π/36) 0 0 0 1 1 0 0 9(2π/30) 0 0 0 1 0 1 0 5(2π/36) 0 0 1 0 0 0 0 10(2π/30) 0 0 1 0 0 0 0 6(2π/36) 0 0 1 0 0 0 1 1 1(2π/30) 0 0 1 0 0 0 1 7(2π/36) 0 0 1 0 0 1 0 12(2π/30) 0 0 1 0 0 1 0 8(2π/36) 0 0 1 0 0 1 1 13(2π/30) 0 0 1 1 0 0 0 9(2π/36) 0 0 1 0 1 0 0 14(2π/30) 0 0 1 1 0 0 1 10(2π/36) 0 0 1 1 0 0 0 15(2π/30) 0 0 1 1 0 1 0 1 1(2π/36) 0 0 1 1 0 0 1 16(2π/30) 0 1 0 0 0 0 0 12(2π/36) 0 0 1 1 0 1 0 17(2π/30) 0 1 0 0 0 0 1 13(2π/36) 0 0 1 1 0 1 1 18(2π/30) 0 1 0 0 0 1 0 14(2π/36) 0 0 1 1 1 0 0 19(2π/30) 0 1 0 1 0 0 0 15(2π/36) 0 1 0 0 0 0 0 20(2π/30) 0 1 0 1 0 0 1 16(2π/36) 0 1 0 0 0 0 1 21(2π/30) 0 1 0 1 0 1 0 17(2π/36) 0 1 0 0 0 1 0 22(2π/30) 1 0 0 0 0 0 0 18(2π/36) 0 1 0 0 0 1 1 23(2π/30) 1 0 0 0 0 0 1 19(2π/36) 0 1 0 0 1 0 0 24(2π/30) 1 0 0 0 0 1 0 20(2π/36) 0 1 0 1 0 0 0 25(2π/30) 1 0 0 1 0 0 0 21(2π/36) 0 1 0 1 0 0 1 26(2π/30) 1 0 0 1 0 0 1 22(2π/36) 0 1 0 1 0 1 0 27(2π/30) 1 0 0 1 0 1 0 23(2π/36) 0 1 0 1 0 1 1 28(2π/30) 1 0 1 0 0 0 0 24(2π/36) 0 1 0 1 1 0 0 29(2π/30) 1 0 1 0 0 0 1 25(2π/36) 1 0 1 0 0 1 0 26(2π/36) 1 0 1 1 0 0 0 27(2π/36) 1 0 1 1 0 0 1 28(2π/36) 1 0 1 1 0 1 0 29(2π/36) 1 1 0 0 0 0 0 30(2π/36) 1 1 0 0 0 0 1 31(2π/36) 1 1 0 0 0 1 0 32(2π/36) 1 1 0 1 0 0 0 33(2π/36) 1 1 0 1 0 0 1 34(2π/36) 1 1 0 1 0 1 0 35(2π/36) CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Table 25. CDCE62005 Output Coarse Phase Adjust Settings (2) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay 40 0 0 0 0 0 0 0 0 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (2π/40) 0 0 0 0 0 0 1 (2π/48) 0 0 0 0 0 1 0 2(2π/40) 0 0 0 0 0 1 0 2(2π/48) 0 0 0 0 0 1 1 3(2π/40) 0 0 0 0 0 1 1 3(2π/48) 0 0 0 0 1 0 0 4(2π/40) 0 0 0 1 0 0 0 4(2π/48) 0 0 0 1 0 0 0 5(2π/40) 0 0 0 1 0 0 1 5(2π/48) 0 0 0 1 0 0 1 6(2π/40) 0 0 0 1 0 1 0 6(2π/48) 0 0 0 1 0 1 0 7(2π/40) 0 0 0 1 0 1 1 7(2π/48) 0 0 0 1 0 1 1 8(2π/40) 0 0 1 0 0 0 0 8(2π/48) 0 0 0 1 1 0 0 9(2π/40) 0 0 1 0 0 0 1 9(2π/48) 0 0 1 0 0 0 0 10(2π/40) 0 0 1 0 0 1 0 10(2π/48) 0 0 1 0 0 0 1 1 1(2π/40) 0 0 1 0 0 1 1 1 1(2π/48) 0 0 1 0 0 1 0 12(2π/40) 0 0 1 1 0 0 0 12(2π/48) 0 0 1 0 0 1 1 13(2π/40) 0 0 1 1 0 0 1 13(2π/48) 0 0 1 0 1 0 0 14(2π/40) 0 0 1 1 0 1 0 14(2π/48) 0 0 1 1 0 0 0 15(2π/40) 0 0 1 1 0 1 1 15(2π/48) 0 0 1 1 0 0 1 16(2π/40) 0 1 0 0 0 0 0 16(2π/48) 0 0 1 1 0 1 0 17(2π/40) 0 1 0 0 0 0 1 17(2π/48) 0 0 1 1 0 1 1 18(2π/40) 0 1 0 0 0 1 0 18(2π/48) 0 0 1 1 1 0 0 19(2π/40) 0 1 0 0 0 1 1 19(2π/48) 0 1 0 0 0 0 0 20(2π/40) 0 1 0 1 0 0 0 20(2π/48) 0 1 0 0 0 0 1 21(2π/40) 0 1 0 1 0 0 1 21(2π/48) 0 1 0 0 0 1 0 22(2π/40) 0 1 0 1 0 1 0 22(2π/48) 0 1 0 0 0 1 1 23(2π/40) 0 1 0 1 0 1 1 23(2π/48) 0 1 0 0 1 0 0 24(2π/40) 1 0 0 0 0 0 0 24(2π/48) 0 1 0 1 0 0 0 25(2π/40) 1 0 0 0 0 0 1 25(2π/48) 0 1 0 1 0 0 1 26(2π/40) 1 0 0 0 0 1 0 26(2π/48) 0 1 0 1 0 1 0 27(2π/40) 1 0 0 0 0 1 1 27(2π/48) 0 1 0 1 0 1 1 28(2π/40) 1 0 0 1 0 0 0 28(2π/48) 0 1 0 1 1 0 0 29(2π/40) 1 0 0 1 0 0 1 29(2π/48) 0 1 1 0 0 0 0 30(2π/40) 1 0 0 1 0 1 0 30(2π/48) 0 1 1 0 0 0 1 31(2π/40) 1 0 0 1 0 1 1 31(2π/48) 0 1 1 0 0 1 0 32(2π/40) 1 0 1 0 0 0 0 32(2π/48) 0 1 1 0 0 1 1 33(2π/40) 1 0 1 0 0 0 1 33(2π/48) 0 1 1 0 1 0 0 34(2π/40) 1 0 1 0 0 1 0 34(2π/48) 0 1 1 1 0 0 0 35(2π/40) 1 0 1 0 0 1 1 35(2π/48) 0 1 1 1 0 0 1 36(2π/40) 1 0 1 1 0 0 0 36(2π/48) 0 1 1 1 0 1 0 37(2π/40) 1 0 1 1 0 0 1 37(2π/48) 0 1 1 1 0 1 1 38(2π/40) 1 0 1 1 0 1 0 38(2π/48) 0 1 1 1 1 0 0 39(2π/40) 1 0 1 1 0 1 1 39(2π/48) 42 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 40(2π/48) 0 0 0 0 0 0 1 (2π/42) 1 1 0 0 0 0 1 41(2π/48) 0 0 0 0 0 1 0 2(2π/42) 1 1 0 0 0 1 0 42(2π/48) 0 0 0 1 0 0 0 3(2π/42) 1 1 0 0 0 1 1 43(2π/48) 0 0 0 1 0 0 1 4(2π/42) 1 1 0 1 0 0 0 44(2π/48) 0 0 0 1 0 1 0 5(2π/42) 1 1 0 1 0 0 1 45(2π/48) 0 0 1 0 0 0 0 6(2π/42) 1 1 0 1 0 1 0 46(2π/48) 0 0 1 0 0 0 1 7(2π/42) 1 1 0 1 0 1 1 47(2π/48) 0 0 1 0 0 1 0 8(2π/42) 0 0 1 1 0 0 0 9(2π/42) 0 0 1 1 0 0 1 10(2π/42) 0 0 1 1 0 1 0 1 1(2π/42) 0 1 0 0 0 0 0 12(2π/42) 0 1 0 0 0 0 1 13(2π/42) 0 1 0 0 0 1 0 14(2π/42) 0 1 0 1 0 0 0 15(2π/42) 0 1 0 1 0 0 1 16(2π/42) 0 1 0 1 0 1 0 17(2π/42) 0 1 1 0 0 0 0 18(2π/42) 0 1 1 0 0 0 1 19(2π/42) 0 1 1 0 0 1 0 20(2π/42) 1 0 0 0 0 0 0 21(2π/42) 1 0 0 0 0 0 1 22(2π/42) 1 0 0 0 0 1 0 23(2π/42) 1 0 0 1 0 0 0 24(2π/42) 1 0 0 1 0 0 1 25(2π/42) 1 0 0 1 0 1 0 26(2π/42) 1 0 1 0 0 0 0 27(2π/42) 1 0 1 0 0 0 1 28(2π/42) 1 0 1 0 0 1 0 29(2π/42) 1 0 1 1 0 0 0 30(2π/42) 1 0 1 1 0 0 1 31(2π/42) 1 0 1 1 0 1 0 32(2π/42) 1 1 0 0 0 0 0 33(2π/42) 1 1 0 0 0 0 1 34(2π/42) 1 1 0 0 0 1 0 35(2π/42) 1 1 0 1 0 0 0 36(2π/42) 1 1 0 1 0 0 1 37(2π/42) 1 1 0 1 0 1 0 38(2π/42) 1 1 1 0 0 0 0 39(2π/42) 1 1 1 0 0 0 1 40(2π/42) 1 1 1 0 0 1 0 41(2π/42) CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Table 26. CDCE62005 Output Coarse Phase Adjust Settings (3) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay 50 0 0 0 0 0 0 0 0 56 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (2π/50) 0 0 0 0 0 0 1 (2π/56) 0 0 0 0 0 1 0 2(2π/50) 0 0 0 0 0 1 0 2(2π/56) 0 0 0 0 0 1 1 3(2π/50) 0 0 0 0 0 1 1 3(2π/56) 0 0 0 0 1 0 0 4(2π/50) 0 0 0 1 0 0 0 4(2π/56) 0 0 0 1 0 0 0 5(2π/50) 0 0 0 1 0 0 1 5(2π/56) 0 0 0 1 0 0 1 6(2π/50) 0 0 0 1 0 1 0 6(2π/56) 0 0 0 1 0 1 0 7(2π/50) 0 0 0 1 0 1 1 7(2π/56) 0 0 0 1 0 1 1 8(2π/50) 0 0 1 0 0 0 0 8(2π/56) 0 0 0 1 1 0 0 9(2π/50) 0 0 1 0 0 0 1 9(2π/56) 0 0 1 0 0 0 0 10(2π/50) 0 0 1 0 0 1 0 10(2π/56) 0 0 1 0 0 0 1 1 1(2π/50) 0 0 1 0 0 1 1 1 1(2π/56) 0 0 1 0 0 1 0 12(2π/50) 0 0 1 1 0 0 0 12(2π/56) 0 0 1 0 0 1 1 13(2π/50) 0 0 1 1 0 0 1 13(2π/56) 0 0 1 0 1 0 0 14(2π/50) 0 0 1 1 0 1 0 14(2π/56) 0 0 1 1 0 0 0 15(2π/50) 0 0 1 1 0 1 1 15(2π/56) 0 0 1 1 0 0 1 16(2π/50) 0 1 0 0 0 0 0 16(2π/56) 0 0 1 1 0 1 0 17(2π/50) 0 1 0 0 0 0 1 17(2π/56) 0 0 1 1 0 1 1 18(2π/50) 0 1 0 0 0 1 0 18(2π/56) 0 0 1 1 1 0 0 19(2π/50) 0 1 0 0 0 1 1 19(2π/56) 0 1 0 0 0 0 0 20(2π/50) 0 1 0 1 0 0 0 20(2π/56) 0 1 0 0 0 0 1 21(2π/50) 0 1 0 1 0 0 1 21(2π/56) 0 1 0 0 0 1 0 22(2π/50) 0 1 0 1 0 1 0 22(2π/56) 0 1 0 0 0 1 1 23(2π/50) 0 1 0 1 0 1 1 23(2π/56) 0 1 0 0 1 0 0 24(2π/50) 0 1 1 0 0 0 0 24(2π/56) 1 0 0 0 0 0 0 25(2π/50) 0 1 1 0 0 0 1 25(2π/56) 1 0 0 0 0 0 1 26(2π/50) 0 1 1 0 0 1 0 26(2π/56) 1 0 0 0 0 1 0 27(2π/50) 0 1 1 0 0 1 1 27(2π/56) 1 0 0 0 0 1 1 28(2π/50) 1 0 0 0 0 0 0 28(2π/56) 1 0 0 0 1 0 0 29(2π/50) 1 0 0 0 0 0 1 29(2π/56) 1 0 0 1 0 0 0 30(2π/50) 1 0 0 0 0 1 0 30(2π/56) 1 0 0 1 0 0 1 31(2π/50) 1 0 0 0 0 1 1 31(2π/56) 1 0 0 1 0 1 0 32(2π/50) 1 0 0 1 0 0 0 32(2π/56) 1 0 0 1 0 1 1 33(2π/50) 1 0 0 1 0 0 1 33(2π/56) 1 0 0 1 1 0 0 34(2π/50) 1 0 0 1 0 1 0 34(2π/56) 1 0 1 0 0 0 0 35(2π/50) 1 0 0 1 0 1 1 35(2π/56) 1 0 1 0 0 0 1 36(2π/50) 1 0 1 0 0 0 0 36(2π/56) 1 0 1 0 0 1 0 37(2π/50) 1 0 1 0 0 0 1 37(2π/56) 1 0 1 0 0 1 1 38(2π/50) 1 0 1 0 0 1 0 38(2π/56) 1 0 1 0 1 0 0 39(2π/50) 1 0 1 0 0 1 1 39(2π/56) 1 0 1 1 0 0 0 40(2π/50) 1 0 1 1 0 0 0 40(2π/56) 1 0 1 1 0 0 1 41(2π/50) 1 0 1 1 0 0 1 41(2π/56) 1 0 1 1 0 1 0 42(2π/50) 1 0 1 1 0 1 0 42(2π/56) 1 0 1 1 0 1 1 43(2π/50) 1 0 1 1 0 1 1 43(2π/56) 1 0 1 1 1 0 0 44(2π/50) 1 1 0 0 0 0 0 44(2π/56) 1 1 0 0 0 0 0 45(2π/50) 1 1 0 0 0 0 1 45(2π/56) 1 1 0 0 0 0 1 46(2π/50) 1 1 0 0 0 1 0 46(2π/56) 1 1 0 0 0 1 0 47(2π/50) 1 1 0 0 0 1 1 47(2π/56) 1 1 0 0 0 1 1 48(2π/50) 1 1 0 1 0 0 0 48(2π/56) 1 1 0 0 1 0 0 49(2π/50) 1 1 0 1 0 0 1 49(2π/56) 1 1 0 1 0 1 0 50(2π/56) 1 1 0 1 0 1 1 51(2π/56) 1 1 1 0 0 0 0 52(2π/56) 1 1 1 0 0 0 1 53(2π/56) 1 1 1 0 0 1 0 54(2π/56) 1 1 1 0 0 1 1 55(2π/56) CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Table 27. CDCE62005 Output Coarse Phase Adjust Settings (4) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay 60 0 0 0 0 0 0 0 0 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (2π/60) 0 0 0 0 0 0 1 (2π/64) 0 0 0 0 0 1 0 2(2π/60) 0 0 0 0 0 1 0 2(2π/64) 0 0 0 0 0 1 1 3(2π/60) 0 0 0 0 0 1 1 3(2π/64) 0 0 0 0 1 0 0 4(2π/60) 0 0 0 1 0 0 0 4(2π/64) 0 0 0 1 0 0 0 5(2π/60) 0 0 0 1 0 0 1 5(2π/64) 0 0 0 1 0 0 1 6(2π/60) 0 0 0 1 0 1 0 6(2π/64) 0 0 0 1 0 1 0 7(2π/60) 0 0 0 1 0 1 1 7(2π/64) 0 0 0 1 0 1 1 8(2π/60) 0 0 1 0 0 0 0 8(2π/64) 0 0 0 1 1 0 0 9(2π/60) 0 0 1 0 0 0 1 9(2π/64) 0 0 1 0 0 0 0 10(2π/60) 0 0 1 0 0 1 0 10(2π/64) 0 0 1 0 0 0 1 1 1(2π/60) 0 0 1 0 0 1 1 1 1(2π/64) 0 0 1 0 0 1 0 12(2π/60) 0 0 1 1 0 0 0 12(2π/64) 0 0 1 0 0 1 1 13(2π/60) 0 0 1 1 0 0 1 13(2π/64) 0 0 1 0 1 0 0 14(2π/60) 0 0 1 1 0 1 0 14(2π/64) 0 0 1 1 0 0 0 15(2π/60) 0 0 1 1 0 1 1 15(2π/64) 0 0 1 1 0 0 1 16(2π/60) 0 1 0 0 0 0 0 16(2π/64) 0 0 1 1 0 1 0 17(2π/60) 0 1 0 0 0 0 1 17(2π/64) 0 0 1 1 0 1 1 18(2π/60) 0 1 0 0 0 1 0 18(2π/64) 0 0 1 1 1 0 0 19(2π/60) 0 1 0 0 0 1 1 19(2π/64) 0 1 0 0 0 0 0 20(2π/60) 0 1 0 1 0 0 0 20(2π/64) 0 1 0 0 0 0 1 21(2π/60) 0 1 0 1 0 0 1 21(2π/64) 0 1 0 0 0 1 0 22(2π/60) 0 1 0 1 0 1 0 22(2π/64) 0 1 0 0 0 1 1 23(2π/60) 0 1 0 1 0 1 1 23(2π/64) 0 1 0 0 1 0 0 24(2π/60) 0 1 1 0 0 0 0 24(2π/64) 0 1 0 1 0 0 0 25(2π/60) 0 1 1 0 0 0 1 25(2π/64) 0 1 0 1 0 0 1 26(2π/60) 0 1 1 0 0 1 0 26(2π/64) 0 1 0 1 0 1 0 27(2π/60) 0 1 1 0 0 1 1 27(2π/64) 0 1 0 1 0 1 1 28(2π/60) 0 1 1 1 0 0 0 28(2π/64) 0 1 0 1 1 0 0 29(2π/60) 0 1 1 1 0 0 1 29(2π/64) 1 0 0 0 0 0 0 30(2π/60) 0 1 1 1 0 1 0 30(2π/64) 1 0 0 0 0 0 1 31(2π/60) 0 1 1 1 0 1 1 31(2π/64) 1 0 0 0 0 1 0 32(2π/60) 1 0 0 0 0 0 0 32(2π/64) 1 0 0 0 0 1 1 33(2π/60) 1 0 0 0 0 0 1 33(2π/64) 1 0 0 0 1 0 0 34(2π/60) 1 0 0 0 0 1 0 34(2π/64) 1 0 0 1 0 0 0 35(2π/60) 1 0 0 0 0 1 1 35(2π/64) 1 0 0 1 0 0 1 36(2π/60) 1 0 0 1 0 0 0 36(2π/64) 1 0 0 1 0 1 0 37(2π/60) 1 0 0 1 0 0 1 37(2π/64) 1 0 0 1 0 1 1 38(2π/60) 1 0 0 1 0 1 0 38(2π/64) 1 0 0 1 1 0 0 39(2π/60) 1 0 0 1 0 1 1 39(2π/64) 1 0 1 0 0 0 0 40(2π/60) 1 0 1 0 0 0 0 40(2π/64) 1 0 1 0 0 0 1 41(2π/60) 1 0 1 0 0 0 1 41(2π/64) 1 0 1 0 0 1 0 42(2π/60) 1 0 1 0 0 1 0 42(2π/64) 1 0 1 0 0 1 1 43(2π/60) 1 0 1 0 0 1 1 43(2π/64) 1 0 1 0 1 0 0 44(2π/60) 1 0 1 1 0 0 0 44(2π/64) 1 0 1 1 0 0 0 45(2π/60) 1 0 1 1 0 0 1 45(2π/64) 1 0 1 1 0 0 1 46(2π/60) 1 0 1 1 0 1 0 46(2π/64) 1 0 1 1 0 1 0 47(2π/60) 1 0 1 1 0 1 1 47(2π/64) 1 0 1 1 0 1 1 48(2π/60) 1 1 0 0 0 0 0 48(2π/64) 1 0 1 1 1 0 0 49(2π/60) 1 1 0 0 0 0 1 49(2π/64) 1 1 0 0 0 0 0 50(2π/60) 1 1 0 0 0 1 0 50(2π/64) 1 1 0 0 0 0 1 51(2π/60) 1 1 0 0 0 1 1 51(2π/64) 1 1 0 0 0 1 0 52(2π/60) 1 1 0 1 0 0 0 52(2π/64) 1 1 0 0 0 1 1 53(2π/60) 1 1 0 1 0 0 1 53(2π/64) 1 1 0 0 1 0 0 54(2π/60) 1 1 0 1 0 1 0 54(2π/64) 1 1 0 1 0 0 0 55(2π/60) 1 1 0 1 0 1 1 55(2π/64) 1 1 0 1 0 0 1 56(2π/60) 1 1 1 0 0 0 0 56(2π/64) 1 1 0 1 0 1 0 57(2π/60) 1 1 1 0 0 0 1 57(2π/64) 1 1 0 1 0 1 1 58(2π/60) 1 1 1 0 0 1 0 58(2π/64) 1 1 0 1 1 0 0 59(2π/60) 1 1 1 0 0 1 1 59(2π/64) 1 1 1 1 0 0 0 60(2π/64) 1 1 1 1 0 0 1 61(2π/64) 1 1 1 1 0 1 0 62(2π/64) 1 1 1 1 0 1 1 63(2π/64) CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Table 28. CDCE62005 Output Coarse Phase Adjust Settings (5) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay Divide□RatioPHnADGC6PHnADGC5PHnADGC4PHnADGC3PHnADGC2PHnADGC1PHnADGC0Phase□Delay 70 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (2π/70) 0 0 0 0 0 0 1 (2π/80) 0 0 0 0 0 1 0 2(2π/70) 0 0 0 0 0 1 0 2(2π/80) 0 0 0 0 0 1 1 3(2π/70) 0 0 0 0 0 1 1 3(2π/80) 0 0 0 0 1 0 0 4(2π/70) 0 0 0 0 1 0 0 4(2π/80) 0 0 0 1 0 0 0 5(2π/70) 0 0 0 1 0 0 0 5(2π/80) 0 0 0 1 0 0 1 6(2π/70) 0 0 0 1 0 0 1 6(2π/80) 0 0 0 1 0 1 0 7(2π/70) 0 0 0 1 0 1 0 7(2π/80) 0 0 0 1 0 1 1 8(2π/70) 0 0 0 1 0 1 1 8(2π/80) 0 0 0 1 1 0 0 9(2π/70) 0 0 0 1 1 0 0 9(2π/80) 0 0 1 0 0 0 0 10(2π/70) 0 0 1 0 0 0 0 10(2π/80) 0 0 1 0 0 0 1 1 1(2π/70) 0 0 1 0 0 0 1 1 1(2π/80) 0 0 1 0 0 1 0 12(2π/70) 0 0 1 0 0 1 0 12(2π/80) 0 0 1 0 0 1 1 13(2π/70) 0 0 1 0 0 1 1 13(2π/80) 0 0 1 0 1 0 0 14(2π/70) 0 0 1 0 1 0 0 14(2π/80) 0 0 1 1 0 0 0 15(2π/70) 0 0 1 1 0 0 0 15(2π/80) 0 0 1 1 0 0 1 16(2π/70) 0 0 1 1 0 0 1 16(2π/80) 0 0 1 1 0 1 0 17(2π/70) 0 0 1 1 0 1 0 17(2π/80) 0 0 1 1 0 1 1 18(2π/70) 0 0 1 1 0 1 1 18(2π/80) 0 0 1 1 1 0 0 19(2π/70) 0 0 1 1 1 0 0 19(2π/80) 0 1 0 0 0 0 0 20(2π/70) 0 1 0 0 0 0 0 20(2π/80) 0 1 0 0 0 0 1 21(2π/70) 0 1 0 0 0 0 1 21(2π/80) 0 1 0 0 0 1 0 22(2π/70) 0 1 0 0 0 1 0 22(2π/80) 0 1 0 0 0 1 1 23(2π/70) 0 1 0 0 0 1 1 23(2π/80) 0 1 0 0 1 0 0 24(2π/70) 0 1 0 0 1 0 0 24(2π/80) 0 1 0 1 0 0 0 25(2π/70) 0 1 0 1 0 0 0 25(2π/80) 0 1 0 1 0 0 1 26(2π/70) 0 1 0 1 0 0 1 26(2π/80) 0 1 0 1 0 1 0 27(2π/70) 0 1 0 1 0 1 0 27(2π/80) 0 1 0 1 0 1 1 28(2π/70) 0 1 0 1 0 1 1 28(2π/80) 0 1 0 1 1 0 0 29(2π/70) 0 1 0 1 1 0 0 29(2π/80) 0 1 1 0 0 0 0 30(2π/70) 0 1 1 0 0 0 0 30(2π/80) 0 1 1 0 0 0 1 31(2π/70) 0 1 1 0 0 0 1 31(2π/80) 0 1 1 0 0 1 0 32(2π/70) 0 1 1 0 0 1 0 32(2π/80) 0 1 1 0 0 1 1 33(2π/70) 0 1 1 0 0 1 1 33(2π/80) 0 1 1 0 1 0 0 34(2π/70) 0 1 1 0 1 0 0 34(2π/80) 1 0 0 0 0 0 0 35(2π/70) 0 1 1 1 0 0 0 35(2π/80) 1 0 0 0 0 0 1 36(2π/70) 0 1 1 1 0 0 1 36(2π/80) 1 0 0 0 0 1 0 37(2π/70) 0 1 1 1 0 1 0 37(2π/80) 1 0 0 0 0 1 1 38(2π/70) 0 1 1 1 0 1 1 38(2π/80) 1 0 0 0 1 0 0 39(2π/70) 0 1 1 1 1 0 0 39(2π/80) 1 0 0 1 0 0 0 40(2π/70) 1 0 0 0 0 0 0 40(2π/80) 1 0 0 1 0 0 1 41(2π/70) 1 0 0 0 0 0 1 41(2π/80) 1 0 0 1 0 1 0 42(2π/70) 1 0 0 0 0 1 0 42(2π/80) 1 0 0 1 0 1 1 43(2π/70) 1 0 0 0 0 1 1 43(2π/80) 1 0 0 1 1 0 0 44(2π/70) 1 0 0 0 1 0 0 44(2π/80) 1 0 1 0 0 0 0 45(2π/70) 1 0 0 1 0 0 0 45(2π/80) 1 0 1 0 0 0 1 46(2π/70) 1 0 0 1 0 0 1 46(2π/80) 1 0 1 0 0 1 0 47(2π/70) 1 0 0 1 0 1 0 47(2π/80) 1 0 1 0 0 1 1 48(2π/70) 1 0 0 1 0 1 1 48(2π/80) 1 0 1 0 1 0 0 49(2π/70) 1 0 0 1 1 0 0 49(2π/80) 1 0 1 1 0 0 0 50(2π/70) 1 0 1 0 0 0 0 50(2π/80) 1 0 1 1 0 0 1 51(2π/70) 1 0 1 0 0 0 1 51(2π/80) 1 0 1 1 0 1 0 52(2π/70) 1 0 1 0 0 1 0 52(2π/80) 1 0 1 1 0 1 1 53(2π/70) 1 0 1 0 0 1 1 53(2π/80) 1 0 1 1 1 0 0 54(2π/70) 1 0 1 0 1 0 0 54(2π/80) 1 1 0 0 0 0 0 55(2π/70) 1 0 1 1 0 0 0 55(2π/80) 1 1 0 0 0 0 1 56(2π/70) 1 0 1 1 0 0 1 56(2π/80) 1 1 0 0 0 1 0 57(2π/70) 1 0 1 1 0 1 0 57(2π/80) 1 1 0 0 0 1 1 58(2π/70) 1 0 1 1 0 1 1 58(2π/80) 1 1 0 0 1 0 0 59(2π/70) 1 0 1 1 1 0 0 59(2π/80) 1 1 0 1 0 0 0 60(2π/70) 1 1 0 0 0 0 0 60(2π/80) 1 1 0 1 0 0 1 61(2π/70) 1 1 0 0 0 0 1 61(2π/80) 1 1 0 1 0 1 0 62(2π/70) 1 1 0 0 0 1 0 62(2π/80) 1 1 0 1 0 1 1 63(2π/70) 1 1 0 0 0 1 1 63(2π/80) 1 1 0 1 1 0 0 64(2π/70) 1 1 0 0 1 0 0 64(2π/80) 1 1 1 0 0 0 0 65(2π/70) 1 1 0 1 0 0 0 65(2π/80) 1 1 1 0 0 0 1 66(2π/70) 1 1 0 1 0 0 1 66(2π/80) 1 1 1 0 0 1 0 67(2π/70) 1 1 0 1 0 1 0 67(2π/80) 1 1 1 0 0 1 1 68(2π/70) 1 1 0 1 0 1 1 68(2π/80) 1 1 1 0 1 0 0 69(2π/70) 1 1 0 1 1 0 0 69(2π/80) 1 1 1 0 0 0 0 70(2π/80) 1 1 1 0 0 0 1 71(2π/80) 1 1 1 0 0 1 0 72(2π/80) 1 1 1 0 0 1 1 73(2π/80) 1 1 1 0 1 0 0 74(2π/80) 1 1 1 1 0 0 0 75(2π/80) 1 1 1 1 0 0 1 76(2π/80) 1 1 1 1 0 1 0 77(2π/80) 1 1 1 1 0 1 1 78(2π/80) 1 1 1 1 1 0 0 79(2π/80) CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Table 29. CDCE62005 Output Coarse Phase Adjust Settings (6) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Output□Divider 2 Output□Divider 3 AUX OUT Register 6 Register 6 CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Auxiliary Output Figure shows the auxiliary output port. Table lists how the auxiliary output port is controlled. The output buffer supports a maximum output frequency of 250 MHz and drives at LVCMOS levels. Refer to Table for the list of divider settings that establishes the output frequency. Figure 32. CDCE62005 Auxiliary Output Table 30. CDCE62005 Auxiliary Output Settings Bit Name AUXFEEDSEL AUXOUTEN AUX OUTPUT SOURCE Register.Bit 6.25 6.24 X OFF Divider Divider Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

/2,/3,/4,/5 Input□Divider /1 - /256 Internal Clock Distribution Bus SMART _MUX SYNTH Internal Clock Distribution Bus 50 kHz – 400 kHz /8 - /1280 Feedback□Divider

1.75 GHz –

Charge□Pump□Current Register 5 15161718192021 Input□Divider□Settings Register 6 Prescaler Register 6 45678910 Feedback□Divider Register 6 131415 Feedback□Bypass□Divider Register 7 1234567 89101112131415 1617181920 Loop□Filter□Settings Register 6 VCO□Select CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Figure provides an overview of the CDCE62005 synthesizer block. The Synthesizer Block provides a Phase Locked Loop, a partially integrated programmable loop filter, and two Voltage Controlled Oscillators (VCO). The synthesizer block generates an output clock called SYNTH and drives it onto the Internal Clock Distribution Bus. Figure 33. CDCE62005 Synthesizer Block Input Divider The Input Divider divides the clock signal selected by the Smart Multiplexer (see Table and presents the divided signal to the Phase Frequency Detector Charge Pump of the frequency synthesizer. Table 31. CDCE62005 Input Divider Settings INPUT DIVIDER SETTINGS DIVIDE SELINDIV7 SELINDIV6 SELINDIV5 SELINDIV4 SELINDIV3 SELINDIV2 SELINDIV1 SELINDIV0 RATIO 5.21 5.20 5.19 5.18 5.17 5.16 5.15 5.14 256 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com Feedback and Feedback Bypass Divider Table shows how to configure the Feedback divider for various divide values Table 32. CDCE62005 Feedback Divider Settings FEEDBACK DIVIDER DIVIDE SELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0 RATIO 6.10 6.9 9.8 6.7 6.6 6.5 6.4 6.3 100 108 112 120 128 140 144 160 168 180 192 200 216 224 240 252 256 280 288 300 320 336 360 384 392 400 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

www.ti.com SCAS862 NOVEMBER 2008 Table 32. CDCE62005 Feedback Divider Settings (continued) FEEDBACK DIVIDER DIVIDE SELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0 RATIO 6.10 6.9 9.8 6.7 6.6 6.5 6.4 6.3 420 432 448 480 500 504 512 560 576 588 600 640 672 700 720 768 784 800 840 896 960 980 1024 1120 1280 Table shows how to configure the Feedback Bypass Divider. Table 33. CDCE62005 Feedback Bypass Divider Settings FEEDBACK BYPASS DIVIDER SELBPDIV2 SELBPDIV1 SELBPDIV0 DIVIDE RATIO 6.15 6.14 6.13 RESERVED 1(bypass) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com VCO Select Table illustrates how to control the dual voltage controlled oscillators. Table 34. CDCE62005 VCO Select VCO Select VCO CHARACTERISTICS SELVCO Bit Name Register.Bit 6.0 VCO Range Fmin (MHz) Fmax (MHz) Low 1750 2046 High 2040 2356 Prescaler Table shows how to configure the prescaler. Table 35. CDCE62005 Prescaler Settings SETTINGS SELPRESCB SELPRESCA DIVIDE RATIO 6.2 6.1 Charge Pump Current Settings Table provides the settings for the charge pump: Table 36. CDCD62005 Charge Pump Settings CHARGE PUMP SETTINGS CHARGE PUMP ICPSEL3 ICPSEL2 ICPSEL1 ICPSEL0 Bit Name CURRENT Register.Bit 6.19 6.18 6.17 6.16 µ A 100 µ A 150 µ A 200 µ A 300 µ A 400 µ A 600 µ A 750 µ A mA 1.25 mA 1.5 mA mA 2.5 mA mA 3.5 mA 3.75 mA Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

EXT_LFNEXT_LFP externalinternal externalinternal VB R2 C2 R2C2 r.0r . 1r . base Ceq Ceq Req Req (a) (b) (c) (d) CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Loop Filter Figure depicts the loop filter topology of the CDCE62005. It facilitates both internal and external implementations providing optimal flexibility. Figure 34. CDCE62005 Loop Filter Topology Internal Loop Filter Component Configuration Figure contains five different loop filter components with programmable values: C1, C2, R2, R3, and C3. Table shows that the CDCE62005 uses one of four different types of circuit implementation (shown in Figure for each of the internal loop filter components. Table 37. CDCE62005 Loop Filter Component Implementation Type Implementation Type Component Control Bits Used (see Figure a a c d b Figure 35. CDCE62005 Internal Loop Filter Component Schematics Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com Table 38. CDCE62005 Internal Loop Filter Settings SETTINGS Bit Name EXLFSEL LFRCSEL14 LFRCSEL13 LFRCSEL12 LFRCSEL11 LFRCSEL10 Capacitor Value 37.5 pF 21.5 pF pF 6.5 pF 1.5 pF Register.Bit 6.26 7.14 7.13 7.12 7.11 7.10 Capacitor Value X X X X X External Loop Filter pF 1.5 pF 6.5 pF pF pF 11.5 pF 16.5 pF pF 21.5 pF pF pF 70.5 pF 75.5 pF pF Table 39. CDCE62005 Internal Loop Filter Settings SETTINGS Bit Name EXLFSEL LFRCSEL4 LFRCSEL3 LFRCSEL2 LFRCSEL1 LFRCSEL0 Capacitor Value 226 pF 123 pF pF pF 12.5 pF Register.Bit 6.26 7.4 7.3 7.2 7.1 7.0 Capacitor Value External Loop Filter pF 12.5 pF pF 37.5 pF pF 99.5 pF 112 pF 124.5 pF 123 pF 135.5 pF 436 pF 448.5 pF 461 pF 473.5 pF Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

www.ti.com SCAS862 NOVEMBER 2008 Table 40. CDCE62005 Internal Loop Filter Settings SETTINGS Bit Name EXLFSEL LFRCSEL9 LFRCSEL8 LFRCSEL7 LFRCSEL6 LFRCSEL5 Resistor Value 56.4 k 38.2 k k k k Register.Bit 6.26 7.9 7.8 7.7 7.6 7.5 Resistor Value Ω X X X X X External Loop Filter 127.6 123.6 118.6 114.6 107.6 103.6 98.6 94.6 89.4 85.4 Table 41. CDCE62005 Internal Loop Filter Settings SETTINGS Bit Name EXLFSEL LFRCSEL18 LFRCSEL17 LFRCSEL16 LFRCSEL15 Capacitor Value pF 19.5 pF 5.5 pF 2.5 pF Register.Bit 6.26 7.18 7.17 7.16 7.15 Capacitor Value X X X X External Loop Filter pF 2.5 pF 5.5 pF pF 19.5 pF pF pF 27.5 pF pF 87.5 pF 104.5 pF 107 pF 110 pF 112.5 pF Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

www.ti.com Table 42. CDCE62005 Internal Loop Filter Settings SETTINGS Bit Name EXLFSEL LFRCSEL20 LFRCSEL19 Resistor Value k k Register.Bit 6.26 7.20 7.19 Resistor Value Ω X X External Loop Filter External Loop Filter Component Configuration To implement an external loop filter, set EXLFSEL bit (6.26) high. Setting all of the control switches low that control capacitors and (see Table remove them from the loop filter circuit. This is necessary for an external loop filter implementation. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

From□Input□Divider From□Feedback Divider To□Loop□Filter From□Input□Divider From□Feedback Divider Locked UnlockedFrom□Input□Divider From□Feedback Divider 25 24 23 22 Register 5 Lock Detect Window (Max) Lock Detect Window Adjust (a) (b) 27 26 From□Digital Lock Detector PLL_LOCK 1 = Locked O = Unlocked (c) CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Digital Lock Detect The CDCE62005 provides both an analog and a digital lock detect circuit. With respect to lock detect, two signals whose phase difference is less than a prescribed amount are locked otherwise they are unlocked The phase frequency detector charge pump compares the clock provided by the input divider and the feedback divider; using the input divider as the phase reference. The digital lock detect circuit implements a programmable lock detect window. Table shows an overview of how to configure the digital lock detect feature. When selecting the digital PLL lock option, the PLL_LOCK pin will possibly jitter several times between lock and out of lock until the PLL achieves a stable lock. If desired, choosing a wide loop bandwidth and a high number of successive clock cycles virtually eliminates this characteristic. PLL_LOCK will return to out of lock, if just one cycle is outside the lock detect window or if a cycle slip occurs. Figure 36. CDCE62005 Digital Lock Detect Table 43. CDCE62005 Digital Lock Detect Control DIGITAL LOCK DETECT Bit Name ADLOCK LOCKDET LOCKW(3) LOCKW(2) LOCKW(1) LOCKW(0) Register.Bit 5.27 5.26 5.25 5.24 5.23 5.22 Lock Detect Window X X X X X Analog Lock X X X X X cycle in lock window triggers a lock continuous cycles in lock window triggers a X X X X X lock X Narrow Window X One step wider than narrow window X Two steps wider than narrow window X Three steps wider than narrow window X Four steps wider than narrow window X Widest Window X X X Reserved Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

1/c61 /c180 /c180Vout i t C (6) /c180/c61 outV Ct i (7) 3.3 1.8 1.8 10 164110 /c61 /c61 /c92 /c64 /c61 /c180/c61 /c64 cc H Out C nF V V V V V nt μs μ 5 pF Locked Unlocked 80k 110 uA 110 uA Vcc PFD/ CP From□Input□Divider From□Feedback□Divider C PLL_LOCK To□HostLock_I CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Analog Lock Detect Figure shows the Analog Lock Detect circuit. Depending upon the phase relationship of the two signals presented at the PFD/CP inputs, the lock detect circuit either charges (if the PLL is locked) or discharges (if PLL is unlocked) the circuit shown via 100 µ A current sources. An external capacitor determines the sensitivity of the lock detect circuit. The value of the capacitor determines the rate of change of the voltage presented on the output pin PLL_LOCK and hence how quickly the PLL_LOCK output toggles based on a change of PLL locked status. The PLL_LOCK pin is an analog output in analog lock detect mode. Solving for t yields: V H 0.55 V CC V L 0.35 V CC For Example, let: Figure 37. CDCE62005 Analog Lock Detect Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Die□Temperature□vs□Total□Device□Power 100 125 0 1 2 3 4 Power□(W) Die□Temp□(C) JEDEC□0□LFM□25□C JEDEC□100□LFM□25□C RL 0□LFM□25□C RL 100□LFM□25□C JEDEC□0□LFM□85□C JEDEC□100□LFM□85□C RL 0□LFM□85□C RL 100□LFM□85□C JEDEC□0□LFM□25□C JEDEC□100□LFM□85□C RL 0□LFM□85□C RL 100□LFM□85□C RL 100□LFM□25□C CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 The CDCE62005 is a high performance device, therefore careful attention must be paid to device configuration and printed circuit board layout with respect to power consumption. Table provides the power consumption for the individual blocks within the CDCE62005. To estimate total power consumption, calculate the sum of the products of the number of blocks used and the power dissipated of each corresponding block. Table 44. CDCE62005 Power Consumption Internal Block (Power at 3.3V) Power Dissipated per Block Number of Blocks per Device Input Circuit mW PLL and VCO Core 746 mW Output Divider 185 mW Output Buffer LVPECL) 116 mW Output Buffer (LVDS) mW Output Buffer (LVCMOS) mW This power estimate determines the degree of thermal management required for a specific design. Employing the thermally enhanced printed circuit board layout shown in Figure insures that the thermal performance curves shown in Figure apply. Observing good thermal layout practices enables the thermal pad on the backside of the QFN-48 package to provide a good thermal path between the die contained within the package and the ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance connection to the ground plane is essential. Figure shows a layout optimized for good thermal performance and a good power supply connection as well. The filled via patter facilitates both considerations. Finally, the recommended layout achieves θ JA 27.3 C/W in still air and 20.3 C/W in an environment with 100 LFM airflow if implemented on a JEDEC compliant thermal test board.. Figure 38. CDCE62005 Die Temperature vs Device Power Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Solder□Mask No□Solder□Mask Thermal□Vias QFN-48 Thermal□Slug (package□bottom) Thermal Dissipation Pad (back□side) Internal Ground Plane Internal Power Plane Component□Side Back□Side CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Figure 39. CDCE62005 Recommended PCB Layout Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Back□Side Component□Side CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 CDCE62005 Power Supply Bypassing Recommended Layout Figure shows two conceptual layouts detailing recommended placement of power supply bypass capacitors. If the capacitors are mounted on the back side, 0402 components can be employed; however, soldering to the Thermal Dissipation Pad can be difficult. For component side mounting, use 0201 body size capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Ground the other side of the capacitor using a low impedance connection to the ground plane. Figure 40. CDCE62005 Power Supply Bypassing Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

/1 - /80 U0P U0N PRI_IN SEC_IN /1 - /80 U4P U4N Divide by 1: Up□to 1500 MHz Otherwise: Up□to 1175 MHz Up□to 5 Outputs: LVPECL or□LVDS Up□to 10 Outputs: LVCMOS XT AL / AUX _IN Output Divider 0 U0P U0N PFD / CP Prescaler Feedback Divider Input Divider Smart MUX Output Divider 4 U4P U4N CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Fan-out Buffer Each output of the CDCE62005 can be configured as a fan-out buffer (divider bypassed) or fan-out buffer with divide and skew control functionality. Figure 41. CDCE62005 Fan-out Buffer Mode Clock Generator The CDCE62005 can generate low noise clocks from a single crystal or crystal oscillator as follows: Figure 42. CDCE62005 Clock Generator Mode Jitter Cleaner Mixed Mode (1) The following table presents a common scenario. The CDCE62005 must generate several integer-related clocks from a reference that has traversed a backplane. In order for jitter cleaning to take place, the phase noise of the on-board clock path must be better than that of the incoming clock. The designer must pay attention to the optimization of the loop bandwidth of the synthesizer and understand the phase noise profiles of the oscillators involved. Further, other devices on the card require clocks at frequencies not related to the backplane clock. The system requires combinations of differential and single-ended clocks in specific formats with specific phase relationships. (1) CLOCK FREQUENCY INPUT/OUTPUT FORMAT NUMBER CDCE62005 PORT COMMENT 10.000 MHz Input LVDS SEC_IN Low end crystal oscillator 30.72 MHz Input LVDS PRI_IN Reference from backplane 122.88 MHz Output LVDS SERDES Clock 491.52 MHz Output LVPECL ASIC 245.76 MHz Output LVPECL FPGA 30.72 MHz Outputs LVCMOS ASIC 10.000 MHz Outputs LVCMOS CPU, DSP (1) Pay special attention when using the universal inputs with two different clock sources. Two clocks derived from the same source may use the internal bias generator and internal termination network without jitter performance degradation. However, if their origin is from different sources (e.g. two independent oscillators) then sharing the internal bias generator can degrade jitter performance significantly. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

/1:/2:HiZ /1:/2:HiZ Prescaler Feedback Divider Input Divider Reference Divider

30.72 MHz

10.00 MHz

122 .88 MHz 491 .52 MHz 245 .76 MHz

10 MHz

/c233 /c249/c61 /c234 /c250 /c235 /c251 jitter in total SNR πf jitter (8) /c40 /c41 /c40 /c41 2 2/c61 /c43total ADC CLKjitter jitter jitter (9) 6.02 1.76/c61 /c43ADCSNR N (10) CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Figure 43. CDCE62005 Jitter Cleaner Example Clocking ADCs with the CDCE62005 High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation trend often causes engineers working in communications system design to encounter the term clock limited performance Therefore, it is important to understand the impact of clock jitter on ADC performance. Equation shows the relationship of data converter signal to noise ratio (SNR) to total jitter. Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample clock: With respect to an ADC with N-bits of resolution, ignoring total jitter, DNL, and input noise, the following equation shows the relationship between resolution and SNR: Figure plots Equation and Equation for constant values of total jitter. When used in conjunction with most ADCs, the CDCE62005 supports a total jitter performance value of ps. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Data□Converter□Jitter□Requirements 100 110 120 130 140 1 10 100 1000 10000 SNR□(dB) 50□fs 100□fs 350□fs 1□ps SERDES Cleaned□Clock Data CDCE 62005 Recovered□Clock ASIC□Clock ASIC CDCE62005 SCAS862 NOVEMBER 2008 www.ti.com Figure 44. Data Converter Jitter Requirements CDCE62005 SERDES Startup Mode A common scenario involves a host communicating to a satellite system via a high-speed wired communications link. Typical communications media might be a cable, backplane, or fiber. The reference clock for the satellite system is embedded in the high speed link. This reference clock must be recovered by the SERDES, however, the recovered clock contains unacceptable levels of jitter due to a degradation of SNR associated with transmission over the media. At system startup, the satellite system must self-configure prior to the recovery and cleanup of the reference clock provided by the host. Furthermore, upon loss of the communication link with the host, the satellite system must continue to operate albeit with limited functionality. Figure shows a block diagram of an optical based system with such a mechanism that takes advantage of the CDCE62005: Figure 45. CDCE62005 SERDES Startup Overview The functionality provided by the Smart Multiplexer provides a straightforward implementation of a SERDES clock link. The Auxiliary Input provides a startup clock because it connects to a crystal. The on-chip EEPROM determines the default configuration at power-up; therefore, the CDCE62005 requires no host communication to begin cleaning the recovered clock once it is available. The CDCE62005 immediately begins clocking the satellite components including the SERDES using the crystal as a clock source and a frequency reference. After the SERDES recovers the clock, the CDCE62005 removes the jitter via the on-chip synthesizer/loop filter. The recovered clock from the communications link becomes the frequency reference for the satellite system after the smart multiplexer automatically switches over to it. The CDCE62005 applies the cleaned clock to the recovered clock input on the SERDES; thereby establishing a reliable communications link between host and satellite systems. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s) CDCE62005

Output□Blocks Interface Control Block To□Satellite System Components Recovered□Clock Cleaned□Clock SERDES Start-up/ Back-up Clock CDCE62005 www.ti.com SCAS862 NOVEMBER 2008 Figure 46. CDCE62005 SERDES Startup Mode Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) CDCE62005

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCE62005RGZR ACTIVE QFN RGZ 48 2500 TBD Call TI Call TI CDCE62005RGZT ACTIVE QFN RGZ 48 250 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 25-Nov-2008 Addendum-Page 1

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