CDCE421RGER

CDCE421_15 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SCAS842,B]
• PDF pages: 24

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Output□Enable/Programming□Interface□and□EEPROM□for□Configuration□Settings Crystal Oscillator Input Feedback Divider PFD/Charge□Pump Loop□Filter VCO□1 VCO□2 Prescaler Output□DividerLVPECL or□LVDS X-tal CE SDATA CLK NCLK B0216-01 CDCE421 www.ti.com SCAS842B APRIL 2007 REVISED JANUARY 2009 Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator Differential Low-Voltage Positive Emitter-Coupled Logic (LVPECL) Output, Single 3.3-V Supply 10.9-MHz to 1.175-GHz Frequency Range High-Performance Clock Generator Two Fully Integrated Voltage-Controlled Incorporating Crystal-Oscillator Circuitry With Oscillators (VCOs) Support Wide Output Integrated Frequency Synthesizer Frequency Range Low-Output Jitter: As Low as 380 fs (rms Fully Integrated Programmable Loop Filter Integrated Between kHz MHz) Typical Power Consumption: 274 mW in LVDS Low Phase Noise at High Frequency: at 708 Mode and 250 mW in LVPECL Mode MHz it is less than 109 dBc/Hz at 10-kHz and 146 dBc/Hz at 10-MHz Offset from the Carrier Chip-Enable Control Pin Supports Crystal Frequencies Between Simple Serial Interface Allows Programming 27.35 MHz to 38.33 MHz After Manufacturing Output Frequency Ranges from 10.9 MHz up to Integrated On-Chip Nonvolatile Memory 766.7 MHz and from 875.2 MHz up to 1175 MHz (EEPROM) to Store Settings Without the Need to Apply High Voltage to the Device Low-Voltage Differential Signaling (LVDS) Output, 100- Ω Differential Off-Chip QFN24 Package Termination, 10.9-MHz to 400-MHz Frequency ESD Protection Exceeds kV HBM Range Industrial Temperature Range: C to +85 C Low-Cost, High-Frequency Crystal Oscillator Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2007 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DESCRIPTION

fxtal/C0043/C0466OutputDivider FeedbackDivider/C0467/C0032fout (1) Crystal Oscillator Feedback Divider 12,□16,□20□and□32 Output Divider PFD/ Charge□Pump Prescaler 2,□3,□4□and□5 Loop□Filter VCO□1 1890 VCO□2 2200 XIN□1 XIN□2 CE SDATA B0217-01 1-Pin Interface and Control EEPROM LVPCL LVDS CDCE421 SCAS842B APRIL 2007 REVISED JANUARY 2009 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The CDCE421 is a high-performance, low-phase-noise clock generator. It has two fully integrated, low-noise, LC-based voltage controlled oscillators (VCOs) that operate in the 1.750-GHz to 2.350-GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. The output frequency out is proportional to the frequency of the input crystal xtal The prescaler divider, feedback divider, output divider, and VCO selection are what set out with respect to xtal For a desired frequency out look in Table and find the corresponding settings in the same row. Use Equation to calculate the exact crystal oscillator frequency needed for the desired output. Output divider (1) 16, or Feedback divider (2) 12, 16, 20, or (1) Output divider and feedback divider should be from the same row in Table (2) Feedback divider is set automatically with respect to the prescaler setting in Table A high-level block diagram of the CDCE421 is shown in Figure The CDCE421 supports one differential LVDS clock output or one differential LVPECL output. All device settings are programmable through a Texas Instruments proprietary simple serial interface. The device operates in a 3.3-V supply environment and is characterized for operation from C to +85 The CDCE421 is available in a QFN-24 package. Figure High-Level Block Diagram of the CDCE421 In the CDCE421, the feedback divider is set automatically with respect to the prescaler setting. The product of the prescaler and the feedback divider will be either or 64, as shown in Table to keep the control loop stable. Submit Documentation Feedback Copyright 2007 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE421

www.ti.com SCAS842B APRIL 2007 REVISED JANUARY 2009 Table Crystal Frequency Selection and Device Settings REQUIRED INPUT DESIRED OUTPUT CRYSTAL VCO OUTPUT PRESCALER FEEDBACK FREQUENCY (MHz) FREQUENCY (MHz) SELECTION DIVIDER SETTING DIVIDER (1) From To From To 1020.0 1175.0 31.875 36.719 VCO 875.2 (2) 1020.0 27.351 31.875 VCO 650.0 766.7 (2) 32.500 38.333 VCO 583.5 650.0 29.174 32.500 VCO 510.0 587.5 31.875 36.719 VCO 437.6 510.0 27.351 31.875 VCO 408.0 460.0 34.000 38.333 VCO 350.1 408.0 29.174 34.000 VCO 340.0 383.3 34.000 38.333 VCO 291.7 340.0 29.174 34.000 VCO 255.0 293.8 31.875 36.719 VCO 218.8 255.0 27.351 31.875 VCO 204.0 230.0 34.000 38.333 VCO 175.0 204.0 29.174 34.000 VCO 170.0 191.7 34.000 38.333 VCO 145.9 170.0 29.174 34.000 VCO 127.5 146.9 31.875 36.719 VCO 109.4 127.5 27.351 31.875 VCO 102.0 115.0 34.000 38.333 VCO 87.5 102.0 29.174 34.000 VCO 85.0 95.8 34.000 38.333 VCO 72.9 85.0 29.174 34.000 VCO 63.8 73.4 31.875 36.719 VCO 54.7 63.8 27.351 31.875 VCO 51.0 57.5 34.000 38.333 VCO 43.8 51.0 29.174 34.000 VCO 42.5 47.9 34.000 38.333 VCO 36.5 42.5 29.174 34.000 VCO 31.9 36.7 31.875 36.719 VCO 27.4 31.9 27.351 31.875 VCO 25.5 28.8 34.000 38.333 VCO 21.9 25.5 29.174 34.000 VCO 21.3 24.0 34.000 38.333 VCO 18.2 21.3 29.174 34.000 VCO 15.9 18.4 31.875 36.719 VCO 13.7 15.9 27.351 31.875 VCO 12.8 14.4 34.000 38.333 VCO 10.9 12.8 29.174 34.000 VCO (1) The feedback divider is set automatically with respect to the prescaler setting. (2) Discontinuity in frequency range. Copyright 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE421

fxtal/C0043/C0466OutputDivider FeedbackDivider/C0467/C0032fout fxtal/C0043/C04661 20/C0467/C0032622.08/C004331.154 MHz (2) SERIAL INTERFACE AND CONTROL CDCE421 SCAS842B APRIL 2007 REVISED JANUARY 2009 www.ti.com The following example illustrates the procedure to calculate the required AT-cut crystal frequency needed to generate a desired output frequency. Assuming the requirement to generate an output frequency of 622.08 MHz, Table shows that the desired output frequency lies between 583.5 MHz and 680 MHz. REQUIRED INPUT DESIRED OUTPUT CRYSTAL VCO OUTPUT PRESCALER FEEDBACK FREQUENCY (MHz) FREQUENCY (MHz) SELECTION DIVIDER SETTING DIVIDER (1) From To From To 650.0 766.7 32.500 38.333 VCO 583.5 650.0 29.174 32.500 VCO 510.0 587.5 31.875 36.719 VCO (1) The feedback divider is set automatically with respect to the prescaler setting. So this means that the device must be configured with: VCO VCO Output divider Prescaler setting To determine the correct crystal frequency needed to get 622.08 MHz with these settings, substitute values into Equation The AT-cut frequency should be 31.154 MHz (between 29.174 MHz and 32.500 MHz, as shown in Table The CDCE421 uses a unique Texas Instruments proprietary interface protocol that can be configured and programmed via a single input pin to the device. The architecture enables only writing to the device from this input pin. Reading the content of a register can be achieved by sending a read command on the input pin and monitoring the output pins (LVDS or LVPECL). In cases where the output pins cannot be used to read the content, the software controlling the interface must account for what is written to the EEPROM and when it is programmed. Monitoring the outputs verifies the programming modes, and cycling power on the device verifies that the EEPROM is holding the proper configuration. The CDCE421 can be configured and programmed via the SDATA input pin. For this purpose, a square-wave programming sequence must be written to the device as described in the following section. During the EEPROM programming phase, the device requires a stable V CC of V to 3.6 V for secure writing of the EEPROM cells. After each Write to WordX, the written data are latched, made effective, and offer look-ahead before the actual data are stored into the EEPROM. The following table summarizes all valid programming commands. SDATA FUNCTION 1100 Enter Programming Mode (State State 2); bits must be sent in the specified order with the specified timing. Otherwise, a time-out occurs. 1011 Enter Register Read Back Mode bits must be sent in the specified order with the specified timing. Otherwise, a time-out occurs. 000 xxxx xxxx Write to Word0 (State (1) (2) (3) 100 xxxx xxxx Write to Word1 (State (1) (2) (3) 010 xxxx xxxx Write to Word2 (State (1) (2) (3) 110 xxxx xxxx Write to Word3 (State (1) (2) (3) (1) Each rising edge causes a bit to be latched. (2) Between the bits, some longer time delays can occur, but this has no effect on the data. (3) A Write to WordX is expected to be bits long. After the 10th bit, the respective word is latched and its effect can be observed as look-ahead function. Submit Documentation Feedback Copyright 2007 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE421

SDATA = 111011 SDATA = 111 0000 0000 SDATA = 111 1111 0000 SDATA = 111 0000 0000 SDATA = 111 0101 0101 SDATA = 111 1111 1111 SDATA = 001100 SDATA = 100 xxxx□xxxx SDATA = 000 xxxx□xxxx SDATA = 010 xxxx□xxxx SDATA = 110 xxxx□xxxx SDATA = 001 xxxx□xxxx SDATA = 101 xxxx□xxxx Power□Up: Read EEPROM□& Configure State□1:□IDLE Normal Operation State□2: Programming Mode 11□□□Bit Written th 11□□□Bit Written th 11□□□Bit Written th 11□□□Bit Written th 11□□□Bit Written th 11□□□Bit Written th Write WORD□0 Write WORD□1 Write WORD□2 Write WORD□3 Write WORD□4 Write WORD□5 State□4: Programming EEPROM Locking State□3: Programming EEPROM No□Locking th Clock Applied State□5: Read□Back Mode F0016-02 CDCE421 www.ti.com SCAS842B APRIL 2007 REVISED JANUARY 2009 SDATA FUNCTION 001 xxxx xxxx Write to Word4 (State (1) (2) (3) 101 xxxx xxxx Write to Word5 (State (1) (2) (3) 111 xxxx xxxx State machine jump: All other patterns not defined as follows cause an exit to normal mode. 111 1111 0000 Jump: Enter EEPROM programming without EEPROM lock (State State 111 0101 0101 Jump: Enter EEPROM programming with EEPROM lock (State State 111 0000 0000 Jump: Exit EEPROM programming (State or State State NOTE: In States and the signal pin CE is disregarded and has no influence on power down. Figure State Flow-Diagram of Single-Pin Interface Copyright 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE421

www.ti.com Figure shows the timing behavior of data to be written into SDATA. The sequence shown is 1100. If the high period is as short as t this is interpreted as If the high period is as long as t this is interpreted as a This behavior is achieved by shifting the incoming signal SDATA by time t into signal SDATA_DELAYED. As can be seen in Figure SDATA_DELAYED can be used to latch (or strobe) SDATA. The timing specifications for t t t r and t f are shown in Figure MIN TYP MAX UNIT f SDATACLK Repeat frequency of programming kHz t LOW signal: high-pulse duration 0.2 t ms t LOW signal: low-pulse duration while entering programming sequence 0.8 t ms t LOW signal: low-pulse duration while programming bits 0.8 t ms t HIGH signal: high-pulse duration 0.8 t ms t HIGH signal: low-pulse duration while entering programming sequence 0.2 t ms t HIGH signal: low-pulse duration while programming bits 0.2 t ms Time-out during Entering Programming Mode and Enter Read Back Mode t High-pulse or low-pulse duration each must be less than this time; otherwise, µ s time-out will result. t CE-high time before first SDATA can be clocked in t ms t r and t f Rise Time and Fall Time ns t f SDATACLK Figure SDATA/CE Timing Load all the registers in RAM by writing Word0 through Word5, and after going back to State then going to State (programming EEPROM, no locking) or State (programming EEPROM with locking), the

contents

EEPROM. Wait ms in State or State when programming the EEPROM before moving to State (the idle state). NOTE: When writing to the device for functionality testing and verification via the serial bus, only the RAM is being accessed. Submit Documentation Feedback Copyright 2007 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE421

EXAMPLE: Programming Cycle of Six Words and Programming Into EEPROM Enter□Programming□Sequence Word0 After□8□bits,□the□payload data□is□transferred□to the□RAM□and□is□active. Wait□for□at□least 10□ms□before exiting□EEPROM write□phase,□for safe□operation. Payload Word1 Payload Word5 Payload State Machine Jump State Machine Jump State□2 State□3/c174 State□3 State□1/c174 T0043-03 /c183 /c183 /c183 /c183 /c183 /c183 Enter Register Readback Mode and Related Timing Diagram CDCE421 www.ti.com SCAS842B APRIL 2007 REVISED JANUARY 2009 The following sequence shows how to enter programming mode and how the different words can be written. The addressing of Word0 Word5 is shown in bold. After the word address, the payload for the respective word is clocked in. In this example, this is followed by a jump from State State into enter EEPROM programming with EEPROM lock In the EEPROM-programming state, it is necessary to wait at least ms for safe programming. The last command is a jump from State into State (normal operation). Cycle power and verify that the device functions as programmed. Figure Programming Cycle of Six Words and Programming Into EEPROM Similar to the enter programming mode sequence, the enter register read back mode is written into SDATA. After the command has been issued, the SDATA input is reconfigured as clock input. By applying one clock, the EEPROM content is read into shift registers. Now, by further applying clocks at SDATA, the EEPROM content can be clocked out and observed at OUTP/OUTN. There are bits to be clocked out. With the 61st rising clock edge, the OUTP/OUTN pins are reconfigured back into normal operation. Copyright 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE421

Enter□Register Read-Back□Mode Fetch EEPROM Content□With

1 CLK

EEPROM□Content

1 Bit Available After

1 Falling□Edge

60 Falling□Edge

Switches□Back□Into Normal□Operation th Output□Oscillation Output□Oscillation REGISTER DESCRIPTIONS CDCE421 SCAS842B APRIL 2007 REVISED JANUARY 2009 www.ti.com In the following table, the content of the output bit stream is summarized. Important to notice: bit is clocked out first. The default values in register to register are programmed in the EEPROM. OUTPUT BIT STREAM FUNCTION Bits[0:2] Revision identifier (MSB first) Bits[3:8] VCO calibration word Bit[9] EEPROM status: EEPROM has never been written EEPROM has been programmed before Bit[10] EEPROM lock: EEPROM can be rewritten EEPROM is locked, rewriting to the EEPROM is not possible any more Bits[11:18] Storage value, Word5 (MSB first) Bits[19:26] Storage value, Word4 (MSB first) Bits[27:34] Storage value, Word3 (MSB first) Bits[35:42] Storage value, Word2 (MSB first) Bits[43:50] Storage value, Word1 (MSB first) Bits[51:58] Storage value, Word0 (MSB first) Word DEFAULT BIT NAME DESCRIPTION/FUNCTION TYPE VALUE Register selection W Register selection W Register selection W SELVCO VCO select, VCO1, VCO2 W SELPRESC Prescaler setting, bit W SELPRESC Prescaler setting, bit W OUTSEL Output divider select, bit W OUTSEL Output divider select, bit1 W OUTSEL Output divider select, bit W DRVSEL Driver select, LVDS, PECL W TITEST0 Reserved W Divide by value (SELPRESC SELPRESC Divide by (00), (01), (10), (11) Output divider (OUTSEL2, OUTSEL1, OUTSEL0) Divide by (000), (001), (010), (011), (100), (101) Submit Documentation Feedback Copyright 2007 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE421

www.ti.com SCAS842B APRIL 2007 REVISED JANUARY 2009 Word DEFAULT BIT NAME DESCRIPTION/FUNCTION TYPE VALUE Register selection W Register selection W Register selection W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W Word DEFAULT BIT NAME DESCRIPTION/FUNCTION TYPE VALUE Register selection W Register selection W Register selection W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W Word DEFAULT BIT NAME DESCRIPTION/FUNCTION TYPE VALUE Register selection W Register selection W Register selection W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W LFRCSEL Loop filter control settings, bit W ICPSEL Charge pump current sel, bit W ICPSEL Charge pump current sel, bit W ICPSEL Charge pump current sel, bit W ICPSEL Charge pump current sel, bit W TITEST1 Reserved W Copyright 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE421

www.ti.com Word DEFAULT BIT NAME DESCRIPTION/FUNCTION TYPE VALUE Register selection W Register selection W Register selection W CALWRD VCO calibration word, bit W CALWRD VCO calibration word, bit W CALWRD VCO calibration word, bit W CALWRD VCO calibration word, bit W CALWRD VCO calibration word, bit W CALWRD VCO calibration word, bit W CALOVR VCO calibration override W ENCAL Enable VCO calibration W Word DEFAULT BIT NAME DESCRIPTION/FUNCTION TYPE VALUE Register selection W Register selection W Register selection W TITSTCFG TI test use, bit W TITSTCFG TI test use, bit W TITSTCFG TI test use, bit W TITSTCFG TI test use, bit W Not used W Not used W Not used W Not used W Submit Documentation Feedback Copyright 2007 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE421

(QFN24) NC VCC RGE□PACKAGE (TOP VIEW) CDCE421 NC NC XIN□2XIN□1NC NC 24 23 22 21 20 19 NC SDATA 4NC 5NC GND 7 8 9 GND 10 11 OUTP NC NC 18 NC

17 VCC

www.ti.com SCAS842B APRIL 2007 REVISED JANUARY 2009 The CDCE421 is available in a QFN 24-pin package. The QFN package footprint is illustrated in Figure as well as the pad locations and numbers. Figure Pinout of the CDCE421 QFN-24 Package Table shows the pin descriptions for the CDCE421 QFN-24 package. Table CDCE421 Pin Descriptions TERMINAL TERMINAL ESD TYPE NO. PROTECTION Chip enable CE enable the device and the outputs. CE I Y CE disable all current sources; in LVDS mode, LVDSP LVDSN Hi-Z; in LVPECL mode, LVPECLP LVPECLN Hi-Z. GND GND Y Ground No connect 15, Do not connect these pins. Leave them floating. 20, 23,24 High-speed negative differential LVPECL or LVDS outputs. (Outputs are OUTN O Y enabled by CE and selected by the EEPROM configuration registers.) High-speed positive differential LVPECL or LVDS outputs. (Outputs are OUTP O Y enabled by CE and selected by the EEPROM configuration registers.) SDATA I Y Programming pin using TI proprietary interface protocol VCC 16, Power Y 3.3-V power supply In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the XIN I Y other end of the crystal. In LVCMOS input single-ended driven mode, XIN1 XIN GND/NC N (pin 21) acts as an input reference, and XIN2 should connect to GND or it can be left unconnected. Copyright 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE421

(LVPECL OR LVDS) ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING CONDITIONS CDCE421 SCAS842B APRIL 2007 REVISED JANUARY 2009 www.ti.com The CDCE421 device has two sets of output drivers, LVPECL and LVDS, where the outputs are wire-ORed together. Only one output can be selected at a time; the other goes to the high-impedance state (Hi-Z). If the device is configured for an LVPECL, the output buffers go to Hi-Z and the termination resistors determine the state of the output (LVPECLP LVPECLN Hi-Z) in the device disable mode (CE L). If the device is configured in LVDS mode, the outputs go to Hi-Z if the device is disabled (CE L). Over operating free-air temperature range (unless otherwise noted). VALUE UNIT V CC Supply voltage (2) 0.5 to 4.6 V V I Voltage range for all other input pins (2) 0.5 to V CC 0.5 V I O Output current for LVPECL mA Electrostatic discharge (HBM) kV T A Characterized free-air temperature range (no airflow) to +85 C T J Maximum junction temperature +125 C T stg Storage temperature range to +150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. Over operating free-air temperature range (unless otherwise noted). MIN TYP MAX UNIT V CC Supply voltage 3.3 3.6 V T A Ambient temperature (no airflow, no heat sink) +85 C Submit Documentation Feedback Copyright 2007 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE421

www.ti.com SCAS842B APRIL 2007 REVISED JANUARY 2009 Using the recommended operating conditions for the CDCE421 device. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V CC Supply voltage 3.3 3.6 V I VCC(LVDS) Total current LVDS mode 103 mA I VCC(LVPECL) Total current LVPECL mode 110 mA LVDS OUTPUT MODE (see Figure f CLK Output frequency 10.9 400 MHz OD LDVS differential output voltage R L 100 Ω 247 454 mV Δ V OD LVDS VOD magnitude change mV V OS Offset voltage C to C 1.1 1.3 V Δ V OS VOS magnitude change mV t r Output rise time 20% to 80% of V OUTpp 230 ps t f Output fall time 80% to 20% of V OUTpp 230 ps Short V out+ to ground mA I OS Short-circuit output current Short V out to ground mA Duty cycle of the output waveform 45% 55% T J Random jitter 10kHz to 20MHz ps, rms LVPECL OUTPUT MODE (see Figure f CLK Output frequency 10.9 1175 MHz V OH LVPECL high-level output voltage V CC 1.2 V CC 0.81 V V OL LVPECL low-level output voltage V CC 2.17 V CC 1.36 V OD LVPECL differential output voltage 407 mV t r Output rise time 20% to 80% of V OUTpp 230 ps t f Output fall time 80% to 20% of V OUTpp 230 ps Duty cycle of the output waveform 45% 55% T J Random jitter 10kHz to 20MHz ps, rms LVCMOS INPUT V IL,CMOS Low-level CMOS input voltage V CC 3.3 V 0.3 V CC V V IH,CMOS High-level CMOS input voltage V CC 3.3 V 0.7 V CC V I L,CMOS Low- level CMOS input current V CC V CC max, V IL V 200 µ A I H,CMOS High-level CMOS input current V CC V CC min, V IH 3.7 V 200 µ A Copyright 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE421

f − Single-Sideband Frequency − Hz G001 −160 −140 −120 −100 −80 −60 −40 −20 Phase Noise − dBc/Hz 10 100 1k 100M10k 100k 1M 10M CDCE421 SCAS842B APRIL 2007 REVISED JANUARY 2009 www.ti.com If the CDCE421 is being referenced by an external and cleaner LVCMOS input of 35.42 MHz, Figure shows the SSB phase noise plot of the output at 708 MHz from 100 Hz to MHz from the carrier. Note the dependence of output jitter on the input reference jitter. See Figure for test setup. Figure Phase Noise Plot for LVPECL Output at 708 MHz Table Phase Noise Parameters With LVCMOS Input of 35.4 MHz and LVPECL Output at 708 MHz Phase noise specifications under following assumptions: input frequency f 35.42 MHz (VCO prescaler output divider 1), f out 708 MHz (driver mode LVPECL) PARAMETER MIN TYP MAX UNIT phn 100 Phase noise at 100 Hz dBc/Hz phn Phase noise at kHz 105 dBc/Hz phn 10k Phase noise at kHz 109 dBc/Hz phn 100k Phase noise at 100 kHz 114 dBc/Hz phn Phase noise at MHz 126 dBc/Hz phn 10M Phase noise at MHz 146 dBc/Hz phn 20M Phase noise at MHz 146 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 438 fs Submit Documentation Feedback Copyright 2007 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE421

f − Single-Sideband Frequency − Hz G002 −160 −140 −120 −100 −80 −60 −40 −20 Phase Noise − dBc/Hz 10 100 1k 100M10k 100k 1M 10M CDCE421 www.ti.com SCAS842B APRIL 2007 REVISED JANUARY 2009 If the CDCE421 is being referenced by a clean external LVCMOS input of 33.33 MHz, Figure shows the SSB phase noise plot of the output at 400 MHz from 100 Hz to MHz from carrier. See Figure for test setup. Figure Phase Noise Plot for LVDS Output at 400 MHz Table Phase Noise Parameters With LVCMOS Input of 33.33 MHz and LVDS Output at 400 MHz Phase noise specifications under following assumptions: input frequency f 33.33 MHz (VCO prescaler output divider 1), f out 400 MHz (driver mode LVDS) PARAMETER MIN TYP MAX UNIT phn 100 Phase noise at 100 Hz dBc/Hz phn Phase noise at kHz 109 dBc/Hz phn 10k Phase noise at kHz 119 dBc/Hz phn 100k Phase noise at 100 kHz 121 dBc/Hz phn Phase noise at MHz 130 dBc/Hz phn 10M Phase noise at MHz 147 dBc/Hz phn 20M Phase noise at MHz 147 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 409 fs Copyright 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CDCE421

VCC – 2V L VPECL L VPECL 50 /c8750 /c87 S0250-01 LVDS 50 /c87 Phase□Noise Analyzer S0251-01 LVPECL 50 /c87 Phase□Noise Analyzer 150 /c87 150 /c87 CDCE421 SCAS842B APRIL 2007 REVISED JANUARY 2009 www.ti.com Test setups are used to characterize the CDCE421 device in ac and dc terminations. Figure through Figure illustrate all four setups used to terminate the clock signal driven by the device under test. Figure LVDS DC Termination Test Configuration Figure LVPECL DC Termination Test Configuration Figure 10. LVDS AC Termination Test Configuration Figure 11. LVPECL AC Termination Test Configuration Submit Documentation Feedback Copyright 2007 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE421

www.ti.com 1-Nov-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CDCE421RGER NRND VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCE 421 CDCE421RGERG4 NRND VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCE 421 CDCE421RGET NRND VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCE 421 CDCE421RGETG4 NRND VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCE 421 CDCE421Y NRND DIESALE Y 0 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 1-Nov-2015 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCE421RGER VQFN RGE 24 3000 367.0 367.0 35.0 CDCE421RGET VQFN RGE 24 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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