CDCD5704

CDCD5704 TI | Alldatasheet

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PW□PACKAGE (TOP VIEW) P0043-01

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Support: 300-MHz 667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad (Open-Drain) Differential Output Drivers Spread-Spectrum Compatible Clock Input Can Be Distributed to Minimize EMI Differential or Single-Ended Reference Clock Input of 100 MHz or 133 MHz Serial Interface Features: Programmable Frequency Multiplier, Select Any One to Four Outputs and Mode of Operation Supports Frequency Multiplication Factors of: 9/2, 15/2, All PLL Loop Filter Components Are Integrated Low |Cycle-to-Cycle| of Cycle Jitter: ps: 300 635 MHz ps: 636 667 MHz PLLs Are Powered Down if No Valid REF Clock <10 MHz) Is Detected or VDD Is Below 1.6 V Operates From Single 2.5-V Supply 0.125 Packaged in TSSOP-28 Commercial Temperature Range C to C XDR Memory Subsystem and Redwood Logic Interface The CDCD5704 clock generator provides the necessary clock signals to support an XDR memory subsystem and Redwood logic interface using a reference clock input with or without spread-spectrum modulation. Contained in a 28-pin TSSOP package that includes four differential clock outputs, the CDCD5704 provides an off-the-shelf solution for a broad range of high-performance interface applications. The block diagram shows the major components of the CDCD5704, which include a phase-locked loop, a bypass multiplexer, and four differential output buffers (CLK0 to CLK3). All four outputs can be disabled by a logical low at the input of the EN pin. An output is enabled when EN is high and a value of is in its serial interface register (RegA RegD). The PLL receives a reference clock input signal, REFCLK, and outputs a clock signal at a frequency equal to the input frequency times the multiplication factor. The PLL output clock signal is fed to the differential output buffers to drive the enabled clocks. Disabled outputs are set to high impedance. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. Rambus, XDR are trademarks of Rambus Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com B0137-01 REFCLK BYPASS CLK0 VSSP VDDP VDDC VDD VSSC VSS VDD VDDC VDDP CLK0B CLK1 CLK1B CLK2 CLK2B CLK3 CLK3B REFCLKB MUX CLK0 SDA SCL ID0 ID1 CLk1 CLK2 CLK3 EN CLK0 Current□and□Voltage Reference ISET RSET PLL 1 300□MHz□to□667□MHz Power Down Logic Serial□Interface Control□Logic CDCD5704 SCAS823 DECEMBER 2006 The bypass mode routes the input clock REFCLK to the differential output buffers, bypassing the PLL. To ensure that the CDCD5704 clock generator always performs correctly, the device switches off the PLL and the outputs are in the high-impedance state, once the clock input is below MHz. If the supply voltage VDD is less than V PUC all logic gates are reset, the PLL is powered down, and the outputs are in the high-impedance state. Therefore, the device only starts its operation if these minimum requirements are met. Because the CDCD5704 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to the start of stabilization time. The device operates from a single 2.5-V supply voltage. The CDCD5704 device is characterized for operation from C to FUNCTIONAL BLOCK DIAGRAM Submit Documentation Feedback

www.ti.com SERIAL INTERFACE Serial Interface Operation Requirement Serial Interface Device Address CDCD5704 SCAS823 DECEMBER 2006 Table TERMINAL FUNCTIONS TERMINAL TYPE NO. BYPASS Input If the PLL is bypassed and the PLL is switched off. CLK0 Output Output for Clock0 CLK0B Output Complementary output for Clock0 CLK1 Output Output for Clock1 CLK1B Output Complementary output for Clock1 CLK2 Output Output for Clock2 CLK2B Output Complementary output for Clock2 CLK3 Output Output for Clock3 CLK3B Output Complementary output for Clock3 EN Input Output enable; if all outputs are disabled. ID0 Input Device ID, bit ID1 Input Device ID, bit ISET Output Set clock driver current with external resistor REFCLK Input Reference clock input REFCLKB Input Complementary reference clock input SCL Input Serial interface clock, 3.3-V compatible SDA Input Serial interface data, 3.3-V compatible VDD 15, 22, Power 2.5-V power supply for outputs VDDC Power 2.5-V power supply for core VDDP Power 2.5-V power supply for PLL VSS 18, 21, Ground Ground VSSC Ground Ground for core VSSP Ground Ground for PLL The following section describes the serial interface programming. In general, the serial interface slave supports byte-write/-read and word-write/-read protocol as defined in the SMBus or I C specification. The internal timing of the serial interface logic block in the CDCD5704 requires a timing reference derived from the input clock (REFCLK). A reference clock must be present at the REFCLK pin for the serial interface to be operational. W/R ID1 ID0 The device-ID is determined by the external pins ID0 and ID1. They are part of the device 8-bit address. Therefore, four different devices (00, 01, 10, and 11) can be addressed via the same serial interface. The least significant bit of the address designates a write or read operation. R/W Bit: write to CDCD5704 device read from CDCD5704 device Submit Documentation Feedback

www.ti.com Command Code Definition Serial Interface Generic Programming Sequence M0053-01 1 7 1 1 8 1 1 S S Slave Address Wr A Data□Byte A P Start□Condition Sr Repeated□Start□Condition Rd Read□(Bit□Value□=□1) Wr Write□(Bit□Value□=□0) A Acknowledge□(ACK□=□0□and□NACK□=□1) P Stop□Condition PE Packet□Error Master-to-Slave Transmission Slave-to-Master Transmission Byte-Write Programming Sequence Byte-Read Programming Sequence CDCD5704 SCAS823 DECEMBER 2006 Bit (C6:C0) Byte offset for byte-write/-read or word-write/-read operation Command Code for Byte-Write/-Read Hex Code Operation Byte 80h Byte 81h Byte 82h Command Code for Word-Write/-Read Hex Code Operation Word Byte and byte 80h Word Byte and byte 81h S Slave Address Wr A Command Code A Data Byte A P S Slave Address Wr A Command Code A S Slave Address Rd A ... Data Byte A P Submit Documentation Feedback

www.ti.com Word-Write Programming Sequence Word-Read Programming Sequence T0131-01 P S P t(BUS) tw(SCLL) tw(SCLH) tr(SM) tf(SM) th(START) tsu(SDATA) th(SDATA) tsu(STOP)tsu(START) tr(SDATA) tf(SDATA) SCLK SDATA VIH(SM) VIH(SM) VIL(SM) VIL(SM) ABit□7□(MSB) Bit□6 Bit□0□(LSB) CDCD5704 SCAS823 DECEMBER 2006 S Slave Address Wr A Command Code A Data Byte Low A ... Data Byte High A P S Slave Address Wr A Command Code A S Slave Address Rd A ... Data Byte A Data Byte A P Figure Timing Diagram, Serial Control Interface Submit Documentation Feedback

www.ti.com Serial Interface Configuration Command Bitmap Byte Byte Byte CDCD5704 SCAS823 DECEMBER 2006 Bit Bit Name Description/Function Type Power-Up Condition RES Reserved R/W MULT2 Multiplication factor, bit R/W MULT1 Multiplication factor, bit R/W MULT0 Multiplication factor, bit R/W RegA Enable CLK0 R/W RegB Enable CLK1 R/W RegC Enable CLK2 R/W RegD Enable CLK3 R/W Bit Bit Name Description/Function Type Power-Up Condition RES Reserved R/W RES Reserved R/W RES Reserved R/W RES Reserved R/W RES Reserved for vendor option R/W RES Reserved for vendor option R/W RES Reserved for vendor option R/W RegTest Vendor test register. If high, then Vendor Test R/W Bit Bit Name Description/Function Type Power-Up Condition REV0 Device revision, bit R REV0 Device revision, bit R REV0 Device revision, bit R REV0 Device revision, bit R REV0 Device revision, bit R VID2 Vendor ID bit R VID1 Vendor ID bit R VID0 Vendor ID bit R Submit Documentation Feedback

www.ti.com FUNCTIONAL (MHz) Multiplication Mult2 Mult1 Mult0 Factor REFCLK 100 MHz REFCLK 133 MHz 300 400 (1) (1) (1) (1) 400 533 500 667 600 800 (2) 800 (2) (2) 450 600 750 (2) (2) 375 500 (1) Default settings after power up (2) Output at this frequency does not conform to all the ac device characteristics in the Device Characteristics table, or ouput frequency is not supported. EN BYPASS Reg-Test RegA RegB RegC RegD CLK0 CLK1 CLK2 CLK3 L X X X X X X HI-Z HI-Z HI-Z HI-Z H X X X X X RESERVED FOR VENDOR TEST H L X X X X REFCLK REFCLK REFCLK REFCLK H H HI-Z HI-Z HI-Z HI-Z H H PLL CLK HI-Z HI-Z HI-Z H H HI-Z PLL CLK HI-Z HI-Z H H PLL CLK PLL CLK HI-Z HI-Z H H HI-Z HI-Z PLL CLK HI-Z H H PLL CLK HI-Z PLL CLK HI-Z H H HI-Z PLL CLK PLL CLK HI-Z H H PLL CLK PLL CLK PLL CLK HI-Z H H HI-Z HI-Z HI-Z PLL CLK H H PLL CLK HI-Z HI-Z PLL CLK H H HI-Z PLL CLK HI-Z PLL CLK H H PLL CLK PLL CLK HI-Z PLL CLK H H HI-Z HI-Z PLL CLK PLL CLK H H PLL CLK HI-Z PLL CLK PLL CLK H H HI-Z PLL CLK PLL CLK PLL CLK H H (1) (1) (1) (1) (1) PLL CLK PLL CLK PLL CLK PLL CLK (1) Default settings after power up Submit Documentation Feedback

www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS CDCD5704 SCAS823 DECEMBER 2006 over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT V DD Supply voltage range 0.3 to 2.8 V For SCL and SDA 0.3 to 3.6 V I Input voltage range (2) V For all other inputs 0.3 to V DD 0.25 V O Output voltage range (2) 0.5 to V DD 0.5 V I IK Input clamp current, I V I V DD mA I O Continuous output current mA No airflow 94.4 Airflow 150 ft/min 82.8 R θ JA Thermal resistance, junction-to-ambient (3) K/W Airflow 250 ft/min 79.1 Airflow 500 ft/min R θ JC Thermal resistance, junction-to-case (3) No airflow 31.8 K/W R θ JB Thermal resistance, junction-to-board (3) No airflow 68.9 K/W T J Maximum junction temperature 125 C T stg Storage temperature range to 150 C (1) Stresses beyond those listed under absolute maximum rating s may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD and JEDEC2S1P (high-k board). MIN NOM MAX UNIT V DDP Supply voltage for PLL 2.375 2.5 2.625 V V DDC Supply voltage for core 2.375 2.5 2.625 V V DD Supply voltage for clock buffers 2.375 2.5 2.625 V T A Operating free-air temperature C V IL,CLK Low-level input voltage, REFCLK/REFCLKB 0.15 0.15 V V IX,CLK Crossing-point voltage, input voltage threshold, REFCLK/REFCLKB 0.2 0.55 V V IH,CLKD High-level input voltage, REFCLK/REFCLKB 0.6 0.95 V Δ V IX,CLK Difference in crossing-point voltage 0.15 V V IL SE Low-level, single-ended input voltage, REFCLK 0.15 V th SE 0.3 V V th SE Single-ended input-voltage threshold, REFCLK (1) 0.35 0.5 V DD V V IH SE High-level, single-ended input voltage, REFCLK V th SE 0.3 2.625 V V IL L Low-level input voltage, ID0, ID1, EN, BYPASS 0.15 0.8 V V IH L High-level input voltage, ID0, ID1, EN, BYPASS 1.4 2.625 V V IL SM Low-level input voltage, SCL, SDA (2) 0.15 0.8 V V IH SM High-level input voltage, SCL, SDA (2) 1.4 3.465 V (1) When using a single-ended clock input, V th is supplied to the REFCLKB pin. Duty cycle of single-ended REFCLK input is measured at V th (2) This range of SCL and SDA input high voltage allows the CDCD5704 to co-exist with 3.3 2.5 and 1.8 V devices on the same serial-interface bus system. Submit Documentation Feedback

www.ti.com RECOMMENDED AC OPERATING CONDITIONS DEVICE CHARACTERISTICS CDCD5704 SCAS823 DECEMBER 2006 MIN NOM MAX UNIT t CYCLE,IN REFCLK/REFCLKB input cycle time ns t CYC,TEST REFCLK/REFCLKB input cycle time for BYPASS ns t J,IN Input |cycle-to-cycle| jitter (1) 185 ps DC IN Input duty cycle over 10,000 cycles (2) 40% 60% t r f Rise and fall time for REFCLK signal from 20% to 80% of input voltage V IN 175 700 ps t cr cf Difference between rise time and fall time of REFCLK signal from 20% to 80% 150 ps f m,IN SSC frequency modulation repeat frequency (3) kHz P m tria Modulation index frequency deviation/center frequency) for triangle modulation (3) 0.6% P m n tria Modulation index frequency deviation/center frequency) for non-triangle modulation (4) 0.5% t SR Input slew rate REFCLK/REFCLKB V/ns SERIAL INTERFACE TIMING f SCLK SCLK frequency (5) 100 kHz t h(START) START hold time (5) µ s t w(SCLL) SCLK low-pulse duration (5) 4.7 µ s t w(SCLH) SCLK high-pulse duration (5) µ s t su(START) START setup time (5) 4.7 µ s t h(SDATA) SDATA hold time (5) 300 ps t su(SDATA) SDATA setup time (5) 250 ps t r(SDATA) SDATA/SCLK input rise time (5) 1000 ns t r(SM) t f(SDATA) SDATA/SCLK input fall time (5) 300 ns t f(SM) t su(STOP) STOP setup time (5) µ s t (BUS) Bus free time 4.7 µ s (1) RefCLK jitter is measured at IH(nom) V IL(nom) )/2 and is the absolute value of the worst-case deviation. (2) Measured at crossing points for differential clock input or at input threshold voltage V TH for single-ended clock input. (3) If input modulation is used; input modulation is allowed but not required. (4) The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%. (5) See Figure for the timing behavior of the serial interface. over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERALL PARAMETER At 300 MHz and 2.625 V I DD Supply current I VDD I VDDP I VDDC mA At 667 MHz and 2.625 V 115 Supply voltage threshold for power-up control Over complete supply voltage V PUC 1.1 1.8 2.2 V circuit range DC DEVICE CHARACTERISTICS V OX Differential output crossing-point voltage (1) Output load; see Figure 0.9 1.1 V V COS Output voltage swing (p-p, single-ended) (2) 0.3 0.325 0.35 V V OL,ABS Absolute output low voltage (3) 0.85 V Reference voltage for swing control current V DD 2.375 V to 2.625 T C V ISET 0.98 1.02 V IREF (4) to C (1) V OX is measured on external divider as shown in Figure (2) V COS (clock output high voltage clock output low voltage), at the measurement points shown in Figure excluding overshoot and undershoot. (3) V OL,ABS is measured at the clock output of the package, instead of the measurement points of Figure (4) I REF is equal to V ISET RC Tolerance of R RC must be or smaller. Submit Documentation Feedback

www.ti.com CDCD5704 SCAS823 DECEMBER 2006 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I OL REF Ratio of output low current to reference current 6.8 7.2 I OL,ABS Minimum current at V OL,ABS (5) V OL,ABS 0.85 V mA V DD 2.375 V to 2.625 V OL,SDA SDA output low voltage 0.4 V I OH mA V DD 2.375 V to 2.625 I OL,SDA SDA output low current mA V O 0.8 V I OZ Output 3-state current CLK0 to CLK4 µ A I IR REFCLK input current V I V or V DD µ A I IL Logic input current V I V or V DD µ A AC DEVICE CHARACTERISTICS Input capacitance, REFCLK, C IR pF REFCLKB (6) C IL Input capacitance logic pins (7) pF 300 MHz to 667 MHz, possible t CYCLE Clock cycle time (8) 1.5 3.33 ns SSC is not taken into account 10,000 cycles, 300 MHz to 635 MHz (9) t jit(per) |Cycle-to-cycle jitter| of clock cycles ps 10,000 cycles, 636 MHz to 667 MHz (9) L SSB phase noise at MHz 300-MHz 667-MHz output (10) 115 dBc/Hz L SSB phase noise at MHz 300-MHz 667-MHz output (10) 150 128 dBc/Hz V DD 2.375 V to 2.625 Δ t skew(o) Drift in t skew(o) (11) ps T to C odc Output duty cycle 45% 50% 55% 300 MHz to 635 MHz t ODC,ERR |Cycle-to-cycle| duty-cycle error ps 636 MHz to 667 MHz t ERR,SSC PLL output phase error when tracking SSC 100 100 ps t r f Output rise and fall time V OUT 20% 80% 100 300 ps V OUT 20% 80%, f out 300 MHz t cr cf Difference between output rise and fall times 100 ps to 667 MHz Z OUT Output dynamic impedance (12) V OL 0.9 V 750 Ω Time from VDD, VDDP, VDDC t L Power-up lock time being applied and settled until ms clock outputs are settled PLL lock time after (1) frequency change via Time from signals for selecting a serial interface (programming of SCL and SDA mode of operation (1) or (2) t ω ms pins completed) or (2) EN and/or BYPASS applied and settled until clock changed state outputs are settled (5) Minimum I OL,ABS is measured at the clock output pins of the package, as shown in Figure (6) Capacitance measured at frequency MHz, dc bias 0.9 and V AC 100 mV (7) Capacitance measured at frequency MHz, dc bias 0.9 and V AC 100 mV (8) Maximum and minimum output clock cycle times are based on nominal output frequency of 300 MHz and 667 MHz, respectively. For spread-spectrum-modulated differential or single-ended REFCLK, the output clock tracks the modulation of the input. (9) Output short-term jitter specification is the absolute value of the worst-case deviation and is defined in the Jitter section. (10) Device must not exceed the upper limit of L(f) for 1-MHz to 100-MHz offset as shown in the Phase Noise section. (11) t skew is the timing difference between any two of the four differential clocks and is measured at common-mode voltage. Δ t skew is the change in t skew when the operating temperature and supply voltage change. (12) Z OUT is defined at the output pins directly. The value is determined as the ac small-signal impedance at low frequencies 100 kHz) and when output is driving a high state. Submit Documentation Feedback

www.ti.com PHASE NOISE −160 −150 −140 −130 −120 −110 −100 −90 −80 fOffset − Offset Frequency − Hz Phase Noise − dBc/Hz 100k 1M 10M 100M 20M G001 Rambus Spec

667 MHz

Rambus Spec Range:

1 MHz /C0051 fOffset /C0051 20 MHz

300 MHz 400 MHz

MHz, phase noise of the CDCD5704 does not exceed the single-sideband phase noise (spectral purity) described by the following equation given by Rambus. L(f) log (50 2.4 138 dBc/Hz Selected numerical values are in given in the following table. f offset frequency 100 MHz L(f) SSB phase noise 114 121 125 128 134 137 138 dBc/Hz Figure Phase Noise Plot Submit Documentation Feedback

www.ti.com S0201-01 VTS CLK V =□1.2□VT VTS CLKB V =□1.2□VT XCG CDCD5704 ISET Measurement□Points RT RT Z =500 /c87 Z =500 /c87 RRC V(t) tf tr VH VL 20% 80% T0132-01 CDCD5704 SCAS823 DECEMBER 2006 NOTE: In the power-up sequence, the rise time for the external voltage applied to the clock output pins TS must be equal to or longer than the rise time for the supply voltage of the device DD V DDP V DDC PARAMETER VALUE for 50- Ω LINE VALUE for I OL,ABS TOLERANCE UNIT R Termination resistor 39.2 Ω R Termination resistor 66.5 31.8 Ω R Termination resistor 93.1 48.7 Ω R T Termination resistor 49.9 Ω R RC Swing control resistor 200 147 Ω V TS Source termination voltage 2.5 2.5 V V T Termination voltage 1.2 1.2 V Figure Output Test Load Figure Input and Output Waveforms Submit Documentation Feedback

www.ti.com T0133-01 Vx+ Vx,□nom Vx– CLK CLKB T0134-01 CLK tCYCLE,i t =□tJ CYCLE,i – t Over□10,000□Consecutive□CyclesCYCLE,i+1 tCYCLE,i+1 CLKB T0135-01 t4CYCLE,i t4CYCLE,i+1 t =□tJ 4CYCLE,i – t Over□10,000□Consecutive□Cycles4CYCLE,i+1 CLK CLKB T0136-01 t =□tDC,ERR PW+,i – t andPW+,i+1 tPW–,i – t PW–,i+1 CLK Cycle□(i) Cycle□(i+1) CLKB tPW–,i tPW–,i+1 tPW+,i+1 tCYCLE,i tCYCLE,i+1 tPW+,i CDCD5704 SCAS823 DECEMBER 2006 Figure Crossing-Point Voltage Figure One-Period Cycle-to-Cycle Jitter Figure Four-Period Cycle-to-Cycle Jitter Figure Cycle-to-Cycle Duty-Cycle Error Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION XDR Memory Subsystem (Source: Rambus) M0054-01 DRSL:□3.2□GHz DQ□BYTE□[2N+1] DQ□BYTE□[2N] DQ□BYTE□[1] DQ□BYTE□[0] /c183 /c183 /c183 CFM□400□MHZ CTM 400□MHZ To□Other□Subsystems System□Clock RSL:□800□MHz RQ□BUS□[0:11] XDR□System□Topology ASIC PLL 4/c180 XMC XIO XDR DRAM□n XDR DRAM□0 XDR Clock Generator CDCD5704 Termination CDCD5704 SCAS823 DECEMBER 2006 Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDCD5704PW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCD5704PWG4 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCD5704PWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCD5704PWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 Addendum-Page 1

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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