CDC950DGGG4

CDC950 TI | Alldatasheet

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Technical content

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Generates Clocks for Next Generation Microprocessors /C0068Uses a 14.318-MHz Crystal Input to Generate Multiple Output Frequencies /C0068Includes Spread Spectrum Clocking (SSC), 0.6% Downspread for Reduced EMI With Theoretical EMI of 7 dB /C0068Power Management Control Terminals /C0068Low Output Skew and Jitter for Clock Distribution /C0068Operates From a Single 3.3-V Supply /C0068Generates the Following Clocks: − 8 Host (Diff Pairs, 100/133 MHz) − 1 CLK33 (3.3 V, 33.3 MHz) − 1 REFCLK (3.3 V, 14.318 MHz) − 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz) /C0068Packaged in a 48-Pin TSSOP Package

description

The CDC950 is a differential clock synthesizer/ driver that generates HCLK/HCLK, CLK33, 3V48, and REFCLK system clock signals to support a computer system with next generation processors and double data rate (DDR) memory subsystems. All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external components. The HCLK, CLK33 clock, and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected through control inputs SEL100 /133, 3V48/SelA, and 3V48/SelB. The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. With a logic high-level on the PWRDWN terminal, the device operates normally. When a logical low-level input is applied, the device powers down completely with the HOST clock at 2 × IREF , HOSTB is undriven, CLK33, 3V48, and REFCLK outputs are in a low-level output state and 3V48B is in a high-level output state. The host bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with the corresponding setting for SEL100/133 control input. The CLK33 (PCI) frequency is fixed to 33 MHz. Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up, as well as following changes to the SEL inputs. With the use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time starts. The CDC950 is characterized for operation from 0°C to 85°C. Copyright  2001 − 2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CLK33 VDD 3.3V 3V48/SelA 3V48/SelB GND VDD 3.3V HCLK(0) HCLK(0) GND HCLK(1) HCLK(1) VDD 3.3V HCLK(2) HCLK(2) GND HCLK(3) HCLK(3) VDD 3.3V REFCLK SPREAD GND XIN XOUT VDD 3.3V SEL100 /133 GND AV DD 3.3V AGND PWRDWN VDD 3.3V HCLK(4) HCLK(4) GND HCLK(5) HCLK(5) VDD 3.3V HCLK(6) HCLK (6) GND HCLK(7) HCLK(7) VDD 3.3V MultSel0 MultSel1 GND AGND I_REF AV DD 3.3V DGG PACKAGE (TOP VIEW)

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23 PLL

Sync Logic & Power Down Logic Test Latched Spread Logic (7,10,13,16, 33,36,39,42) (8,11,14,17 32,35,38,41) 100/133 MHz CPU PLL /2 /2 I_REF 26 2Control Logic MultSel0 30 MultSel1 29 Phase Shift

1 CLK33

33.3 MHz

(1) 1 3V48B

48 MHz

(4) 100/133 MHz

8 HCLKs

1 REFCLK

14.318 MHz

(19) 1 3V48 (3) 180° SEL100 /133 SPREAD PWRDWN SEL100 /133

8 HCLK s

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION 3V48/SelA, 3V48/SelB 3, 4 I/O 48-MHz 180° shifted pair clocks for USB use Logic select pins. Selects the mode of operation, see Table 1 for details. AGND 27, 45 P Analog ground AV DD 3.3V 25, 46 P Power. Analog power supply CLK33 1 O 33-MHz reference clock for PCI use, host clock divided by 3 or by 4 GND 5, 9, 15, 21, 28, 34, 40, 47 P Ground HCLK 7, 10, 13, 16, 33, 36, 39, 42 O CPU and host clock outputs [7:0]. These eight differential CPU clock pairs run at 100/133 MHz. The VOH swing amplitude is configured by MultSel0, MultSel1 pins. See Table 5 and Intel’s CK00 document for details. HCLK 8, 11, 14, 17, 32, 35, 38, 41 O CPU and host clock outputs [7:0]. These eight differential CPU clock pairs run at 100/133 MHz. The VOH swing amplitude is configured by MultSel0, MultSel1 pins. See Table 5 and Intel’s CK00 document for details. I_REF 26 I Current reference. This pin establishes the reference current for host clock parts. See Table 5 and Intel’s CK00 document for details. MultSel0 30 I See Table 5 and Intel’s CK00 document for details. MultSel1 29 I See Table 5 and Intel’s CK00 document for details. PWRDWN 44 I Power-down input. 3.3-V LVTTL compatible, asynchronous input that requests the device to enter the power-down mode. See Table 2 for details. REFCLK 19 O 14.138-MHz reference clock output: 3.3 V copy of the 14.318-MHz reference clock. SEL100 /133 48 I Active low LVTTL level logic select. SEL100/133 is used for enabling 100/133 MHz. Low = 100 MHz, high = 133 MHz SPREAD 20 U Spread spectrum enable. 3.3-V LVTTL compatible, input that enables the spread spectrum mode when held low. See Table 4 for details. VDD 3.3V 2, 6, 12, 18, 24, 31, 37, 43 P Power. Power supply XIN 22 I Crystal connection or an external reference frequency input. Connect to either a 14.138-MHz crystal or an external reference signal. XOUT 23 O Crystal connection. An output connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected.

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Table 1. Select Functions Table 2. Enable Functions

1 On On On On On On

Table 3. Output Buffer Specifications Table 4. Spread Spectrum Functions

1 Spread spectrum clocking inactive

Table 5. Host/HOST Output Buffer Specifications NOTE: The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations. implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

1. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,

which use a trace length of zero.

1. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

Book, literature number SCBD002.

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR † ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DGG 1400 mW 11.2 mW/°C 900 mW 730 mW † This is the inverse of the traditional junction-to-case thermal resistance (RθJA) and uses a board-mounted device at 89°C/W recommended operating conditions (see Note 4) MIN NOM ‡ MAX UNIT Supply voltages, VDD , AVDD 3.135 3.3 3.465 High-level input voltage, VIH 2 VLow-level input voltage, VIL 0.8 V Input voltage, VI −0.3 VDD + 0.3 HCLK/HCLK −40 High-level output current, IOH CLK33 −18 High-level output current, IOH 3V48/SelA and 3V48/SelB −14 REFCLK −14 mAHCLK/HCLK 0 mA Low-level output current, IOL CLK33 12 Low-level output current, IOL 3V48/SelA and 3V48/SelB 9 REFCLK 9 Reference frequency, f(XIN)§ Test mode 14 MHzCrystal, f(XTAL)¶ Normal mode 13.8 14.318 14.8 MHz Operating free-air temperature, TA 0 85 °C ‡ All nominal values are measured at their respective nominal VDD values. § Reference frequency is a test clock driven on the XIN input during the device test mode or normal mode. In test mode, XIN can be driven externally up to f(XIN) = 16 MHz. If XIN is driven externally, XOUT is floating. ¶ This is a series fundamental crystal with fo = 14.31818 MHz NOTE 4: Unused inputs must be held high or low to prevent them from floating.

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK Input clamp voltage VDD = 3.135 V, II = –18 mA −1.2 V IIH High-level input current All inputs except SelA, SelB VDD = 3.465 V, VI = VDD 5 µA IIL Low-level input current All inputs except SelA, SelB VDD = 3.465 V, VI = GND −5 µA IOZ High-impedance -state output current All outputs including SelA, SelB VDD = 3.465 V 3V48/SelA, 3V48/SelB = H, SEL100/133 = L, VO = VDD or GND, PWRDWN = H ±10 µA IDD(Z) High-impedance-state supply current‡ VDD = 3.465 V 3V48/SelA, 3V48/SelB = H, SEL100/133 = L, PWRDWN = H 19 25 mA IDD(PD) SelA, SelB = L R (ref) = 475 Ω VDD Supply 43 47 mA AIDD(PD) PWRDWN state supply current‡ R (ref) = 475 Ω PWRDWN = L AVDD Supply 3.4 4.2 mA IDD(D) Dynamic supply current‡ VDD = 3.465 V, R ref = 475 Ω PWRDWN = H SSC = ON/OFF

100 MHz 173 190

mAIDD(D) Dynamic supply current‡ DD R ref = 475 Ω, IO = 6 x Iref SSC = ON/OFF C L = MAX 133 MHz 183 200 mA

100 MHz and SSC off 19 24

AlDD Analog power supply current VDD = 3.465 V

133 MHz and SSC off 26 33

mAAlDD Analog power supply current V DD = 3.465 V 100 MHz and SSC on 26 33 mA

133 MHz and SSC on 35 45

C I Input capacitance§ VDD = 3.3 V, VI = VDD or GND 2 5 pF C (XTAL) Crystal load capacitance/C0087 Effective capacity between CIN and COUT 13.5 22.5 pF † All typical values are measured at their respective nominal VDD values. ‡ C L = MAX = 5 pF, RS = 33.2 Ω, Rp = 49.9 Ω at HCLK/HCLK (Type X1) C L = MAX = 20 pF, RL = 500 Ω at 48 MHz, REF (Type 3) C L = MAX = 30 pF, RL = 500 Ω at CLK33 (Type 5) § These parameters are assured by design and lab characterization, not 100% production tested. ¶ This is the corresponding capacitive load for the XTAL in this oscillator application (Pierce oscillator)

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) HCLK/HCLK (Type X1) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT ro Output resistance 3000 Ω VO Output voltage 1.2 V IO Output current VDD = 3.30 V nom All combinations of Table 5, See Note 5 −7% l(NOM) l(NOM) mAIO Output current VDD = 3.30 V, ±5% All combinations of Table 5, See Note 5 −12% l(NOM) 12% l(NOM) mA C O Output capacitance VDD = 3.30 V nom VO = VDD GND 3.5 pF NOTE 5: I(NOM) is output current (IOH ) of table 5. 3V48, 3V48REFCLK (Type 3) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage VDD = min to max,IOH = –1 mA VDD – 0.1 VOH High-level output voltage VDD = 3.135 V, IOH = −14 mA 2.4 V VOL Low-level output voltage VDD = min to max,IOL = 1 mA 0.1 V VOL Low-level output voltage VDD = 3.135 V, IOL = 9 mA 0.18 0.4 VDD = 3.135 V, VO = 1 V −29 IOH High-level output current VDD = 3.3 V, VO = 1.65 V −37IOH High-level output current VDD = 3.465 V, VO = 3.135 V −11 −23 mAVDD = 3.135 V, VO = 1.95 V 29 mA IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 39IOL Low-level output current VDD = 3.465 V, VO = 0.4 V 16 27 C O Output capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7 pF Zo Output impedance High state VO = 0.5 VDD , VO /IOH 20 40 60 ΩZo Output impedance Low state VO = 0.5 VDD , VO /IOL 20 40 60 Ω † All typical values are measured at their respective nominal VDD values.

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) CLK33 (Type 5) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage VDD = min to max,IOH = –1 mA VDD – 0.1 VOH High-level output voltage VDD = 3.135 V, IOH = −18 mA 2.4 V VOL Low-level output voltage VDD = min to max,IOL = 1 mA 0.1 V VOL Low-level output voltage VDD = 3.135 V, IOL = 12 mA 0.15 0.4 VDD = 3.135 V, VO = 1 V −33 IOH High-level output current VDD = 3.3 V, VO = 1.65 V −53IOH High-level output current VDD = 3.465 V, VO = 3.135 V −16 −33 mAVDD = 3.135 V, VO = 1.95 V 30 mA IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 51IOL Low-level output current VDD = 3.465 V, VO = 0.4 V 21 38 C O Output capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7.5 pF Zo Output impedance High state VO = 0.5 VDD , VO /IOH 12 35 55 ΩZo Output impedance Low state VO = 0.5 VDD , VO /IOL 12 35 55 Ω † All typical values are measured at their respective nominal VDD values. switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT V(over) Overshoot† HCLK/HCLK 0.7-V VOH + 200 mVV(under) Undershoot† HCLK/HCLK 0.7-V amplitude VOL − 200 mV V(over) Overshoot† Other clocks, GND − 0.7 VV(under) Undershoot† Other clocks, C L = worst case VDD + 0.7 V tPZL Output enable time from low level SEL100 /133 All outputsSEL100 /133 ↑ R ref = 475 Ω 10 tPZH Output enable time to high level SEL100 /133 All outputsSEL100 /133 ↑ R ref = 475 Ω 10 ns tPHZ Output disable time from high level SEL100 /133 All outputsSEL100 /133 ↓ R ref = 475 Ω 10 ns tPLZ Output disable time from low level SEL100 /133 All outputsSEL100 /133 ↓ R ref = 475 Ω 10 ts Stabilization time‡ VDD All outputsAfter power up 0.1 ms ts Stabilization time‡ PWRDWN All outputsFrom PWRDWN ↑ 0.25 ms † These parameters are assured by design and lab characterization, not 100% production tested. ‡ Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at XIN. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the time since VDD achieves its nominal operating level (3.3 V) or PWRDWN transition from a low to a high level (2 V) until the output frequency is stable and operating within specification.

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued) HCLK/HCLK (Type X1), CL = 2 pF, R ref = 475 Ω, 6 x Rref PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HCLK clock period‡ f(HCLK) = 100 MHz 10 10.2 nsHCLK clock period‡ f(HCLK) = 133 MHz 7.5 7.65 ns Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz SSC off −80 80 psTjit(cc) Cycle-to-cycle jitter f (HCLK) = 100 or 133 MHz SSC on −110 110 ps tdc Duty cycle f(HCLK) = 100 or 133 MHz, Crossing point 45% 55% tsk(o) HCLK bus skew f(HCLK) = 100 or 133 MHz, Crossing point 70 ps tr Rise time† 0.7-V amplitude VO = 0.14 V to 0.56 V 175 700 pstf Fall time† 0.7-V amplitude VO = 0.14 V to 0.56 V 175 700 ps v(cross) Cross point voltages† 0.7-V amplitude f(HCLK) = 100 or 133-MHz HCLK and HCLK 45% VOH 55% VOH V † These parameters are assured by design and lab characterization, not 100% production tested. ‡ The average over any 1-µs period of time is greater than the minimum specified period. CLK33 (Type 5), CL = 30 pF, RL = 500 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PCI clock period† f(HCLK) = 100 or 133 MHz 30 30.06 30.6 ns Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz −150 150 ps t(dc) Duty cycle f(CLK33) = 33.3 MHz 45% 55% tr Rise time VO = 0.4 V to 2.4 V 0.5 2 ns tf Fall time VO = 0.4 V to 2.4 V 0.5 2 ns † The average over any 1-µs period of time is greater than the minimum specified period. 3V48 (Type 3), CL = 20 pF, RL = 500 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3V48 clock period f(HCLK) = 100 or 133 MHz 20.83 ns Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz −300 300 ps tdc Duty cycle f(3V48) = 48 MHz 45% 55% tr Rise time VO = 0.4 V to 2.4 V 1 4 ns tf Fall time VO = 0.4 V to 2.4 V 1 4 ns REF (Type 3), CL = 20 pF, RL = 500 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REF clock period f(REF) = 14.318 MHz 69.84 ns Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz −0.5 0.5 ns t(dc) Duty cycle f(REF) = 14.318 MHz 45% 55% tr Rise time VO = 0.4 V to 2.4 V 1 4 nstf Fall time VO = 0.4 V to 2.4 V 1 4 ns

NOTES: A. C L includes probe and jig capacitance. CL = 2 pF (HCLK, HCLK), CL = 20 pF (48 MHz, REF), CL = 30 pF (CLK33). B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

R (S1) = 33 Ω R (S1) = 33 Ω R I(REF) = 475 Ω R (T1) = 49.9 Ω R (T1) = 49.9 Ω C L = 2 pF C L = 2 pF C L Represents CBOARD and Cjig ZTLA = ZTLB = 50 Ω VDD HCLK HCLK Figure 2. Load Circuit for HCLK Bus the CPU-PLL allows energy to be distributed to many different frequencies which reduces the power peak. Figure 3. Frequency Power Spectrum With and Without the Use of SSC indicates a down-spread modulation.

/C0067/C0068/C0067/C0057/C0053/C0048 /C0049/C0051/C0051/C0262/C0077/C0072/C0122 /C0068/C0073/C0070/C0070/C0069/C0082/C0069/C0078/C0084/C0073/C0065/C0076 /C0067/C0076/C0079/C0067/C0075 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0070/C0079/C0082 /C0080/C0067 /C0077/C0079/C0084/C0072/C0069/C0082/C0066/C0079/C0065/C0082/C0068/C0083/C0047/C0083/C0069/C0082/C0086/C0069/C0082/C0083 SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°−/C0257 8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDC950DGG ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDC950DGGG4 ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDC950DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDC950DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 Addendum-Page 1

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97 0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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