CDC922

CDC922_06 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Texas Instruments, Incorporated[M]
• PDF pages: 18

Technical content

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Generates Clocks for Pentium III Class Microprocessors /C0068Supports a Single Pentium III Microprocessor /C0068Uses a 14.318 MHz Crystal Input to Generate Multiple Output Frequencies /C0068Includes Spread Spectrum Clocking (SSC), 0.34% Downspread for Reduced EMI Performance /C0068Power Management Control Terminals /C0068Low Output Skew and Jitter for Clock Distribution /C0068Operates from Dual 2.5-V and 3.3-V Supplies /C0068Generates the Following Clocks: – 3 CPU (2.5 V, 100/133 MHz) – 10 PCI (3.3 V, 33.3 MHz) – 1 CPU/2 (2.5 V, 50/66 MHz) – 1 APIC (2.5 V, 16.67 MHz) – 3 3V66 (3.3 V, 66 MHz) – 2 REF (3.3 V, 14.318 MHz) – 1 48MHz (3.3 V, 48 MHz) /C0068Packaged in 48-Pin SSOP Package /C0068Designed for Use with TI’s Direct Rambus Clock Generators (CDCR81, CDCR82, CDCR83)

description

The CDC922 is a clock synthesizer/driver that generates CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF system clock signals to support computer systems with a single Pentium III class microprocessor. All output frequencies are generated from a 14.318-MHz crystal input. Instead of a crystal, a reference clock input can be provided at the XIN input. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100 The 48MHz clock can be independently disabled via the control inputs SEL0, SEL1, and SEL133/100. In this state, the 48-MHz PLL is disabled and the 48MHz clock is driven to high impedance to reduce component jitter. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely with the outputs in a low-level output state. Copyright  1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. REF0 REF1 VDD 3.3V XIN XOUT GND PCI0 PCI1 VDD 3.3V PCI2 PCI3 PCI4 PCI5 GND PCI6 PCI7 VDD 3.3V PCI8 PCI9 GND 3V66(0) 3V66(1) 3V66(2) V DD 3.3V GND VDD 2.5V APIC GND VDD 2.5V CPU_DIV2 GND VDD 2.5V CPU2 GND VDD 2.5V CPU1 CPU0 GND V DD 3.3V GND PWR_DWN SPREAD SEL1 SEL0 V DD 3.3V 48MHz GND SEL133/100 DL PACKAGE (TOP VIEW) Intel and Pentium III are trademarks of Intel Corporation. Direct Rambus and Rambus are trademarks of Rambus Inc. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999

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description (continued) The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100 control input. The PCI bus frequency is fixed to 33 MHz. Since the CDC922 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts. Function Tables SELECT FUNCTIONS INPUTS OUTPUTS SEL133/

100 SEL1 SEL0 CPU CPU_DIV2 3V66 PCI 48MHz REF APIC FUNCTION

L L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 3-state L L H N/A N/A N/A N/A N/A N/A N/A Reserved L H L 100 MHz 50 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off L H H 100 MHz 50 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on H L L TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 Test H L H N/A N/A N/A N/A N/A N/A N/A Reserved H H L 133 MHz 66 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off H H H 133 MHz 66 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on ENABLE FUNCTIONS INPUTS OUTPUTS INTERNAL PWR_DWN CPU CPU_DIV2 APIC 3V66 PCI REF, 48MHz CRYSTAL VCOs L L L L L L L Off Off H On On On On On On On On OUTPUT BUFFER SPECIFICATIONS BUFFER NAME VDD RANGE (V) IMPEDANCE (W ) BUFFER TYPE CPU, CPU_DIV2, APIC 2.375 – 2.625 13.5 – 45 TYPE 1 48MHz, REF 3.135 – 3.465 20 – 60 TYPE 3 PCI, 3V66 3.135 – 3.465 12 – 55 TYPE 5

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION 3V66 [0–2] 21–23 O 3.3 V, Type 5, 66-MHz clock outputs 48MHz 27 O 3.3 V, Type 3, 48-MHz clock output APIC 46 O 2.5 V, Type 2, APIC clock output at 16.67 MHz CPU [0–2] 36, 37, 40 O 2.5 V, Type 1, CPU clock outputs CPU_DIV2 43 O 2.5 V, Type 1, CPU_DIV2 clock output GND 6, 14, 20, 26, 33, 35, 39, 42, 45, 48 Ground for PCI, 3V66, 48MHz, CPU, CPU_DIV2, APIC, REF [0–1] outputs and CORE 15, 16, 18, 19 O 3.3 V, Type 5, 33-MHz PCI clock outputs PWR_DWN 32 I Power down for complete device with outputs forced low REF0, REF1 1, 2 O 3.3 V, Type 3, 14.318-MHz reference clock outputs SEL0, SEL1 29, 30 I LVTTL level logic select terminals for function selection SEL133/100 25 I LVTTL level logic select terminal for enabling 100/133 MHz SPREAD 31 I Disables SSC function VDD 2.5V 38, 41, 44, 47 Power for CPU, CPU_DIV2, and APIC outputs VDD 3.3V 3, 9, 17, 24, 28, 34 Power for the REF, PCI, 3V66, 48MHz outputs and CORE XIN 4 I Crystal input – 14.318 MHz XOUT 5 O Crystal output – 14.318 MHz

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of the CPU–PLL allows to distribute the energy to many different frequencies which reduces the power peak. Figure 1. Frequency Power Spectrum With and Without the Use of SSC approximately –0.34% (compared to –0.5% on the CDC921). CDC922 is shown in Figure 2. Figure 2. SSC Modulation Profile

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram 2*REF

14.318 MHz

(1,2) SEL133/100 PWR_DWN SPREAD XOUT XIN SEL1 SEL0 Control Logic 3-State SEL 133/100 48-MHz Inactive Test Xtal Oscillator5 4 48 MHz PLL CPU PLL Spread Logic Sync Logic & Power Down Logic /2 /231 1*48MHz

48 MHz

(27) 3*CPU 100/133 MHz (36,37,40) 10*PCI

33 MHz

(7,8,10,11,12, 13,15,16,18,19) 1*APIC

16.67 MHz

(46) 3*AGP (3V66)

66 MHz

(21,22,23) 1*CPU_DIV2 50/66 MHz (43)

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range applied to any output in the high-impedance state or power-off state, † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C DERATING FACTOR † TA = 70°C TA = 85°CPACKAGE A POWER RATNG ABOVE T A = 25°C A POWER RATING A POWER RATING DL 1315.7 mW 10.53 mW/°C 842.1 mW 684.2 mW † This is the inverse of the traditional junction-to-case thermal resistance (RqJA) and uses a board-mounted device at 95°C/W. recommended operating conditions (see Note 2) MIN NOM † MAX UNIT Supply voltage VDD 3.3 V 3.135 3.465 VSupply voltage, VDD 2.5 V 2.375 2.625 V High-level input voltage, VIH 2 VDD +

0.3 V V

Low-level input voltage, VIL GND – 0.3 V 0.8 V Input voltage, VI 0 VDD V CPUx, CPU_DIV2 –12 High level output current IOH APIC –12 mAHigh-level output current, IOH 48MHz, REFx –14 mA PCIx, PCI_F, 3V66x –18 CPUx, CPU_DIV2 12 Low level output current IOL APIC 12 mALow-level output current, IOL 48MHz, REFx 9 mA PCIx, PCI_F, 3V66x 12 Reference frequency, f(XTAL)‡ Test mode 130 MHz Crystal frequency, f(XTAL)§ Normal mode 13.8 14.318 14.8 MHz Operating free-air temperature, TA 0 85 °C NOTE 2: Unused inputs must be held high or low to prevent them from floating. † All nominal values are measured at their respective nominal VDD values. ‡ Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven externally up to f(XTAL) = 130 MHz. If XIN is driven externally, XOUT is floating. § This is a series fundamental crystal with fO = 14.31818 MHz.

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK Input clamp voltage VDD = 3.135 V, II = –18 mA –1.2 V R I Input resistance XIN, XOUT VDD = 3.465 V, VI = VDD –0.5 V 80 350 kW XOUT VDD = 3.135 V, VI = VDD –0.5 V 20 50 mA IIH High-level input current SEL0, SEL1, SPREAD VDD = 3.465 V, VI = VDD <10 10 mA IH g PWR_DWN VDD = 3.465 V, VI = VDD <10 10 mA SEL133/100 VDD = 3.465 V, VI = VDD <10 10 mA XOUT VDD = 3.135 V, VI = 0 V –2 –5 mA IIL Low-level input current SEL0, SEL1, SPREAD VDD = 3.465 V, VI = GND <10 –10 mA IL PWR_DWN VDD = 3.465 V, VI = GND <10 –10 mA SEL133/100 VDD = 3.465 V, VI = GND <10 –10 mA IOZ High-impedance-state output current |VDD | = max, VO = VDD or GND ±10 mA VDD = 2.625 V, PWR_DWN = low All outputs = low, <20 100 mA IDD Supply current VDD = 2.625 V, All outputs = high <20 100 mA IDD Supply current VDD = 3.465 V, PWR_DWN = low All outputs = low, <50 200 mA VDD = 3.465 V, All outputs = high 12 37 mA IDD(Z) High-impedance-state supply VDD = 2.625 V 1.4 mAIDD(Z) gy current VDD = 3.465 V 30 mA Dynamic IDD C L = 20 pF, VDD = 3.465 V 114 156 mAD ynamic IDD L CPU = 133 MHz VDD = 2.625 V 44 60 mA C I Input capacitance VDD = 3.3 V, VI = VDD or GND 3.3 5.8 pF Crystal terminal capacitance VDD = 3.3 V, VI = 0.3 V 18 18.5 22.5 pF † All typical values are measured at their respective nominal VDD values.

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) CPUx, CPU_DIV2, APIC (Type 1) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage VDD = min to max, IOH = –1 mA VDD –

0.1 V VOH gg

VDD = 2.375 V, IOH = –12 mA 2 VOL Low level output voltage VDD = min to max, IOL = 1 mA 0.1 VVOL Low-level output voltage VDD = 2.375 V, IOL = 12 mA 0.18 0.4 V VDD = 2.375 V, VO = 1 V –26 –42 IOH High-level output current VDD = 2.5 V, VO = 1.25 V –46 mA VDD = 2.625 V, VO = 2.375 V –16 –27 VDD = 2.375 V, VO = 1.2 V 27 57 IOL Low-level output current VDD = 2.5 V, VO = 1.25 V 63 mA VDD = 2.625 V, VO = 0.3 V 23 43 C O Output capacitance VDD = 3.3 V, VO = VDD or GND 5.8 8.5 pF ZO Output impedance High state VO = 0.5 VDD , VO /IOH 13.5 27 45 WZO O utput impedance Low state VO = 0.5 VDD , VO /IOL 13.5 20 45 W † All typical values are measured at their respective nominal VDD values. 48MHz, REFx (Type 3) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage VDD = min to max, IOH = –1 mA VDD – VDD = 3.135 V, IOH = –14 mA 2.4 VOL Low level output voltage VDD = min to max, IOL = 1 mA 0.1 VVOL Low-level output voltage VDD = 3.135 V, IOL = 9 mA 0.18 0.4 V VDD = 3.135 V, VO = 1 V –27 –41 IOH High-level output current VDD = 3.3 V, VO = 1.65 V –41 mA VDD = 3.465 V, VO = 3.135 V –12 –23 VDD = 3.135 V, VO = 1.95 V 29 50 IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 53 mA VDD = 3.465 V, VO = 0.4 V 20 37 C O Output capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7 pF ZO Output impedance High state VO = 0.5 VDD , VO /IOH 20 40 60 WZO O utput impedance Low state VO = 0.5 VDD , VO /IOL 20 31 60 W † All typical values are measured at their respective nominal VDD values.

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PCIx, 3V66x (Type 5) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage VDD = min to max, IOH = –1 mA VDD – VDD = 3.135 V, IOH = –18 mA 2.4 VOL Low level output voltage VDD = min to max, IOL = 1 mA 0.1 VVOL Low-level output voltage VDD = 3.135 V, IOL = 12 mA 0.15 0.4 V VDD = 3.135 V, VO = 1 V –33 –53 IOH High-level output current VDD = 3.3 V, VO = 1.65 V –53 mA VDD = 3.465 V, VO = 3.135 V –16 –33 VDD = 3.135 V, VO = 1.95 V 30 67 IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 70 mA VDD = 3.465 V, VO = 0.4 V 27 49 C O Output capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7.5 pF ZO Output impedance High state VO = 0.5 VDD , VO /IOH 12 31 55 WZO O utput impedance Low state VO = 0.5 VDD , VO /IOL 12 24 55 W † All typical values are measured at their respective nominal VDD values. switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Overshoot/undershoot GND – 0.7 V VDD + 0.7 V V Ring back VIL – 0.1 V VIH + 0.1 V V Stabilization time, PWR_DWN to PCIx f(CPU) = 133 MHz 0.05 3 ms tdis3 Disable time, PWR_DWN to PCIx f(CPU) = 133 MHz 50 ns Stabilization time, PWR_DWN to CPUx f(CPU) = 133 MHz 0.03 3 ms tdis4 Disable time, PWR_DWN to CPUx f(CPU) = 133 MHz 50 ns Stabilization time† After SEL1, SEL0 3 msStabilization time† After power up 3 ms † Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification.

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999

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switching characteristics, VDD = 2.375 V to 2.625 V, TA = 0°C to 85°C (continued) CPUx PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 CPUx f(CPU) = 100 or 133MHz 6 10 ns tdis1 Output disable time SEL133/100 CPUx f(CPU) = 100 or 133MHz 8 10 ns t CPU clock period† f(CPU) = 100 MHz 10 10.04 10.2 ns tc CPU clock period† f(CPU) = 133 MHz 7.5 7.53 7.7 ns Cycle to cycle jitter f(CPU) = 100 or 133MHz 250 ps Duty cycle f(CPU) = 100 or 133MHz 45 55 % tsk(o) CPU bus skew CPUx CPUx f(CPU) = 100 or 133MHz 50 175 ps tsk(p) CPU pulse skew CPUn CPUn f(CPU) = 100 or 133MHz 2.2 ns t(off) CPU clock to APIC clock offset, rising edge 1.5 2.8 4 ns t(off) CPU clock to 3V66 clock offset, rising edge 0 0.75 1.5 ns t 1 Pulse duration width high f(CPU) = 100 MHz 2.6 4.3 nstw1 Pulse duration width, high f(CPU) = 133 MHz 1.4 3.7 ns t 2 Pulse duration width low f(CPU) = 100 MHz 2.8 4.3 nstw2 Pulse duration width, low f(CPU) = 133 MHz 1.7 4 ns tf Fall time VO = 0.4 V to 2.0 V 0.4 1.4 2 ns † The average over any 1-ms period of time is greater than the minimum specified period. CPU_DIV2 PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 CPU_DIV2 f(CPU) = 100 or 133MHz 6 10 ns tdis1 Output disable time SEL133/100 CPU_DIV2 f(CPU) = 100 or 133MHz 8 10 ns t CPU DIV2 clockperiod† f(CPU) = 100 MHz 20 20.08 20.4 ns tc CPU _DIV2 clock period† f(CPU) = 133 MHz 15 15.06 15.3 ns Cycle to cycle jitter f(CPU) = 100 or 133MHz 250 ps Duty cycle f(CPU) = 100 or 133MHz 45 55 % tsk(p) CPU_DIV2 pulse skew f(CPU) = 100 or 133MHz 1.6 ns t 1 Pulse duration width high f(CPU) = 100 MHz 7.1 nstw1 Pulse duration width, high f(CPU) = 133 MHz 4.7 ns t 2 Pulse duration width low f(CPU) = 100 MHz 7.3 8.9 nstw2 Pulse duration width, low f(CPU) = 133 MHz 5 6.6 ns tr Rise time VO = 0.4 V to 2.0 V 0.4 1.4 2 ns † The average over any 1-ms period of time is greater than the minimum specified period.

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VDD = 2.375 V to 2.625 V, TA = 0°C to 85°C (continued) APIC PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 APIC f(APIC) = 16.67 MHz 6 10 ns tdis1 Output disable time SEL133/100 APIC f(APIC) = 16.67 MHz 8 10 ns tc APIC clock period† f(APIC) = 16.67 MHz 60 60.24 60.6 ns Cycle to cycle jitter f(CPU) = 100 or 133 MHz 400 ps Duty cycle f(APIC) = 16.67 MHz 45 55 % tsk(p) APIC pulse skew f(APIC) = 16.67 MHz 3 ns t(off) APIC clock to CPU clock offset, rising edge APIC CPUx –1.5 –4 ns tw1 Pulse duration width, high f(APIC) = 16.67 MHz 25.5 28 ns tw2 Pulse duration width, low f(APIC) = 16.67 MHz 25.3 29.2 ns tr Rise time VO = 0.4 V to 2 V 0.4 1.6 2.1 ns tf Fall time VO = 0.4 V to 2 V 0.4 1.2 1.7 ns † The average over any 1-ms period of time is greater than the minimum specified period. switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C 3V66 PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 3V66x f(3V66) = 66 MHz 6 10 ns tdis1 Output disable time SEL133/100 3V66x f(3V66) = 66 MHz 8 10 ns tc 3V66 clock period† f(3V66) = 66 MHz 15 15.06 15.3 ns Cycle to cycle jitter f(CPU) = 100 or 133 MHz 400 ps Duty cycle f(3V66) = 66 MHz 45 55 % tsk(o) 3V66 bus skew 3V66x 3V66x f(3V66) = 66 MHz 50 150 ps tsk(p) 3V66 pulse skew 3V66n 3V66n f(3V66) = 66 MHz 2.6 ns t(off) 3V66 clock to CPU clock offset3V66x CPUx 0 –0.75 –1.5 ns t(off) 3V66 clock to PCI clock offset, rising edge 1.2 2.1 3 ns tw1 Pulse duration width, high f(3V66) = 66 MHz 5.2 ns tw2 Pulse duration width, low f(3V66) = 66 MHz 5 ns tr Rise time VO = 0.4 V to 2 V 0.5 1.5 2 ns tf Fall time VO = 0.4 V to 2 V 0.5 1.5 2 ns † The average over any 1-ms period of time is greater than the minimum specified period.

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999

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switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued) 48MHz PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 48MHz f(48MHz) = 48 MHz 6 10 ns tdis1 Output disable time SEL133/100 48MHz f(48MHz) = 48 MHz 8 10 ns tc 48MHz clock period† f(48MHz) = 48 MHz 20.5 20.83 21.1 ns Cycle to cycle jitter f(CPU) = 100 or 133 MHz 500 ps Duty cycle f(48MHz) = 48 MHz 45 55 % tsk(p) 48MHz pulse skew 48MHz 48MHz f(48MHz) = 48 MHz 3 ns tw1 Pulse duration width, high f(48MHz) = 48 MHz 7.8 ns tw2 Pulse duration width, low f(48MHz) = 48 MHz 7.8 ns tr Rise time VO = 0.4 V to 2 V 1 2.1 2.8 ns tf Fall time VO = 0.4 V to 2 V 1 1.9 2.8 ns † The average over any 1-ms period of time is greater than the minimum specified period. REF PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 REFx f(REF) = 14.318 MHz 6 10 ns tdis1 Output disable time SEL133/100 REFx f(REF) = 14.318 MHz 8 10 ns tc REF clock period† f(REF) = 14.318 MHz 69.84 ns Cycle to cycle jitter f(CPU) = 100 or 133 MHz 700 ps Duty cycle f(REF) = 14.318 MHz 45 55 % tsk(o) REF bus skew REFx REFx f(REF) = 14.318 MHz 150 250 ps tsk(p) REF pulse skew REFn REFn f(REF) = 14.318 MHz 2 ns tw1 Pulse duration width, high f(REF) = 14.318 MHz 26.2 32.7 ns tw2 Pulse duration width, low f(REF) = 14.318 MHz 26.2 31.2 ns tr Rise time VO = 0.4 V to 2 V 1 2 2.8 ns tf Fall time VO = 0.4 V to 2 V 1 1.9 2.8 ns † The average over any 1-ms period of time is greater than the minimum specified period.

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued) PCI PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 PCIx f(PCI) = 33 MHz 6 10 ns tdis1 Output disable time SEL133/100 PCIx f(PCI) = 33 MHz 8 10 ns tc PCIx clock period† f(PCI) = 33 MHz 30 30.12 30.5 ns Cycle to cycle jitter f(CPU) = 100 or 133 MHz 300 ps Duty cycle f(PCI) = 33 MHz 45 55 % tsk(o) PCIx bus skew PCIx PCIx f(PCI) = 33 MHz 70 300 ps tsk(p) PCIx pulse skew PCIn PCIn f(PCI) = 33 MHz 4 ns t(off) PCIx clock to 3V66 clock offset –1.2 –3 ns tw1 Pulse duration width, high f(PCI) = 33 MHz 12 ns tw2 Pulse duration width, low f(PCI) = 33 MHz 12 ns tr Rise time VO = 0.4 V to 2 V 0.5 1.6 2 ns tf Fall time VO = 0.4 V to 2 V 0.5 1.5 2 ns † The average over any 1-ms period of time is greater than the minimum specified period.

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B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 3. Load Circuit and Voltage Waveforms

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999

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DL (R-PDSO-G) PLASTIC SMALL-OUTLINE PACKAGE 4040048/D 08/97 48-PIN SHOWN 0.730 (18,54) 0.720 (18,29) 4828 0.370 (9,40) (9,65) 0.380 Gage Plane DIM 0.420 (10,67) 0.395 (10,03) A MIN A MAX 0.006 (0,15) NOM PINS 0.630 (16,00) (15,75) 0.620 0.010 (0,25) Seating Plane 0.020 (0,51) 0.040 (1,02) 0.008 (0,203) 0.012 (0,305) 0.008 (0,20) MIN A 0.110 (2,79) MAX 0.299 (7,59) 0.291 (7,39) 0.004 (0,10) M0.005 (0,13) 0.025 (0,635) 0°–8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDC922DL OBSOLETE SSOP DL 48 TBD Call TI Call TI CDC922DLR OBSOLETE SSOP DL 48 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2006 Addendum-Page 1

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