CDC913 TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Generates Programmable CPU Clock Output (50 MHz, 60 MHz, or 66 MHz) /C0068Generates 33-MHz Clock for Asynchronous PCI /C0068One 14.318-MHz Reference Clock Output /C0068All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input /C0068LVTTL-Compatible Inputs and Outputs /C0068Internal Loop Filters for Phase-Lock Loops Eliminate the Need for External Components /C0068Operates at 3.3-V VCC /C0068Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages
description
The CDC913 is a high-performance clock generator with integrated dual 1-to-4 buffers, which simplifies clock system design for PC motherboards. The CDC913 consists of a crystal oscillator, two phase-locked loops (PLL), and two 1-to-4 buffers. The CDC913 generates all frequencies using a single 14.318-MHz crystal. The CPUCLK output is programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 inputs. PCICLK outputs a 33-MHz clock, independent of the CPUCLK frequency. REFCLK provides a buffered copy of the 14.318-MHz reference. The oscillator and PLLs in the CDC913 are bypassed when in the TEST mode, i.e., SEL1 = SEL0 = H. When in the TEST mode, a test clock can be driven over the X1 input and buffered out from the PCICLK, CPUCLK, and REFCLK outputs. Outputs 1Yn and 2Yn are 3-state outputs and are enabled via OE . When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are enabled. Since the CDC913 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, and following any changes to the SELn inputs. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. AGND VCC 1Y1 1Y2 1Y3 1Y4 GND CPUCLK SEL0 A VCC REFCLK OE VCC 2Y1 2Y2 2Y3 2Y4 GND PCICLK SEL1 DB OR DW PACKAGE (TOP VIEW) Copyright 1996, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SEL0 SEL1 X1 CPUCLK PCICLK REFCLK L L 14.318 MHz 50 MHz 33 MHz 14.318 MHz H L 14.318 MHz 60 MHz 33 MHz 14.318 MHz L H 14.318 MHz 66 MHz 33 MHz 14.318 MHz H H TCLK † TCLK † TCLK † TCLK † † Test clock (TCLK) is driven over X1 when the CDC913 is in the TEST mode; i.e., SEL1 = SEL0 = H. OE 1A 2A 1Yn 2Yn H X X Hi-Z Hi-Z L L L L L L L H L H L H L H L L H H H H
PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram X1 1 OSC 1Y15 1Y37 2Y120 1Y2 1Y4 2Y2 2Y3 33-MHz PLL X2 2 REFCLK23 PCICLK14 CPUCLK11 CPU-CLK PLL SEL0 12 Select Logic SEL1 13 OE 22 1A 10 2A 15 17 2Y4
PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 3.135 3.6 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V REFCLK –12 PCICLK –6 IOH High-level output current CPUCLK –6 mA 1Yn –12 2Yn –12 REFCLK 12 PCICLK 6 IOL Low-level output current CPUCLK 6 mA 1Yn 12 2Yn 12 TA Operating free-air temperature 0 70 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C MIN TYP † MAX UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN TYP † MAX UNIT VIK VCC = 3.135 V, II = –18 mA –1.2 –1.2 V IOH = –12 mA REFCLK 2.5 2.4 IOH = –6 mA PCICLK 2.5 2.4 VOH VCC = 3.135 V IOH = –6 mA CPUCLK 2.5 2.4 VOH CC IOH = –12 mA 1Yn 2.5 2.4 IOH =1 2 m A 2Yn 25 24IOH = –12 mA 2Yn 2.5 2.4 IOL = 12 mA REFCLK 0.4 0.5 IOL = 6 mA PCICLK 0.4 0.5 VOL VCC = 3.135 V IOL = 6 mA CPUCLK 0.4 0.5 VOL CC IOL = 12 mA 1Yn 0.4 0.5 IOL =1 2m A 2Yn 04 05IOL = 12 mA 2Yn 0.4 0.5 II VCC = 3.6 V, VI = VCC or GND ±1 ±1 mA IOZ VCC = 3.6 V, VO = 3 V or 0 ±1 ±1 mA V3 6 V I0 Outputs high 1 ICC VCC = 3.6 V, VI=V CC or GND IO = 0, Outputs low 1 mAVI = VCC or GND Outputs disabled 1 C i VI = 3.135 V or 0 6 pF C o VI = 3.135 V or 0 6 pF † All typical values are at VCC = 3.3 V, TA = 25/C0095C. timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT Stabilization time‡ After SEL1, SEL0 5 msStabilization time ‡ After power up 5 ms ‡ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable.
PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V, TA = 25°C VCC = 3.135 V to 3.6 V, TA = 0°C to 70°C UNIT(INPUT) (OUTPUT) MIN TYP MAX MIN MAX tPLH 1A 1Yn 1.5 3.5 1.2 3.8 nstPLH 2A 2Yn 1.5 3.5 1.2 3.8 ns tPHL 1A 1Yn 1.5 3.5 1.2 3.8 nstPHL 2A 2Yn 1.5 3.5 1.2 3.8 ns tPZH OE 1Yn 2.5 7 2 7.5 nstPZH OE 2Yn 2.5 7 2 7.5 ns tPZL OE 1Yn 2.5 7 2 7.5 nstPZL OE 2Yn 2.5 7 2 7.5 ns tPHZ OE 1Yn 2.5 7 2 7.5 nstPHZ OE 2Yn 2.5 7 2 7.5 ns tPLZ OE 1Yn 2.5 7 2 7.5 nstPLZ OE 2Yn 2.5 7 2 7.5 ns 1Yn 350 350 tsk(o) 2Yn 350 350 ps() Any Y 500 500 tsk(p) 1Yn and 2Yn 1 1 ns † CPUCLK ±250 Jitter(pk pk)† CPUCLK ±250 psJitter(pk-pk)† PCICLK ±350 s PCICLK 30 SEL0 = L, SEL1 = L 20 tc(period)† CPUCLK SEL0 = H, SEL1 = L 16.7 ns SEL0 = L, SEL1 = H D t c cle† CPUCLK 45% 55% D uty cycle† PCICLK 45% 55% tr‡ 2 ns tf‡ 2 ns † Specifications are applicable only after the PLL stabilization time has elapsed. ‡ Rise and fall times are characterized using the load circuits shown in Figure 1.
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The difference between the fastest and slowest of tPLHn ( n = 1 , 2 ,..., 8 ) . The difference between the fastest and slowest of tPHLn ( n = 1 , 2 ,..., 8 ) . Pulse skew, tsk(p), is calculated as the greater of | tPLHn – tPLHn | (n = 1, 2,..., 8 ) . Figure 2. Waveforms for Calculation of tsk(o) and tsk(p)
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDC913DW OBSOLETE SOIC DW 24 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 Addendum-Page 1
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated