CDC857

CDC857 TI | Alldatasheet

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CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM

Applications

/C0068Distributes One Differential Clock Input to Ten Differential Outputs /C0068External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Clock Input /C0068Operates at VCC = 2.5 V and AVCC = 3.3 V /C0068Packaged in Plastic 48-Pin (DGG) Thin Shrink Small-Outline Package (TSSOP) /C0068Spread Spectrum Clocking Tracking Capability to Reduce EMI

description

The CDC857-2 and CDC857-3 are high-perfor- mance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance state (3-state). Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV CC to ground. If AVCC is at GND and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized for operation from 0°C to 85°C. Copyright  1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. GND VCC GND GND VCC VCC CLK CLK VCC AV CC AGND GND VCC GND GND V CC GND GND V CC G FBIN FBIN VCC FBOUT FBOUT GND V CC GND DGG PACKAGE (TOP VIEW)

CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

H < 20 MHz < 20 MHz Z Z Z Z OFF logic symbol FBOUT FBOUT Clk Clk FBIN FBIN PLL G AV CC = 3.3 V Test Mode Logic AV CC NOTE A: All outputs are connected to VCC = 2.5 V.

CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SPECIAL TEST MODES INPUTS OUTPUTS COMMENTS VCC AV CC G CLK † Y Y FBOUT FBOUT COMMENTS ON 0 V L L Z Z Z Z Clock Mode ON 0 V L H Z Z Z Z Clock Mode ON 0 V H L L H L H Clock Mode ON 0 V H H H L H L Clock Mode ON UP ‡ ↓§ LZ Z L H PLL Mode ON UP ‡ ↓§ H Z Z H L PLL Mode † Only one signal shown for this differential input. ‡ AV CC ramped up after two (2) high-to-low transitions on G input & G being low. § At least two (2) high-to-low transitions during AVCC = 0. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AGND 17 Ground Analog ground. AGND provides the ground reference for the analog circuitry. AV CC 16 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (G = 0), the PLL is powered down. CLK CLK I Clock input, CLK provides the clock signal to be distributed by the CDC857 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN FBIN I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. FBOUT FBOUT O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. G 37 I Output bank enable. G is the output enable for outputs Y and Y. When G is low outputs Y are disabled to a high-impedance state. When G is high, all outputs Y are enabled and switch at the same frequency as CLK. GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 Ground Ground VCC 4, 11, 12, 15, 21, 28, 34, 38, 45 Power Power supply Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, 3, 5, 10, 20, 22, 46, 44, 39, 29, O Clock outputs. These outputs provide low-skew copies of CLK. Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, 2, 6, 9, 19, 23, 47, 43, 40, 30, O Clock outputs. These outputs provide low-skew copies of CLK.

CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) MIN NOM MAX UNIT Supply voltage, VCC 2.3 2.7 V Analog supply voltage AVCC CDC857–2 2.3 2.7 V Analog supply voltage, AV CC CDC857–3 3 3.6 V Low–level input voltage, VIL(G) G input 0.3 × VCC V High–level input voltage, VIH(G) G input 0.7 × VCC V DC input signal voltage (see Note 5) CLK, FBIN –0.3 VCC +0.3 V Differential input signal voltage, VID dc CLK, FBIN 0.35 VCC +0.6 Vgg , ID (see Note 6) ac CLK, FBIN 0.7 VCC +0.6 V Differential cross-point input voltage (see Note 7) VCC /2–0.2 VCC /2 VCC /2+0.2 V High-level output current, IOH –12 mA Low-level output current, IOL 12 mA Input slew rate, SR 1 V/ns Operating free-air temperature, TA 0 85 °C NOTES: 4. Unused inputs must be held high or low to prevent them from floating. 5. DC input signal voltage specifies the allowable dc execution of differential input. 6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary input level (see figure 3). 7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing.

CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK Input voltage All input pinsVCC = 2.3 V, I I = –18 mA –1.2 V VOH High level output voltage VCC = min to max, IOH= –1 mA VCC –0.1 VVOH High-level output voltage VCC = 2.3 V, I OH = –12 mA 1.7 V VOL Low level output voltage VCC = min to max, IOL = 1 mA 0.1 VVOL Low-level output voltage VCC = 2.3 V, I OL = 12 mA 0.6 V IOH High-level output current VCC = 2.3 V, V O = 1 V –18 –32 mA IOL Low-level output current VCC = 2.3 V, VO = 1.2 V 26 35 mA VO Output voltage swing For load condition see Figure 3 1.1 VCC –0.4 V II Input current G VCC = 2.7 V, V I = 0 V to 2.7 V ±10 mAII Input current CLK, FBIN VCC = 2.7 V, V I = 0 V to 2.7 V ±10 mA IOZ High impedance output current VCC =2 7 V V O =V CC or GND ±10 mAIOZ High-impedance output current VCC = 2.7 V, VO = VCC or GND ±10 mA VOC Output crossing point voltage‡ (VCC /2)–

0.1 VCC /2 (VCC /2)+

0.1 V ICCZ Supply current, disabled AV CC and VCC = max, G = L or no input CLK signal 500 800 mA lCC Supply current on VCC(see Figure 7) VCC = 2.7 V, f O = 167 MHz, All outputs switching 16 pF in 60 W environment, See Figure 3 235 300 mA AICC Supply current on CDC857–2 AV CC = 2.7 V, f O = 167 MHz 9 12 mAAICC Su ly current on AV CC CDC857–3 AV CC = 3.6 V, f O = 167 MHz 15 19 mA C I Input capacitance VCC = 2.5 V, V I = VCC or GND 2 pF C O Output capacitance VCC = 2.5 V,VO = VCC or GND 3 pF † All typical values are at respective nominal VCC . ‡ The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-W resistor, where VTR is the true input signal voltage and VCP is the complementary input signal voltage (see Figure 3).

CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999

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timing requirements over recommended ranges or supply voltage and operating free–air temperature PARAMETER TEST CONDITIONS MIN MAX UNIT fC Clock frequency 66 167 MHz Input clock duty cycle 40% 60% Stabilization time† 0.1 ms † Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed–frequency, fixed–phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. switching characteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tPLH ‡ Low–to high level propagation delay time (see Figure 5) CLK mode/CLK to any output 1.5 3.5 6 ns tPHL ‡ High–to low level propagation delay time (see Figure 5) CLK mode/CLK to any output 1.5 3.5 6 ns ten Output enable time CLK mode/G to any Y output 3 ns tdis Output disable time CLK mode/G to any Y output 3 ns t(jitt ) Jitter (peak topeak)

66 MHz 120

pst(jitter) Jitter (peak-to–peak) 100/125/133/167 MHz 75 ps t(jitt ) Jitter (cycle to cycle)

66 MHz 110

pst(jitter) Jitter (cycle-to-cycle) 100/125/133/167 MHz 65 ps t(phase error) Phase error (see Figure 4) All differential input and output termi- –150 150 ps tskew(0) Output skew (see Figure 4) All differential in ut and out ut termi- nals are terminated with 120 W /

16 F h i Fi 2

tskew(p) Pulse skew 16 pF as shown in Figure 2 100 ps Duty cycle§ (see Figure 6) 66 MHz to 100 MHz 49.5% 50.5% D uty cycle§ (see Figure 6)

101 MHz to 167 MHz 49% 51%

tr, tf Output rise and fall times (20% – 80%)Load = 120 W /16 pF 650 800 950 ps ‡ Refers to transition of noninverting output. § While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = twH /tc, were the cycle time (tc) decreases as the frequency goes up.

Table 1. Clock Structure and SDRAM Loads per Clock

120 WCLK

120 W16 pF

Figure 1. Clock Structure #1

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 2. Clock Structure #2 Figure 3 shows the differential clocks are directly terminated by a 120-W resistor. Figure 3. Differential Signal Using Direct Termination Resistor

Figure 4. Phase Error and Skew Waveforms

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 5. Propagation Delay Time; tPLH , tPHL Figure 6. Output Duty Cycle NOTE A: Cycle-to-cycle jitter = |tc(n) – tc(n+1)| over 2000 consecutive cycles. Figure 7. Cycle-to-Cycle Jitter

CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PIN SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: B. All linear dimensions are in millimeters. C. This drawing is subject to change without notice. D. Body dimensions do not include mold protrusion not to exceed 0,15. E. Falls within JEDEC MO-153

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