CDC706PWR

CDC706 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 41

Technical content

Features

(SSC) for Lowering System EMI Programmable Output Slew-Rate Control (SRC) for Lowering System EMI 3.3-V Device Power Supply Industrial Temperature Range C to C Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. Pro-Clock is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2006 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com

DESCRIPTION

protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The CDC706 is one of the smallest and powerful PLL synthesizer multiplier divider available today. Despite its small physical outlines, the CDC706 is very flexible. It has the capability to produce an almost independent output frequency from a given input frequency. The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller. To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from up to 511 for the M-Divider and from up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output. The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27-MHz). The CDC706 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 300 MHz and optimized for zero-ppm factors. PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise. Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL. The device provides customized applications. It is preprogrammed with a factory default configuration (see Figure and can be reprogrammed to a different application configuration via the serial SMBus Interface. Two free programmable inputs, and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc). The CDC706 has three power supply pins, V CC V CCOUT1 and V CCOUT2 V CC is the power supply for the device. It operates from a single 3.3-V supply voltage. V CCOUT1 and V CCOUT2 are the power supply pins for the outputs. V CCOUT1 supplies the outputs and and V CCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 At output voltages lower than 3.3 the output current drive is limited. The CDC706 is characterized for operation from C to Submit Documentation Feedback

www.ti.com PLL1 XO or 2□LVCMOS or Differential Input MUX MUX PLL3 PFD Filter VCO PLL2 w/□SSC PFD Filter VCO SO/CLK_SEL SCLOCK Output□Switch□Matrix LV CMOS LV CMOS LV CMOS LV CMOS LV CMOS LV CMOS PROGRAMMING LOGIC SMBUS LOGIC PFD Filter VCO SDATA VCO1□Bypass VCO2□Bypass VCO3□Bypass MUX 6□x□Programmable□7-Bit□Divider□P0,□P1,□P2,□P3,□P4,□P5,□and□Inversion□Logic 5□x□6□Programmable□Switch A PLL Bypass VCC GND V CCOUT1 GND V CCOUT2 prg. 9□Bit Divider□M prg.□12□Bit Divider□N prg.□9□Bit Divider□M prg.□12□Bit Divider□N prg.□9□Bit Divider□M prg.□12□Bit Divider□N Crystal□or Clock□InputCLK_IN1 Factory□Prg. CLK_IN0 SSC On/Off 6□x□6□Programmable□Switch□B 5x6 − Switch A Input CLK (PLL Bypass) PLL 1 PLL 2 non SSC PLL 2 w/ SSC PLL 3 6x6 − Switch B7-Bit Divider Programming CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 FUNCTIONAL BLOCK DIAGRAM OUTPUT SWITCH MATRIX Submit Documentation Feedback

www.ti.com ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL RESISTANCE CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 TERMINAL FUNCTIONS TERMINAL I/O NO. 11, 12, 15, to O LVCMOS outputs 16, 19, Dependent on SMBus settings, CLK_IN0 is the crystal oscillator input and can also be used CLK_IN0 I as LVCMOS input or as positive differential signal inputs. Dependent on SMBus settings, CLK_IN1 is serving as the crystal oscillator output or can be CLK_IN1 I/O the second LVCMOS input or the negative differential signal input. V CC Power 3.3-V power supply for the device. V CCOUT1 Power Power supply for outputs Y0, Y1. V CCOUT2 Power Power supply for outputs Y2, Y3, Y4, Y5. GND 13, Ground Ground User programmable control input (PLL bypass or power-down mode) or CLK_SEL S0, I (selects one of two LVCMOS clock inputs), dependent on the SMBus settings; LVCMOS CLK_SEL inputs; internal pullup 150 k Ω User programmable control input (output enable/disable or all output low), dependent on I the SMBus settings; LVCMOS inputs; internal pullup 150 k Ω SDATA I/O Serial control data input/output for SMBus controller; LVCMOS input SCLOCK I Serial control clock input for SMBus controller; LVCMOS input over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT V CC Supply voltage range 0.5 to 4.6 V V I Input voltage range (2) 0.5 to V CC 0.5 V V O Output voltage range (2) 0.5 to V CC 0.5 V I I Input current I V I V CC mA I O Continuous output current mA T stg Storage temperature range to 150 C T J Maximum junction temperature 125 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. for TSSOP20 (PW) Package (1) (2) PARAMETER AIRFLOW (LFM) C/W 66.3 150 59.3 θ JA Thermal resistance junction-to-ambient 250 56.3 500 51.9 θ JC Thermal resistance junction-to-case 19.7 (1) The package thermal impedance is calculated in accordance with JESD and JEDEC2S2P (high-k board). (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com Submit Documentation Feedback

www.ti.com RECOMMENDED OPERATING CONDITIONS RECOMMENDED CRYSTAL SPECIFICATIONS TIMING REQUIREMENTS CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V CC Device supply voltage 3.3 3.6 V V CCOUT1 Output Y0, supply voltage 2.3 3.6 V V CCOUT2 Output Y2, Y3, Y4, supply voltage 2.3 3.6 V V IL Low level input voltage LVCMOS 0.3 V CC V V IH High level input voltage LVCMOS 0.7 V CC V V Ithresh Input voltage threshold LVCMOS 0.5 V CC V V I Input voltage range LVCMOS 3.6 V ID Differential input voltage 0.1 V V IC Common-mode for differential input voltage 0.2 V cc 0.6 V I OH OL Output current (3.3 mA I OH OL Output current (2.5 mA C L Output load LVCMOS pF T A Operating free-air temperature C MIN NOM MAX UNIT f Xtal Crystal input frequency range (fundamental mode) MHz ESR Effective series resistance (1) (2) Ω C IN Input capacitance CLK_IN0 and CLK_IN1 pF (1) For crystal frequencies above MHz the effective series resistor should not exceed Ω to assure stable start-up condition. (2) Maximum Power Handling (Drive Level) see Figure over recommended ranges of supply voltage, load, and operating-free air temperature MIN NOM MAX UNIT CLK_IN REQUIREMENTS PLL mode 200 f CLK_IN CLK_IN clock input frequency (LVCMOS or Differential) MHz PLL bypass mode 200 t r t f Rise and fall time CLK_IN signal (20% to 80%) ns duty REF Duty cycle CLK_IN at V CC 40% 60% SMBus TIMING REQUIREMENTS (see Figure f SCLK SCLK frequency 100 kHz t h(START) START hold time µ s t w(SCLL) SCLK low-pulse duration 4.7 µ s t w(SCLH) SCLK high-pulse duration µ s t su(START) START setup time 0.6 µ s t h(SDATA) SDATA hold time 0.3 µ s t su(SDATA) SDATA setup time 0.25 µ s t r SCLK SDATA input rise time 1000 ns t f SCLK SDATA input fall time 300 ns t su(STOP) STOP setup time µ s t BUS Bus free time 4.7 µ s t POR Time in which the device must be operational after power-on reset 500 ms Submit Documentation Feedback

www.ti.com DEVICE CHARACTERISTICS CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT OVERALL PARAMETER All PLLs on, all outputs on, I CC Supply current (2) f OUT MHz, f CLK_IN MHz, 115 mA f (VCO) 160 MHz Power down current. Every circuit I CCPD f IN MHz, V CC 3.6 V µ A powered down except SMBus Supply voltage V CC threshold for V (PUC) 2.1 V power up control circuit All PLLs 200 Normal speed-mode (3) VCO frequency of internal PLL (any f (VCO) PLL2 with SSC 167 MHz of three PLLs) High-speed mode (3) 180 300 V CC 2.5 V 250 LVCMOS output frequency range (4) f OUT MHz See Figure V CC 3.3 V 300 LVCMOS PARAMETER V (IK) LVCMOS input voltage V CC I I mA 1.2 V LVCMOS input current (CLK_IN0 and I I V I V or V CC V CC 3.6 V µ A CLK_IN1) I IH LVCMOS input current (S1/S0) V I V CC V CC 3.6 V µ A I IL LVCMOS input current (S1/S0) V I V CC 3.6 V -35 -10 µ A Input capacitance at CLK_IN0 and C I V I V or V CC pF CLK_IN1 LVCMOS PARAMETER FOR V CCOUT 3.3-V Mode V CCOUT I OH 0.1 mA 2.9 V OH LVCMOS high-level output voltage V CCOUT I OH mA 2.4 V V CCOUT I OH mA 2.1 V CCOUT I OL 0.1 mA 0.1 V OL LVCMOS low-level output voltage V CCOUT I OL mA 0.5 V V CCOUT I OL mA 0.85 All PLL bypass t PLH Propagation delay ns t PHL VCO bypass Rise and fall time for output t V CCOUT 3.3 V (20% 80%) 1.7 3.3 4.8 ns slew rate Rise and fall time for output t V CCOUT 3.3 V (20% 80%) 1.5 2.5 3.2 ns slew rate Rise and fall time for output t V CCOUT 3.3 V (20% 80%) 1.2 1.6 2.1 ns slew rate Rise and fall time for output t V CCOUT 3.3 V (20% 80%) 0.4 0.6 ns slew rate (default configuration) f OUT MHz PLL, Output f OUT 245.76 MHz t jit(cc) Cycle-to-cycle jitter (5) (6) ps f OUT MHz 125 155 PLLs, Outputs f OUT 245.76 MHz (1) All typical values are at respective nominal V CC (2) For calculating total supply current, add the current from Figure Figure and Figure Using high-speed mode of the VCO reduces the current consumption. See Figure (3) Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in Byte Bit [7:5]. The min f (VCO) can be lower but impacts jitter-performance. (4) Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow). See Figure (5) 50000 cycles. (6) Jitter depends on configuration. Jitter data is normal t r f input frequency 3.84 MHz, f (VCO) 245.76 MHz. Submit Documentation Feedback

www.ti.com CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT f OUT MHz PLL, Output f OUT 245.76 MHz t jit(per) Peak-to-peak period jitter (5) (6) ps f OUT MHz 145 180 PLLs, Outputs f OUT 245.76 MHz 105 Output skew (see (7) and Table 1.6-ns rise/fall time at t sk(o) 200 ps f (VCO) 150 MHz, Pdiv odc Output duty cycle (8) f (VCO) 100 MHz, Pdiv 45% 55% LVCMOS PARAMETER FOR V CCOUT 2.5-V Mode (9) V CCOUT 2.3 I OH 0.1 mA 2.2 V OH LVCMOS high-level output voltage V CCOUT 2.3 I OH mA 1.7 V V CCOUT 2.3 I OH mA 1.5 V CCOUT 2.3 I OL 0.1 mA 0.1 V OL LVCMOS low-level output voltage V CCOUT 2.3 I OL mA 0.5 V V CCOUT 2.3 I OL mA 0.85 All PLL bypass t PLH Propagation delay ns t PHL VCO Bypass Rise and fall time for output t V CCOUT 2.5 V (20% 80%) 3.9 5.6 ns slew rate Rise and fall time for output t V CCOUT 2.5 V (20% 80%) 1.8 2.9 4.4 ns slew rate Rise and fall time for output t V CCOUT 2.5 V (20% 80%) 1.3 3.2 ns slew rate Rise and fall time for output t V CCOUT 2.5 V (20% 80%) 0.4 0.8 1.1 ns slew rate (default configuration) f OUT MHz 105 PLL, Output f OUT 245.76 MHz t jit(cc) Cycle-to-cycle jitter (10) (11) ps f OUT MHz 130 160 PLLs, Outputs f OUT 245.76 MHz f OUT MHz 110 PLL, Output f OUT 245.76 MHz t jit(per) Peak-to-peak period jitter (10) (11) ps f OUT MHz 145 180 PLLs, Outputs f OUT 245.76 MHz 105 Output skew (see (12) and Table 2-ns rise/fall time at t sk(o) 250 ps f (VCO) 150 MHz, Pdiv odc Output duty cycle (13) f (VCO) 100 MHz, Pdiv 45% 55% SMBus PARAMETER SCLK and SDATA input clamp V IK V CC I I mA 1.2 V voltage I I SCLK and SDATA input current V I V or V CC V CC 3.6 V µ A V IH SCLK input high voltage 2.1 V V IL SCLK input low voltage 0.8 V V OL SDATA low-level output voltage I OL mA, V CC V 0.4 V (7) The t sk(o) specification is only valid for equal loading of all outputs. (8) odc depends on output rise and fall time r f The data is for normal t r f and is valid for both SSC on and off. (9) T here is a limited drive capability at output supply voltage of 2.5 For proper termination, see application report SCAA080 (10) 50000 cycles. (11) Jitter depends on configuration. Jitter data is normal t r f input frequency 3.84 MHz, f (VCO) 245.76 MHz. (12) The t sk(o) specification is only valid for equal loading of all outputs. (13) odc depends on output rise and fall time r f The data is for normal t r f and is valid for both SSC on and off. Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION Yn 1□k 1□k 10□pF LVCMOS CDC706 TYPICAL CHARACTERISTICS V =□3.3□V, M□div□=□1, N□div□=□2, P div□=□1, VCO□normal-speed□mode CC PLL 1□+□PLL 2□+□PLL3 PLL 1□+□PLL 2 f -□[MHz]VCO 210 I -□[mA]CC PLL 1 20017016015090 140130120 120 110 110 100 100 190180 CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Input capacitance at SCLK V I V or V CC pF C I Input capacitance at SDATA V I V or V CC pF Figure Test Load Figure I CC vs Number of PLLs and VCO Frequency (VCO at Normal-Speed Mode, Byte Bit [7:5]) Submit Documentation Feedback

www.ti.com V =□3.3□V, M□div□=□1, N□div□=□2, P div□=□1, VCO□high-speed□mode CC PLL 1□+□PLL 2□+□PLL3 PLL 1□+□PLL 2 f -□[MHz]VCO 310 I -□[mA] CC PLL 1 300250190180 170160150 120 140 110 130 100 270260240230200 220210 290280 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 6□Outputs 5□Outputs 4□Outputs 3□Outputs 2□Outputs 1□Outputs V =□3.3□V, M□div□=□1, N□div□=□2, P div□=□1 CC f -□[MHz]VCO I -□[mA] CC CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) Figure I CC vs Number of PLLs and VCO Frequency (VCO at High-Speed Mode, Byte Bit [7:5]) Figure I CCOUT vs Number of Outputs and VCO Frequency Submit Documentation Feedback

www.ti.com 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 VOH at□V =□3.6□VCCOUT VOH at□V =□2.3□VCCOUT VOL at□V =□3.6□VCCOUTVOL at□V =□2.3□VCCOUT f -□[MHz]OUT VOUT□-□[V] V =□3.3□V, M□div□=□4, N□div□=□15, P div□=□1 CC CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) Figure Output Swing vs Output Frequency Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION SMBus Data Interface Data Protocol Slave Receiver Address bits) CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. It follows the SMBus specification Version 2.0, which is based upon the principals of operation of I More details of the SMBus specification can be found at http:// www.smbus.org Through the SMBus, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the SMBus data interface initialize to their default setting upon power-up; therefore, using this interface is optional. The clock device register changes are normally made upon system initialization, if any are required. The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the controller. For Block Write/Read operations, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individually addressed bytes. Once a byte has been sent, it is written into the internal register and effective immediately with the rising edge of the ACK bit. This applies to each transferred byte, independent of whether this is a Byte Write or a Block Write sequence. The offset of the indexed byte is encoded in the command code, as described in Table The Block Write and Block Read protocol is outlined in Figure and Figure while Figure and Figure outlines the corresponding Byte Write and Byte Read protocol. R Table Command Code Definition Bit (6:0) Byte Offset for Byte Read and Byte Write operation. For Block Read and Block Write operation, these bits have to be 000 0000. Submit Documentation Feedback

www.ti.com 1 7 1 1 8 1 1 S Slave Address Wr A Data Byte A P S Start Condition Sr Reapeated Start Condition Rd Read (Bit Value = 1) Wr Write (Bit Value = 0) A Acknowledge (ACK = 0 and NACK = 1) P Stop Condition PE Packet Error Master to Slave Transmission Slave to Master Transmission Byte Write Programming Sequence Byte Read Programming Sequence Block Write Programming Sequence (1) CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Figure Generic Programming Sequence S Slave Address Wr A CommandCode A Data Byte A P Figure Byte Write Protocol S Slave Address Wr A CommandCode A S Slave Address Rd A Data Byte A P Figure Byte Read Protocol S Slave Address Wr A CommandCode A Byte Count N A Data Byte A Data Byte A Data Byte N A P (1) Data Byte is reserved for revision code and vendor identification. However, this byte is used for internal test. Do not write into it other than 0000 0000. Figure Block Write Protocol Submit Documentation Feedback

www.ti.com Block Read Programming Sequence P S P SCLK SDATA ABit 7 (MSB) Bit 6 Bit 0 (LSB) th(SDATA) tsu(SDATA) tsu(START) t(BUS) th(START) tr(SM) tr(SM) tf(SM) tf(SM) tW(SCLH)tW(SCLL) tsu(STOP) VIH(SM) VIL(SM) VIH(SM) VIL(SM) SMBus Hardware Interface SDATA SCLK SMB□Host CDC706 CBUS CBUS RP RP CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 S Slave Address Wr A CommandCode A Sr Slave Address Rd A Byte Count N A Data Byte A Data Byte N A P Figure 10. Block Read Protocol Figure 11. Timing Diagram Serial Control Interface The following diagram shows how the CDC706 clock synthesizer is connected to the SMBus. Note that the current through the pullup resistors p must meet the SMBus specifications (min 100 µ max 350 µ A). If the CDC706 is not connected to SMBus, the SDATA and SCLK inputs have to be connected with k Ω resistors to V CC to avoid floating input conditions. Figure 12. SMBus Hardware Interface Submit Documentation Feedback

www.ti.com CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Table Register Configuration Command Bitmap Adr Bit Bit Bit Bit Bit Bit Bit Bit Byte Revision Code Vendor Identification Byte PLL1 Reference Divider M 9-Bit [7:0] Byte PLL1 Feedback Divider N 12-Bit [7:0] PLL1 Ref Byte PLL1 Mux PLL2 Mux PLL3 Mux PLL1 Feedback Divider N 12-Bit [11:8] Dev M [8] Byte PLL2 Reference Divider M 9-Bit [7:0] Byte PLL2 Feedback Divider N 12-Bit [7:0] PLL1 fvco PLL2 fvco PLL3 fvco PLL2 Ref Byte PLL2 Feedback Divider N 12-Bit [11:8] Selection Selection Selection Dev M [8] Byte PLL3 Reference Divider 9-Bit M [7:0] Byte PLL3 Feedback Divider N [12-Bit 7:0] PLL3 Ref Byte PLL Selection for (Switch PLL3 Feedback Divider N 12-Bit [11:8] Dev M [8] Inp. Clock Byte PLL Selection for (Switch Configuration Inputs Configuration Inputs Selection Byte Input Signal Source PLL Selection for (Switch PLL Selection for (Switch Byte Reserved Power Down PLL Selection for (Switch PLL Selection for (Switch Byte Reserved 7-Bit Divider [6:0] Byte Reserved 7-Bit Divider [6:0] Byte Reserved 7-Bit Divider [6:0] Byte Reserved 7-Bit Divider [6:0] Byte Reserved 7-Bit Divider [6:0] Byte Reserved 7-Bit Divider [6:0] Inv. or Enable or Byte Reserved Slew-Rate Control Divider Selection (Switch Non-Inv Low Inv. or Enable or Byte Reserved Slew-Rate Control Divider Selection (Switch Non-Inv Low Inv. or Enable or Byte Reserved Slew-Rate Control Divider Selection (Switch Non-Inv Low Inv. or Enable or Byte Reserved Slew-Rate Control Divider Selection (Switch Non-Inv Low Inv. or Enable or Byte Reserved Slew-Rate Control Divider Selection (Switch Non-Inv Low Inv or Enable or Byte Reserved Slew-Rate Control Divider Selection (Switch Non-Inv Low Spread Spectrum (SSC) Modulation Byte Reserved Frequency Selection for SSC Selection Byte Reserved 7-Bit Byte Count Submit Documentation Feedback

www.ti.com Default Device Setting PLL1 XO or 2LVCMOS or Differential Input MUX MUX Divider□M MUX Divider□M 375 PLL3 PFD Filter VCO PLL2 w/□SSC PFD Filter VCO Divider□N Divider□N 250 Divider□N 3136 SO/CLK_SEL SCLOCK Output□Switch□Matrix 27□MHz PROGRAMMING LOGIC SMBUS LOGIC PFD Filter VCO SDATA P0-Div P1-Div P2-Div P3-Div P4-Div P5-Div fVCO3 =□225.792□MHz CLK_IN0 CLK_IN1 27□MHz Crystal 14□pF 14□pF SSC-OFF 27□MHz 27□MHz 27□MHz 27□MHz LV CMOS LV CMOS LV CMOS LV CMOS LV CMOS LV CMOS 27□MHz Divider□M fVCO1 =□216□MHz fVCO2 =□250□MHz (1) CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 The CDC706 is pre-programmed with a factory default configuration as shown below. This puts the device in an operating mode without the need to program it first. The default setting appears after power is switched on or after a power-down/up sequence until it is re-programmed by the user to a different application configuration. A new register setting is programmed via the serial SMBUS Interface. A different default setting can be programmed upon customer request. Contact a Texas Instruments sales or marketing representative for more information. NOTE: All outputs are enabled and in non-inverting mode. S0, S1, and SSC comply according the default setting described in Byte and Byte respectively. Figure 13. Default Device Setting The output frequency can be calculated: Submit Documentation Feedback

www.ti.com Functional read-/write-able, unless otherwise expressly mentioned. Byte (read only): Vendor Identification Bits [3:0]; Revision Code Bit [7:4] (1) Revision Code Vendor Identification X X X X (1) Byte is readable by "Byte Read sequency" only. Byte to Reference Divider M of PLL1, PLL2, PLL3 (1) Div by Default (2) (3) Not allowed 509 510 511 (1) By selecting the PLL divider factors, M N and MHz fvco 300 MHz. (2) Unless customer specific setting. (3) Default setting of divider M for PLL1 for PLL2 and for PLL3 375. Byte to Feedback Divider N of PLL1, PLL2, PLL3 (1) N11 N10 Div by Default (2) (3) Not allowed 4093 4094 4095 (1) By selecting the PLL divider factors, M N and MHz fvco 300 MHz. (2) Unless customer specific setting. (3) Default setting of divider N for PLL1 for PLL2 250 and for PLL3 3136. Byte Bit [7:5]: PLL (VCO) Bypass Multiplexer PLLxMUX PLL (VCO) MUX Output Default (1) PLLx Yes VCO bypass (1) Unless customer specific setting. Byte Bit [7:5]: VCO Frequency Selection Mode for each PLL (1) PLLxFVCO VCO Frequency Range Default (2) 80-200 MHz 180-300 MHz Yes (1) This bit selects the normal-speed mode or the high-speed mode for the dedicated VCO in PLL1, PLL2 or PLL3. At power-up, the high-speed mode is selected, f VCO is 180-300 MHz. In case of higher f VCO this bit has to be set to [1]. (2) Unless customer specific setting. Submit Documentation Feedback

www.ti.com CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Byte to 12: Outputs Switch Matrix (5x6 Switch PLL Selection for P-Divider P0-P5 SWAPx2 SWAPx1 SWAPx0 Any Output Px Default (1) PLL bypass (input clock) PLL1 P2, P3, P4, PLL2 non-SSC PLL2 SSC (2) PLL3 Reserved Reserved Reserved (1) Unless customer specific setting. (2) PLL2 has a SSC output and non-SSC output. If SSC bypass is selected (see Byte 25, Bit [6:4]), the SSC circuitry of PLL2 is powered-down and the SSC output is reset to logic low. The non-SSC output of PLL2 is not affected by this mode and can still be used. Byte 10, Bit [1:0]: Configuration Settings of Input S0/CLK_SEL S01 S00 Function Default (1) If is low, the PLLs and the clock-input stage are going into power-down mode, outputs are in Yes 3-state, all actual register settings will be maintained, SMBus stays active (2) If is low, the PLL and all dividers (M-Div and P-Div) are bypassed and PLL is in power-down, all outputs are active (inv. or non-inv.), actual register settings will be maintained, SMBus stays active; this mode is useful for production test; CLK_SEL (input clock selection overwrites the CLK_SEL setting in Byte 10, Bit [4]) (3) CLK_SEL is set low selects CLK_IN_IN0 CLK_SEL is set high selects CLK_IN_IN1 Reserved (1) Unless customer specific setting. (2) Power-down mode overwrites 3-state or low-state of setting in Byte 10, Bit [3:2]. (3) If the clock input (CLK_IN0/CLK_IN1) is selected as crystal input or differential clock input (Byte 11, Bit [7:6]) then this setting is not relevant. Byte 10, Bit [3:2]: Configuration Settings of Input S11 S10 Function Default (1) If is set low, all outputs are switched to a low-state (non-inv.) or high-state (inv.); Yes If is set low, all outputs are switched to a 3-state Reserved Reserved (1) Unless customer specific setting. Byte 10, Bit [4]: Input Clock Selection (1) CLKSEL Input Clock Default (2) CLK_IN0 Yes CLK_IN1 (1) This bit is not relevant, if crystal input or differential clock input is selected, Byte 11, Bit [7:6]. (2) Unless customer specific setting. Byte 11, Bit [7:6]: Input Signal Source (1) IS1 IS0 Function Default (2) CLK_IN0 is Crystal Oscillator Input and CLK_IN1 is serving as Crystal Oscillator Output. Yes CLK_IN0 and CLK_IN1 are two LVCMOS Inputs. CLK_IN0 or CLK_IN1 are selectable via CLK_SEL control pin. CLK_IN0 and CLK_IN1 serve as differential signal inputs. Reserved (1) In case the crystal input or differential clock input is selected, the input clock selection, Byte 10, Bit [4], is not relevant. (2) Unless customer specific setting. Submit Documentation Feedback

www.ti.com CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Byte 12, Bit [6]: Power-Down Mode (except SMBus) PD Power-Down Mode Default (1) Normal Device Operation Yes Power Down (2) (1) Unless customer specific setting. (2) In power down, all PLLs and the Clock-Input-Stage are going into power-down mode, all outputs are in 3-State, all actual register settings will be maintained and SMBus stays active. Power-Down Mode overwrites 3-State or Low-State of and setting in Byte 10. Byte to 18, Bit [6:0]: Outputs Switch Matrix 6x7-Bit Divider P0-P5 DIVYx6 DIVYx5 DIVYx4 DIVYx3 DIVYx2 DIVYx1 DIVYx0 Div by Default (1) (2) Not allowed 125 126 127 (1) Unless customer specific setting. (2) Default setting of divider 10, 20, 32, and Byte to 24, Bit [5:4]: LVCMOS Output Rise/Fall Time Setting at Y0-Y5 SRCYx1 SRCYx0 Yx Default (1) Nominal ns Nominal ns Nominal ns Nominal Yes (1) Unless customer specific setting. Byte to 24, Bit [2:0]: Outputs Switch Matrix x Switch Divider (P0-P5) Selection for Outputs Y0-Y5 SWBYx2 SWBYx1 SWBYx0 Any Output Yx Default (1) Divider Divider Divider Y0, Y1, Y2, Y3, Y4, Divider Divider Divider Reserved Reserved (1) Unless customer specific setting. Byte to 24, Bit [3]: Output Y0-Y5 Enable or Low-State ENDISYx Output Yx Default (1) Disable to low Enable Yes (1) Unless customer specific setting. Byte to 24, Bit [6]: Output Y0-Y5 Non-Inverting/Inverting INVYx Output Yx Status Default (1) Non-inverting Yes Inverting (1) Unless customer specific setting. Submit Documentation Feedback

www.ti.com CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Byte 25, Bit [3:0]: SSC Modulation Frequency Selection in the Range of kHz kHz (1) f vco (MHz) Modulation FSSC3 FSSC2 FSSC1 FSSC0 Default (2) Factor 100 110 120 130 140 150 160 167 5680 17.6 19.4 21.1 22.9 24.6 26.4 28.2 29.4 5412 18.5 20.3 22.2 24.0 25.9 27.7 29.6 30.9 5144 19.4 21.4 23.3 25.3 27.2 29.2 31.1 32.5 4876 20.5 22.6 24.6 26.7 28.7 30.8 32.8 34.2 4608 21.7 23.9 26.0 28.2 30.4 32.6 34.7 36.2 4340 23.0 25.3 27.6 30.0 32.3 34.6 36.9 38.5 4072 24.6 27.0 29.5 31.9 34.4 36.8 39.3 41.0 3804 26.3 28.9 31.5 34.2 36.8 39.4 42.1 43.9 f mod [kHz] 3536 28.3 31.1 33.9 36.8 39.6 42.4 45.2 47.2 3286 30.4 33.5 36.5 39.6 42.6 45.6 48.7 50.8 Yes 3000 33.3 36.7 40.0 43.3 46.7 50.0 53.3 55.7 2732 36.6 40.3 43.9 47.6 51.2 54.9 58.6 61.1 2464 40.6 44.6 48.7 52.8 56.8 60.9 64.9 67.8 2196 45.5 50.1 54.6 59.2 63.8 68.3 72.9 76.0 1928 51.9 57.1 62.2 67.4 72.6 77.8 83.0 86.6 1660 60.2 66.3 72.3 78.3 84.3 90.4 96.4 100.6 (1) The PLL has to be bypassed (turned off) when changing SSC Modulation Frequency Facto r on-the-fly. This can be done by following programming sequence: bypass PLL2 (Byte Bit 1); write new Modulation Factor (Byte 25); re-activate PLL2 (Byte Bit 0). (2) Unless customer specific setting. Submit Documentation Feedback

www.ti.com CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Byte 25, Bit [6:4]: SSC Modulation Amount (1) SSC2 SSC1 SSC0 Function Default (2) SSC Modulation Amount SSC bypass for PLL (3) Yes SSC Modulation Amount 0.1% (center spread) SSC Modulation Amount 0.25% (center spread) SSC Modulation Amount 0.4% (center spread) SSC Modulation Amount (down spread) SSC Modulation Amount 1.5% (down spread) SSC Modulation Amount (down spread) SSC Modulation Amount (down spread) (1) The PLL has to be bypassed (turned off) when changing SSC Modulation Amount on-the-fly. This can be done by following programming sequence: bypass PLL2 (Byte Bit 1); write new Modulation Amount (Byte 25); re-activate PLL2 (Byte Bit 0). (2) Unless customer specific setting. (3) If SSC bypass is selected, SSC circuitry of PLL2 is powered-down and the SSC output is reset to logic low. The non-SSC output of PLL2 is not affected by this mode and can still be used. Byte 26, Bit [6:0]: Byte Count (1) BC6 BC5 BC4 BC3 BC2 BC1 BC0 No. of Bytes Default (2) Not allowed Yes 125 126 127 (1) Defines the number of Bytes, which will be sent from this device at the next Block Read protocol. (2) Unless customer specific setting. Submit Documentation Feedback

www.ti.com FUNCTIONAL (CLK_IN0 and CLK_IN1) XO or 2LVCMOS or Differential Input CLK_IN0 CLK_IN1 Input□source□select (from□SMBUS□Register) CX0 CX1 crystal unit CICB CICB CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 The CDC706 as: Crystal oscillator input (default setting) Two independent single-ended LVCMOS inputs Differential signal input The dedicated clock input can be selected by the input signal source Bit [7:6] of Byte 11. Crystal Oscillator Inputs The input frequency range in crystal mode is MHz to MHz. The CDC706 uses a Pierce-type oscillator circuitry with included feedback resistance for the inverting amplifier. The user, however, has to add external capacitors C C to match the input load capacitor from the crystal (see Figure The required values can be calculated: C C x C L C ICB where C L is the crystal load capacitor as specified for the crystal unit and C ICB is the input capacitance of the device including the board capacitance (stray capacitance of PCB). For example, for a fundamental 27-MHz crystal with C L of pF and C ICB of pF, C C x pF) pF pF. It is important to use a short PCB trace from the device to the crystal unit to keep the stray capacitance of the oscillator loop to a minimum. Figure 14. Crystal Input Circuitry In order to ensure a stable oscillating, a certain drive power must be applied. The CDC706 gain. The drive level is the amount of power dissipated by the oscillating crystal unit and is usually specified in terms of power dissipated by the resonator (equivalent series resistance (ESR)). Figure gives the resulting drive level vs crystal frequency and ESR. Submit Documentation Feedback

www.ti.com 100 5 10 15 20 25 30 35 40 45 50 55 C = 18 pF U pk = 300 mV Frequency − MHz Pdrive − /C0109W /C012621 /C0109W ERS = 60 /C0087 ERS = 50 /C0087 ERS = 40 /C0087 ERS = 30 /C0087 ERS = 25 /C0087 ERS = 15 /C0087 XO or 2LVCMOS or Differential input CLK_IN0 CLK_IN1 CLK_SEL (A) Input Source□Select (From□SMBUS□Register) CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Figure 15. Crystal Drive Power For example, if a 27-MHz crystal with ESR of Ω is used and x C L is pF, the drive power is µ Drive level should be held to a minimum to avoid over driving the crystal. The maximum power dissipation is specified for each type of crystal in the oscillator specifications, i.e., 100 µ W for the example above. Single-Ended LVCMOS Clock Inputs When selecting the LVCMOS clock mode, CLK_IN0 and CLK_IN1 act as regular clock inputs pins and can be driven up to 200 MHz. Both clock inputs circuitry are equal in design and can be used independently to each other (see Figure The internal clock select bit, Byte 10, Bit [4], selects one of the two input clocks. CLK_IN0 is the default selection. There is also the option to program the external control pin S0/CLK_SEL as clock select pin, Byte 10, Bit [1:0]. The two clock inputs can be used for redundancy switching, i.e. to switch between a primary clock and secondary clock. Note a phase difference between the clock inputs may require PLL correction. Also in case of different frequencies between the primary and secondary clock, the PLL has to re-lock to the new frequency. CLK_SEL is optional and can be configured by SMBUS setting. Figure 16. LVCMOS Clock Input Circuitry Submit Documentation Feedback

www.ti.com XO or 2LVCMOS or Differential input CLK_IN0 CLK_IN1 Input□source□select (from□SMBUS) PLL Configuration and Setting MUX 9−Bit Divider M 1 .. 511 PLLx 12−Bit Divider N 1 .. 4095 PFD Filter VCO SSC (PLL2 only) Input Clock Programming PLL output SSC output (PLL2 Only) VCO Bypass CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Differential Clock Inputs The CDC706 supports differential signaling as well. In this mode, CLK_IN0 and CLK_IN1 pin serve as differential signal inputs and can be driven up to 200 MHz. The minimum magnitude of the differential input voltage is 100 mV over a differential common-mode input voltage range of 200 mV to V CC 0.6. If LVDS or LVPECL signal levels are applied, ac-coupling and a biasing structure is recommended to adjust the different physical layers (see Figure The capacitor removes the dc component of the signal (common-mode voltage), while the ac component (voltage swing) is passed on. A resistor pull-up and/or pull-down network represents the biasing structure used to set the common-mode voltage on the receiver side of the ac-coupling capacitor. DC coupling is also possible. Figure 17. Differential Clock Input Circuitry The CDC706 includes three PLLs which are equal in function and performance. Except PLL2 which in addition supports spread spectrum clocking (SSC) generation. Figure shows the block diagram of the PLL. Figure 18. PLL Architecture All three PLLs are designed for easiest configuration. The user just has to define the input and output frequencies or the divider (M, setting respectively. All other parameters, such as charge-pump current, filter components, phase margin, or loop bandwidth are controlled and set by the device itself. This assures optimized jitter attenuation and loop stability. The PLL support normal-speed mode (80 MHz f VCO 200 MHz) and high-speed mode (180 MHz f VCO 300 MHz) which can be selected by PLLxFVCO (Bit [7:5] of Byte 6). The respective speed option assures stable operation and lowest jitter. The divider M and divider N operates internally as fractional divider for f VCO up to 250 MHz. This allows fractional divider ratio for zero ppm output clock error. In case of f VCO 250 MHz, it is recommended that integer factors of N/M are used only. For optimized jitter performance, keep divider M as small as possible. Also, the fractional divider concept requires a PLL divider configuration, M N (or N/M 1). Submit Documentation Feedback

www.ti.com Spread Spectrum Clocking and EMI Reduction Down Spread 3% 9th Harmonic, fm = 60 kHz 11.3dB 7dB Center Spread/C00430.4% 9th Harmonic, fm = 60 kHz Down Spread 3% 9th Harmonic, fm = 60 11.3dB 11.3 dB 7dB 7 dB Center Spread/C00430.4% 9th Harmonic, fm = 60 CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Additionally, each PLL supports two bypass options: PLL Bypass and VCO Bypass In PLL bypass mode, the PLL completely is bypassed, so that the input clock is switched directly to the Output-Switch-A (SWAPxx of Byte to 12). In the VCO bypass mode, only the VCO of the respective PLL is bypassed by setting PLLxMUX to (Bit [7:5] of Byte 3). But the divider M still is useable and expands the output divider by additional 9-bits. This gives a total divider range of M x P 511 x 127 64897. In VCO bypass mode the respective PLL block is powered down and minimizes current consumption. Table Example for Divide, Multiplication, and Bypass Operation f IN f OUT-desired f OUT-actual Divider Function Equation (1) f VCO [MHz] [MHz] [MHz] [MHz] M N P N/M Fractional (2) f OUT f IN x (N/M)/P 30.72 155.52 155.52 5.0625 155.52 Integer Factor (3) f OUT f IN x (N/M)/P 270 270 270 VCO bypass f OUT f IN /(M x 30.72 0.06 0.06 (1) P-divider of Output-Switch-Matrix is included in the calculation. (2) Fractional operation for f VCO 250 MHz. (3) Integer operation for f VCO 250 MHz. In addition to the basic PLL function, PLL2 supports spread spectrum clocking (SSC) as well. Thus, PLL outputs, a SSC output and a non-SSC output. Both outputs can be used in parallel. The mean phase of the Center Spread SSC modulated signal is equal to the phase of the non-modulated input frequency. SSC is selected by Output-Switch-A (SWAPxx of Byte to 12). SSC also is bypass-able (Byte 25, Bit [6:4]), which powers-down the SSC output and set it to logic low state. The non-SSC output of PLL2 is not affected by this mode and can still be used. SSC is an effective method to reduce electro-magnetic interference (EMI) noise in high-speed applications. It reduces the RF energy peak of the clock signal by modulating the frequency and spread the energy of the signal to a broader frequency range. Because the energy of the clock signal remains constant, a varying frequency that broadens the overtones necessarily lowers their amplitudes. Figure shows the effect of SSC on a 54-MHz clock signal for DSP Figure 19. Spread Spectrum Clocking With Center Spread and Down Spread The peak amplitude of the modulated clock is 11.3 dB lower than the non-modulated carrier frequency for down spread and radiated less electro-magnetic energy. Submit Documentation Feedback

www.ti.com SSC Modulation Amount SSC Modulation Frequency 30 40 50 60 3% Down Spread 2% Down Spread fmodulation − kHz EMI Reduction− dB /C00430.4 Center Spread /C00430.25 Center Spread Further EMI Reduction CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 In SSC mode, the user can select the SSC modulation amount and SSC modulation frequency. The modulation amount is the frequency deviation based to the carrier (min/max frequency), whereas the modulation frequency determines the speed of the frequency variation. In SSC mode, the maximum VCO frequency is limited to 167 MHz. The CDC706 supports center spread modulation and down spread modulation. In center spread, the clock is symmetrically shifted around the carrier frequency and can be 0.1%, 0.25%, and 0.4%. At down spread, the clock frequency is always lower than the carrier frequency and can be 1%, 1.5%, 2%, and 3%. The down spread is preferred if a system can not tolerate an operating frequency higher than the nominal frequency (over-clocking problem). Example: Modulation Type Minimum Center Maximum Frequency Frequency Frequency A 0.25% center spread 53.865 MHz MHz 54.135 MHz B down spread 53.46 MHz MHz C 0.5% down spread (1) 53.73 MHz 53.865 MHz MHz (1) A down spread of 0.5% of a 54-MHz carrier is equivalent to 59.865 MHz at a center spread of 0.25%. The modulation frequency (sweep rate) can be selected between kHz and kHz. It is also based on the VCO frequency as shown in the SSC Modulation Frequency Selection As shown in Figure the damping increases with higher modulation frequencies. It may be limited by the tracking skew of a downstream PLL. The CDC706 uses a triangle modulation profile which is one of the common profiles for SSC. Figure 20. EMI Reduction vs f Modulation and f Amount The optimum damping is a combination of modulation amount, modulation frequency and the harmonics which are considered. Note that higher order harmonic frequencies results in stronger EMI reduction because of respective higher frequency deviation. As seen in Figure and Figure a slower output slew rate and/or smaller output signal amplitude helps to reduce EMI emission even more. Both measures reduce the RF energy of clock harmonics. The CDC706 allows slew rate control in four steps between 0.6 ns and 3.3 ns (Byte 19-24, Bit [5:4]). The output amplitude is set by the two independent output supply voltage pins, V CCOUT1 and V CCOUT2 and can vary from 2.3 V to 3.6 Even a lower output supply voltage down to 1.8 V works, but the maximum frequency has to be considered. Submit Documentation Feedback

www.ti.com 11.3dB 7dB11.3dB11.3dB 7dB7dB nom− 1 nom nom+2 − 3dB 6.4dB nom− 1 nom nom+2 − 2.5dB 5.6dB Slew-Rate for VCCOUT = 2.5 V Slew-Rate for VCCOUT = 3.3 V 3.6 V3 V2.5 V VCCOUT EMI Reduction − dB (Relative to Nom) Multi-Function Control Inputs and CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Figure 21. EMI Reduction vs Slew-Rate and V ccout Figure 22. EMI Reduction vs V ccout The CDC706 pins. When programmed as control pins, they can function as clock select pin, enable/disable pin or device power-down pin. If both pins used as address-bits, up to four devices can be connected to the same SMBus. The respective function is set in Byte 10; Bit [3:0]. Table shows the possible setting for the different output conditions, clock select and device addresses. Submit Documentation Feedback

www.ti.com Output Switching Matrix CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Table Configuration Setting of Control Inputs Configuration Bits External Control Pins Device Function Byte 10, Byte 10, Bit [3:2] Bit [1:0] Power S11 S10 S01 S00 Yx Outputs Pin Pin (Pin (Pin Down X X Active No Output ctrl Output ctrl X Low/High (1) No Output ctrl Output ctrl X 3-State Outputs only Output ctrl Output ctrl X X 3-State PLL, inputs and outputs Output ctrl Output ctrl and pd S10 =0: low/high (1) X PLL only Output ctrl PLL and Div bypass S10 =1: 3-State X Active PLL only Output ctrl PLL and Div bypass S10 =0: Low/High (1) X (2) No Output ctrl CLK_SEL S10 =1: 3-State X (2) Active No Output ctrl CLK_SEL (1) A non-inverting output will be set to low and an inverting output will be set to high. (2) If is CLK_IN0 is selected; if is CLK_IN1 is selected. As shown in Table there is a specific order of the different output condition: Power-down mode overwrites 3-state, 3-state overwrites low-state, and low-state overwrites active-state. The flexible architecture of the output switch matrix allows the user to switch any of the internal clock signal sources via a free-selectable post-divider to any of the six outputs. As shown in Figure the CDC706 is based on two banks of switches and six post-dividers. Switch A comprises six 5-Input-Muxes which selects one of the four PLL clock outputs or directly selects the input clock and feed it to one of the 7-bit post-divider (P-Divider). Switch B is made up of six 6-Input-Muxes which takes any post-divider and feeds it to one of the six outputs, Yx. Switch B was added to the output switch matrix to ensure that outputs frequencies derive from one P-divider are 100% phase aligned. Also, the P-divider is built in a way that every divide factor is automatically duty-cycle corrected. Changing the divider value on the fly may cause a glitch on the output. Submit Documentation Feedback

www.ti.com 5x6 − Switch A Input CLK (PLL Bypass) PLL 1 PLL 2 non SSC PLL 2 w/ SSC PLL 3 6x6 − Switch B7-Bit Divider Output Switch Matrix (1..127) (1..127) (1..127) (1..127) (1..127) Programming OutputsInternal Clock Sources PLL/Input_Clk Selection P-Divider Selection Output Selection: Active/Low/3-State/ Inverting/Non-Inverting P-Divider Setting (1..127) Slew Rate/VCCOUT LVCMOS Output Configuration Inverting Slew Rate Low Select Enable/Disable Clock div by 3 BufferSel M U X P−div(0) output P−div(1) output P−div(2) output P−div(3) output P−div(4) output P−div(5) output Yx Inversion Select Slew-Rate Control Low Select Enable/Disable P−Divider Select (Optional all outputs low or 3−State) V CCOUT1 /VCCOUT2 CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Figure 23. CDC706 Output Switch Matrix In addition, the outputs can be switched active, low or 3-state and/or 180 degree phase shifted. Also the outputs slew-rate and the output-voltage is user selectable. The output stage of the CDC706 supports all common output setting, such as enable, disable, low-state and signal inversion (180 degree phase shift). It further (0.6 ns to 3.3 ns) and variable output supply voltage (2.3 V to 3.6 V). Figure 24. Block Diagram of Output Architecture Figure 25. Example for Output Waveforms All output settings are programmable via SMBus: enable, disable, low-state via external control pins and Byte 10, Bit[3:0] enable or disable-to-low Byte to 24, Bit[3] inverting/non-inverting Byte to 24, Bit[6] slew-rate control Byte to 24, Bit[5:4] output swing external pins V CCOUT1 (Pin 14) and V CCOUT2 (Pin 18) Submit Documentation Feedback

www.ti.com Performance Data: Output Skew, Jitter, Cross Coupling, Noise Rejection (Spur-Suppression), Output Skew Jitter Performance CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 and Phase Noise Skew is an important parameter for clock distribution circuits. It is defined as the time difference between outputs that are driven by the same input clock. Table shows the output skew sk(o) of the CDC706 for high-to-low and low-to-high transitions over the entire range of supply voltages, operating temperature and output voltage swing. Table Output Skew PARAMETER V ccout TYP MAX UNIT 2.5 V 130 250 ps t sk(o) 3.3 V 130 200 ps Jitter is a major parameter for PLL-based clock driver circuits. This becomes important as speed increases and timing budget decreases. The PLL and internal circuits of CDC706 are designed for lowest jitter. The peak-to-peak period jitter is only ps (typical). Table gives the peak-to-peak and rms deviation of cycle-to-cycle jitter, period jitter and phase jitter as taken during characterization. Table Jitter Performance of CDC706 PARAMETER f out TYP (1) MAX (1) UNIT Peak-Peak rms Peak-Peak rms (one sigma) (one sigma) t jit(cc) MHz ps 133 MHz 245.76 MHz t jit(per) MHz ps 133 MHz 245.76 MHz t jit(phase) MHz 730 840 115 ps 133 MHz 930 130 1310 175 245.76 MHz 720 930 125 (1) All typical and maximum values are at V CC 3.3 temperature V ccout 3.3 one output is switching, data taken over several 10000 cycles. Figure Figure and Figure show the relationship between cycle-to-cycle jitter, period jitter, and phase jitter over 10000 samples. The jitter varies with a smaller or wider sample window. The cycle-to-cycle jitter and period jitter show the measured value whereas the phase jitter is the accumulated period jitter. Cycle-to-Cycle jitter jit(cc) is the variation in cycle time of a clock signal between adjacent cycles, over a random sample of adjacent cycle pairs. Cycle-to-cycle jitter will never be greater than the period jitter. It is also known as adjacent cycle jitter. Submit Documentation Feedback

www.ti.com −40 −30 −20 −10 1 1001 2001 3001 4001 5001 6001 7001 8001 9001 10001 Cycle tjit(cc) [ps] −25 −20 −15 −10 1 1001 2001 3001 4001 5001 6001 7001 8001 9001 10001 Cycle tjit(per) [ps] CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Figure 26. Snapshot of Cycle-to-Cycle Jitter Period jitter jit(per) is the deviation in cycle time of a clock signal with respect to the ideal period (1/fo) over a random sample of cycles. In reference to a PLL, period jitter is the worst-case period deviation from the ideal that would ever occur on the PLLs outputs. This is also referred to as short-term jitter. Figure 27. Snapshot of Period Jitter Submit Documentation Feedback

www.ti.com −300 −250 −200 −150 −100 −50 100 150 200 250 300 1 1001 2001 3001 4001 5001 6001 7001 8001 9001 10001 Cycle tjit(phase) [ps] CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Phase jitter jit(phase) is the long-term variation of the clock signal. It is the cumulative deviation in Θ for a controlled edge with respect to a Θ mean in a random sample of cycles. Phase jitter, Time Interval Error (TIE), or Wander are used in literature to describe long-term variation in frequency. As of ITU-T: G.810, wander is defined as phase variation at rates less than Hz while jitter is defined as phase variation greater than Hz. The measurement interval must be long enough to gain a meaningful result. Wander can be caused by temperature drift, aging, supply voltage drift, etc. Figure 28. Snapshot of Phase Jitter Jitter depends on the VCO frequency VCO of the PLL. A higher f VCO results in better jitter performance compared to a lower f VCO The VCO frequency can be defined via the and N-divider of the PLL As the CDC706 supports a pretty wide frequency range, the device offers a VCO Frequency Selection Bit, Bit [7:5] of Byte This bit defines the jitter-optimized frequency range of each PLL. The user can select between the normal-speed mode (80 MHz to 200 MHz) and the high-speed mode (180 MHz to 300 MHz). Figure shows the jitter performance over f VCO for the two frequency ranges. Submit Documentation Feedback

www.ti.com 100 120 140 160 180 200 220 240 260 280 300 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 T =□25 C, V =□3.3□V, A CC o M□div□=□4, N□div□=□15, P div□=□3 High-Speed Mode >180□MHz f Frequency□RangeVCO for□High-Speed□Mode f for□Normal-Speed□Mode VCO Frequency□Range Normal-Speed□Mode <□200□MHz fVCO − MHz□Set□Point tjit(per)p − ps Cross Coupling, Spur Suppression and Noise Rejection CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Figure 29. Period Jitter vs f VCO for Normal-Speed Mode and High-Speed Mode The TI Pro Clock software automatically calculates the PLL parameter for jitter-optimized performance. Cross-Coupling in ICs occurs through interactions between several parts of the chip such as between output stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive and resistive (ohmic) induced by output switching, leakage current, ground bouncing, power supply transients, etc. The CDC706 is designed in BiCMOS process technology incorporating silicon-germanium (SiGe) technology. This process gives excellent performance in linearity, low power consumption, best-in-class noise performance and very good isolation characteristic between the on-chip components. The good isolation was a major criteria to use BiCMOS process as it minimizes the coupling effect. Even if all three PLLs are active and all outputs are on, the noise suppression is clearly above dB. Figure and Figure show an example of noise coupling, spur-suppression, and power supply noise rejection of CDC706. Die respective measurement conditions are shown in Figure and Figure Submit Documentation Feedback

www.ti.com carrier 48MHz carrier 48MHz spurs at 47MHz&49MHz 56 dB carrier 48MHz spurs at 47MHz&49MHz 56 dB spur 47MHz and fundamental at 1MHz w Measured Y0: 48 MHz w Y1, Y2, Y3, Y4 & Y5 tri− stated w Inserted 30mV 1MHz @ Vcc = 3.3V Phase Noise Characteristic CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Figure 30. Noise Coupling and Spur Suppression Figure 31. Power Supply Noise Rejection In high-speed communication systems, the phase noise characteristic of the PLL frequency synthesizer is of high interest. Phase noise describes the stability of the clock signal in the frequency domain, similar to the jitter specification in the time domain. Phase noise is a result of random and discrete noise causing a broad slope and spurious peaks. The discrete spurious components could be caused by known clock frequencies in the signal source, power line interference, and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the result of thermal noise, shot noise and/or flicker noise in active and passive devices. Important factor for PLL synthesizer is the loop bandwidth dB cut-off frequency) large loop bandwidth (LBW) results in fast transient response but have less reference spur attenuation. The LBW of the CDC706 is about 100 kHz to 250 kHz, dependent on selected PLL parameter. For the CDC706, two phase noise characteristics are of interest: The phase noise of the crystal-input stage and the phase noise of the internal PLL (VCO). Figure shows the respective phase noise characteristic. Submit Documentation Feedback

www.ti.com dBc/Hz −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 CDC706□Cyrstal□27□MHz□Input 27□MHz□Buffered□Output CDC706□fOUT 135□MHz f 135□MHzVCO foffset -□[Hz] CDC706□fOUT 135□MHz f 270□MHzVCO Phase□Noise□Comparison f 135□MHz f 135□MHz□vs□270□MHz OUT VCO PLL Lock-Time CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Figure 32. Phase Noise Characteristic f offset Hz Some switching, i.e. to change frequency in TV application (switching between channels) or change the PCI-X frequency in computers. The time spent by the PLL in achieving the new frequency is of main interest. The lock time is the time it takes to jump from one specified frequency to another specified frequency within a given frequency tolerance (see Figure It should be low, because a long lock time impacts the data rate of the system. The PLL-Lock-Time depends on the device configuration and can be changed by the VCO frequency, i.e. by changing the M/N divider values. Table gives the typical lock times of the CDC706 and Figure shows a snapshot of a frequency switch. Table CDC706 PLL Lock-Times µ s Frequency change via CLK_SEL pin (switching between CLK_IN0 and CLK_IN1) 100 µ s Power-up lock time with system clock µ s Power-up lock time with MHz Crystal at CLK_IN0 and CLK_IN1 300 (1) µ s (1) Is the result of Crystal lock time (200 µ and PLL lock time (100 µ s). Submit Documentation Feedback

www.ti.com EVM□Board□Configuration: Measurement:

• Start□Condition: ƒ (M =□10,□N□=□30)□=□81□MHz Result:
• 60 /c109s□to□PLL Pull□In
• 90 /c109s□to□PLL Phase□Lock 20 /c109s/div 297 0 60 t□[ s]/c109 Start□Condition: Acknowledge□of N-Divider□Byte Frequency Response Curve□of Y0 fVCO (MHz)
• Y0□(PLL1), Y1□3□state
• measured□Channel: Y0 Power Supply Sequencing Device Behavior During Supply Voltage Drops V t Typ□3.3□V Typ□2.1□V Typ□1.7□V A B C D VCC VPUC_ON VPUC_OFF GND CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 Figure 33. Snapshot of the PLL Lock-Time The CDC706 includes three power supply pins, V CC V CCOUT1 and V CCOUT2 There are no power supply sequencing requirements, as the three power nodes are separated from each other. So, power can be supplied in any order to the three nodes. Also, the part has a power-up circuitry which switches the device on if V CC exceeds 2.1 V (typical) and switches the device off at V CC 1.7 V (typical). In power-down mode, all outputs and clock inputs are switched off. The CDC706 has a Power-Up-Circuit, which activates the device function at V PUC_ON (typical 2.1 V). At the same time, the ROM information is loaded into the register. This mechanism ensures that there is a pre-defined default after Power-Up and no need to reprogram the CDC706 in the application. In the event of a supply-voltage-drop, the Power-Up-Circuit assures that there is always a defined setup within the register. Figure shows possible voltage drops with different amplitudes. Figure 34. Different Voltage Drops on V CC During Operation Submit Documentation Feedback

www.ti.com EVM and Programming SW CDC706 SCAS829A SEPTEMBER 2006 REVISED MARCH 2007 The CDC706 Power-Up-Circuit has an inbuilt hysteresis. If the voltage stays above V PUC_OFF which is typically at 1.7 the register content stays unchanged. If the voltage drops below V PUC_OFF the internal register is reloaded by the ROM after V PUC_ON is crossed again. V PUC_ON is typically 2.1 Table show the content of the ROM and the Register after above voltage drops scenarios. Table ROM and Register Content After V CC Drop Power Drop ROM Content Register Content A Unchanged Unchanged B Unchanged Unchanged C Unchanged Reloaded from ROM D Unchanged Reloaded from ROM The CDC706 EVM is a development kit consisting of a performance evaluation module, the TI Pro Clock software, and the User's Guide. Contact Texas Instruments sales or marketing representative for more information. Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDC706PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC706PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC706PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC706PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 1

Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CDC706PWR PW 20 MLA 330 16 6.95 7.1 1.6 8 16 PKGORN T1TR-MS P TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) CDC706PWR PW 20 MLA 342.9 336.6 28.58 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

(TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for design. Customers are responsible for their products and components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony Low Power www.ti.com/lpw Video Imaging www.ti.com/video Wireless Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2007, Texas Instruments Incorporated