CDC5801ADBQ

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/C0067/C0068/C0067/C0053/C0056/C0048/C0049/C0065 /C0076/C0079/C0087 /C0074/C0073/C0084/C0084/C0069/C0082 /C0067/C0076/C0079/C0067/C0075 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0073/C0069/C0082 /C0065/C0078/C0068 /C0068/C0073/C0086/C0073/C0068/C0069/C0082 /C0087/C0073/C0084/C0072 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0068/C0069/C0076/C0065/C0089 /C0065/C0078/C0068 /C0080/C0072/C0065/C0083/C0069 /C0065/C0076/C0073/C0071/C0078/C0077/C0069/C0078/C0084 SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Jitter Clock Multiplier by x4, x6, x8. Input Frequency Range (19 MHz to 125 MHz). Supports Output Frequency From 150 MHz to 500 MHz /C0068Fail-Safe Power Up Initialization /C0068Low Jitter Clock Divider by /2, /3, /4. Input Frequency Range (50 MHz to 125 MHz). Supports Ranges of Output Frequency From 12.5 MHz to 62.5 MHz /C00682.6 mUI Programmable Bidirectional Delay Steps /C0068Typical 8-ps Phase Jitter (12 kHz to 20 MHz) at 500 MHz /C0068Typical 2.1-ps RMS Period Jitter (Entire Frequency Band) at 500 MHz /C0068One Single-Ended Input and One Differential Output Pair /C0068Output Can Drive LVPECL, LVDS, and LVTTL /C0068Three Power Operating Modes to Minimize Power /C0068Low Power Consumption (Typical 200 mW at 500 MHz) /C0068Packaged in a Shrink Small-Outline Package (DBQ) /C0068No External Components Required for PLL /C0068Spread Spectrum Clock Tracking Ability to Reduce EMI /C0068Applications: Video Graphics, Gaming Products, Datacom, Telecom /C0068Accepts LVCMOS, LVTTL Inputs for REFCLK Terminal /C0068Accepts Other Single-Ended Signal Levels at REFCLK Terminal by Programming Proper V DD REF Voltage Level (For Example, HSTL 1.5 if VDD REF = 1.6 V) /C0068Supports Industrial Temperature Range of −40 °C to 85°C

description

The CDC5801A device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz. See Table 1 and Table 2 for detail frequency support. The implemented phase aligner provides the possibility to phase align (zero delay) between CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG terminals. The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI (unit interval). For every rising edge on the DLYCTRL terminal, the output clocks are delayed by 2.6-mUI step size as long as there is low on the LEADLAG terminal. Similarly, for every rising edge on the DLYCTRL terminal, the output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the application may implement a self calibration routine at power up to produce a certain phase start position, before programming a fixed delay with the clock on the DLYCTRL terminal. Copyright  2005, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VDD REF REFCLK VDD P GNDP GND LEADLAG DLYCTRL GNDPA VDD PA VDD PD STOPB PWRDNB VDD O GNDO CLKOUT NC CLKOUTB GNDO V DD O MULT0/DIV0 MULT1/DIV1 DBQ PACKAGE (TOP VIEW) NC − No internal connection

/C0067/C0068/C0067/C0053/C0056/C0048/C0049/C0065 /C0076/C0079/C0087 /C0074/C0073/C0084/C0084/C0069/C0082 /C0067/C0076/C0079/C0067/C0075 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0073/C0069/C0082 /C0065/C0078/C0068 /C0068/C0073/C0086/C0073/C0068/C0069/C0082 /C0087/C0073/C0084/C0072 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0068/C0069/C0076/C0065/C0089 /C0065/C0078/C0068 /C0080/C0072/C0065/C0083/C0069 /C0065/C0076/C0073/C0071/C0078/C0077/C0069/C0078/C0084 SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Depending on the selection of the mode terminals (P0:2), the device behaves as a multiplier (by 4, 6, or 8) with the phase aligner bypassed or as a multiplier or divider with programmable delay and phase aligner functionality. Through the select terminals (P0:2) user can also bypass the phase aligner and the PLL (test mode) and output the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could be in a high impedance state. This device has another unique capability to be able to function with a wide band of voltages on the REFCLK terminal by varying the voltage on the V DD REF terminal. The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions. The CDC5801A device is characterized for operation over free-air temperatures of −40°C to 85°C. functional block diagram B A PLL Phase Aligner VDDPD/2 PLLCLK CLKOUT CLKOUTB REFCLK φD LEADLAG MULT0/DIV0 MULT1/DIV1 PWRDWNB P0 P1 P2 STOPB Control Logic Phase Aligner Bypass MUX DLYCTRL Divider Ratio VDDREF/2

/C0067/C0068/C0067/C0053/C0056/C0048/C0049/C0065 /C0076/C0079/C0087 /C0074/C0073/C0084/C0084/C0069/C0082 /C0067/C0076/C0079/C0067/C0075 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0073/C0069/C0082 /C0065/C0078/C0068 /C0068/C0073/C0086/C0073/C0068/C0069/C0082 /C0087/C0073/C0084/C0072 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0068/C0069/C0076/C0065/C0089 /C0065/C0078/C0068 /C0080/C0072/C0065/C0083/C0069 /C0065/C0076/C0073/C0071/C0078/C0077/C0069/C0078/C0084 SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE † MODE P0 P1 P2 CLKOUT/CLKOUTB Multiplication with programmable delay and phase alignment active‡ 0 0 0 REFCLK multiplied by ratio per Table 1 selected by MULT/DIV terminals. Outputs are delayed or advanced based on DLYCTRL and LEADLAG terminal configuration. Division with programmable delay and phase alignment active ‡ 0 0 1 REFCLK divided by ratio per Table 2 selected by MULT/DIV terminals. Outputs are delayed or advanced based on DLYCTRL and LEADLAG terminal configuration. Multiplication only mode (phase aligner bypassed) § 1 0 0 In this mode one can only multiply as per Table 1. Programmable delay capability and divider capability is deactivated. PLL is running. Test mode 1 1 0 PLL and phase aligner both bypassed. REFCLK is directly channeled to output. Hi-Z mode 0 1 X Hi-Z † X = don’t care, Hi-Z = high impedance ‡ Please see Table 4 and Table 5 for explanation for the programmability and phase alignment functions. § In this mode the DLYCTRL and LEADLAG terminals must be strapped high or low. Lowest possible jitter is achieved in this mode, but a delay of 200 ps to 2 ns expected typically from REFCLK to CLKOUT depending on the output frequency. Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION CLKOUT 20 O Output clock CLKOUTB 18 O Output clock (complement) DLYCTRL 7 I Every rising edge on this terminal delays/advances the CLKOUT/CLKOUTB signal by 1/384th of the CLKOUT/CLKOUTB period. (e.g., for a 90 degree delay or advancement one needs to provide 96 rising edges). See Table 4. GND 5 GND for VDD REF and VDD PD GNDO 17, 21 GND for clock output terminals (CLKOUT, CLKOUTB) GNDP 4 GND for PLL GNDPA 8 GND for phase aligner LEADLAG 6 I Decides if the output clock is delayed or advanced with respect to REFCLK. See Table 4. MULT0/DIV0 15 I PLL multiplier and divider select MULT1/DIV1 14 I PLL multiplier and divider select NC 19 Not used PWRDNB 12 I Active low power down state, CLKOUT/CLKOUTB goes low P0 24 I Mode control, see the Function Table P1 23 I Mode control, see the Function Table P2 13 I Mode control, see the Function Table REFCLK 2 I Reference input clock STOPB 11 I Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as per Table 3 VDD PA 9 I Supply voltage for phase aligner VDD PD 10 I Reference voltage for the DLYCTRL, LEADLAG terminals and STOPB function VDD REF 1 I Reference voltage for REFCLK VDD O 16, 22 I Supply voltage for the output terminals (CLKOUT, CLKOUTB) VDD P 3 I Supply voltage for PLL

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 1 and Table 2 list the supported REFCLK and BUSCLK (CLKOUT/CLKOUTB) frequencies. Table 1. Multiplication Ratios (P0:2 = 000 or 100) Table 2. Divider Ratio (P0:2 = 001) REFCLK, the PLL requires stabilization time to achieve phase lock. Table 3. Clock Output Driver States Table 4. Programmable Delay and Phase Alignment CLKOUT phase is not updated on every 32nd edge. Table 5. Clock Output Driver States frequency of the LEADLAG terminal.

/C0067/C0068/C0067/C0053/C0056/C0048/C0049/C0065 /C0076/C0079/C0087 /C0074/C0073/C0084/C0084/C0069/C0082 /C0067/C0076/C0079/C0067/C0075 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0073/C0069/C0082 /C0065/C0078/C0068 /C0068/C0073/C0086/C0073/C0068/C0069/C0082 /C0087/C0073/C0084/C0072 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0068/C0069/C0076/C0065/C0089 /C0065/C0078/C0068 /C0080/C0072/C0065/C0083/C0069 /C0065/C0076/C0073/C0071/C0078/C0077/C0069/C0078/C0084 SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C ‡ TA = 85°C POWER RATING DBQ 1400 mW 11 mW/°C 740 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD (VDD P, VDD PA, VDD O) 3 3.3 3.6 V High-level input voltage, VIH (CMOS) 0.7 × VDD V Low-level input voltage, VIL (CMOS) 0.3 × VDD V REFCLK low-level input voltage, VIL 0.3 × VDD REF V REFCLK high-level input voltage, VIH 0.7 × VDD REF V Input signal low voltage, VIL (STOPB, DLYCTRL, LEADLAG) 0.3 × VDD PD V Input signal high voltage, VIH (STOPB, DLYCTRL, LEADLAG) 0.7 × VDD PD V Input reference voltage for (REFCLK) (VDD REF) 1.235 VDD V Input reference voltage for (DLYCTRL and LEADLAG) (VDD PD) 1.235 VDD V High-level output current, IOH −16 mA Low-level output current, IOL 16 mA Operating free-air temperature, TA −40 85 °C timing requirements MIN MAX UNIT Input frequency of modulation, fmod (if driven by SSC CLKIN) 33 kHz Modulation index (nonlinear maximum 0.5%) 0.6% Input slew rate, SR 1 4 V/ns Input duty cycle on REFCLK 40% 60% Input frequency on REFCLK 19 125 MHz Allowable frequency on DLYCTRL 200 MHz Allowable frequency on LEADLAG 400 MHz Allowable duty cycle on DLYCTRL and LEADLAG 25% 75%

/C0067/C0068/C0067/C0053/C0056/C0048/C0049/C0065 /C0076/C0079/C0087 /C0074/C0073/C0084/C0084/C0069/C0082 /C0067/C0076/C0079/C0067/C0075 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0073/C0069/C0082 /C0065/C0078/C0068 /C0068/C0073/C0086/C0073/C0068/C0069/C0082 /C0087/C0073/C0084/C0072 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0068/C0069/C0076/C0065/C0089 /C0065/C0078/C0068 /C0080/C0072/C0065/C0083/C0069 /C0065/C0076/C0073/C0071/C0078/C0077/C0069/C0078/C0084 SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † MIN TYP ‡ MAX UNIT VO(STOP) Output voltage during CLK stop mode See Figure 1 1.1 2 V VOX Output crossing-point voltage See Figure 1 and Figure 4 0.5VDD O−0.2 0.5VDD O+0.2 V VO Output voltage swing (VOH − VOL ) See Figure 1 1.7 2.9 V VIK Input clamp voltage VDD = 3 V, II = −18 mA −1.2 V VOH High-level output voltage See Figure 1, VDD = 3 to 3.6 V 2.0 2.6 VVOH High-level output voltage VDD = 3 V, IOH = −16 mA 2.2 V VOL Low-level output voltage See Figure 1, VDD = 3 to 3.6 V 0.3 0.6 VVOL Low-level output voltage VDD = 3 V, IOL = 16 mA 0.5 V VDD = 3.135 V, VO = 1 V −32 −52 IOH High-level output current VDD = 3.3 V, VO = 1.65 V −51 mAIOH High-level output current VDD = 3.465 V, VO = 3.135 V −14.5 −21 mA VDD = 3.135 V, VO = 1.95 V 43 61.5 IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 65 mAIOL Low-level output current VDD = 3.465 V, VO = 0.4 V 25.5 36 mA IOZ High-impedance-state output current P0 = 0, P1 = 1 ±10 µA IOZ(STOP) High-impedance-state output current during CLK stop Stop = 0, VO = GND or VDD ±100 µA IOZ(PD) High-impedance-state output current in power-down state PWRDNB = 0, VO = GND or VDD −10 100 µA High-level input REFCLK, STOPB VDD = 3.6 V, VI = VDD 10 IIH High-level input current PWRDNB, P0:2, MULT/ DIV0:1 VDD = 3.6 V, VI = VDD 10 µA Low-level input REFCLK, STOPB VDD = 3.6 V, VI = 0 −10 IIL Low-level input current PWRDNB, P0:2, MULT/ DIV0:1 VDD = 3.6 V, VI = 0 −10 µA ZO Output impedance High state R I at IO −14.5 mA to −16.5 mA 15 35 50 ΩZO Output impedance (single ended) Low state R I at IO 14.5 mA to 16.5 mA 11 17 35 Ω Reference current VDD REF, VDD = 3.6 V PWRDNB = 0 50 µA Reference current VDD REF, VDD PD VDD = 3.6 V PWRDNB = 1 0.5 mA C I Input capacitance VI = VDD or GND 2 pF C O Output capacitance VO = VDD or GND 3 pF IDD(PD) Supply current in power-down stateREFCLK = 0 MHz to 100 MHz, PWDNB = 0, STOPB = 1 150 µA IDD(CLKSTOP) Supply current in CLK stop stateBUSCLK configured for 500 MHz 40 mA IDD(NORMAL) Supply current in normal state BUSCLK = 500 MHz P0:2 = 000; load see Figure 1 70 mA † VDD refers to any of the following; VDD PA, VDD PD, VDD REF, VDD O, and VDD P ‡ All typical values are at VDD = 3.3 V, TA = 25°C.

/C0067/C0068/C0067/C0053/C0056/C0048/C0049/C0065 /C0076/C0079/C0087 /C0074/C0073/C0084/C0084/C0069/C0082 /C0067/C0076/C0079/C0067/C0075 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0073/C0069/C0082 /C0065/C0078/C0068 /C0068/C0073/C0086/C0073/C0068/C0069/C0082 /C0087/C0073/C0084/C0072 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0068/C0069/C0076/C0065/C0089 /C0065/C0078/C0068 /C0080/C0072/C0065/C0083/C0069 /C0065/C0076/C0073/C0071/C0078/C0077/C0069/C0078/C0084 SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 jitter specification over recommended operating free-air temperature range and VCC (unless otherwise noted) PARAMETER CLKOUT TEST CONDITIONS MIN TYP † MAX UNIT

155 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) ps

200 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Phase jitter (accumulated, 50 kHz to 80 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) 5.5 ps t(jitter) (Multiplication only mode. Phase alignment and programmable delay features are not selected (PA bypass). See Figure 2.)

312 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Phase jitter (accumulated, 50 kHz to 80 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) ps

400 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Phase jitter (accumulated, 50 kHz to 80 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) 2.3 ps

500 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Phase jitter (accumulated, 50 kHz to 80 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) 2.1 ps Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) ps t(jitter) (Multiplication with phase alignment and Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Phase jitter (accumulated, 50 kHz to 80 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) ps (jitter) (Multiplication with phase alignment and programmable delay features selected. See Figure 2.) Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Phase jitter (accumulated, 50 kHz to 80 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) ps Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Phase jitter (accumulated, 50 kHz to 80 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) 3.1 ps † All typical values are at VDD = 3.3 V, TA = 25°C.

/C0067/C0068/C0067/C0053/C0056/C0048/C0049/C0065 /C0076/C0079/C0087 /C0074/C0073/C0084/C0084/C0069/C0082 /C0067/C0076/C0079/C0067/C0075 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0073/C0069/C0082 /C0065/C0078/C0068 /C0068/C0073/C0086/C0073/C0068/C0069/C0082 /C0087/C0073/C0084/C0072 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0068/C0069/C0076/C0065/C0089 /C0065/C0078/C0068 /C0080/C0072/C0065/C0083/C0069 /C0065/C0076/C0073/C0071/C0078/C0077/C0069/C0078/C0084 SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

jitter specification over recommended operating free-air temperature range and VCC (unless otherwise noted) (continued) PARAMETER CLKOUT TEST CONDITIONS MIN TYP † MAX UNIT t(jitter) (Multiplication with phase alignment and programmable delay features selected. See Figure 2.) Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Phase jitter (accumulated, 50 kHz to 80 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) 2.9 ps MULT0:1 = 11 (Divider

12.5 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Cycle-to-cycle (+) Cycle-to-cycle (−) ps (Divider ratio = 4)

15.5 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Cycle-to-cycle (+) Cycle-to-cycle (−) ps t(jitter) (Divider mode with MULT0:1 = 10 (Divider

25 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Cycle-to-cycle (+) Cycle-to-cycle (−) 7.5 ps (jitter) (Divider mode with phase aligner not active: DLYCTRL =LEADLAG = 0 or 1. See Figure 2.) (Divider ratio = 3)

31 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Cycle-to-cycle (+) Cycle-to-cycle (−) 5.5 ps MULT0:1 = 00 (Divider

50 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) ps (Divider ratio = 2)

62.5 MHz

Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) 5.5 ps MULT0:1 = 11 (Divider Period RMS (1Σ jitter, full frequency band) Period p-p Cycle-to-cycle (+) Cycle-to-cycle (−) 12.5 ps t(jitter) (Divider mode with phase alignment and (Divider ratio = 4) Period RMS (1Σ jitter, full frequency band) Period p-p Cycle-to-cycle (+) Cycle-to-cycle (−) 8.5 ps phase alignment and programmable delay features selected. See Figure 2.) MULT0:1 = 10 (Divider Period RMS (1Σ jitter, full frequency band) Period p-p Cycle-to-cycle (+) Cycle-to-cycle (−) ps (Divider ratio = 3) Period RMS (1Σ jitter, full frequency band) Period p-p Cycle-to-cycle (+) Cycle-to-cycle (−) ps

/C0067/C0068/C0067/C0053/C0056/C0048/C0049/C0065 /C0076/C0079/C0087 /C0074/C0073/C0084/C0084/C0069/C0082 /C0067/C0076/C0079/C0067/C0075 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0073/C0069/C0082 /C0065/C0078/C0068 /C0068/C0073/C0086/C0073/C0068/C0069/C0082 /C0087/C0073/C0084/C0072 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0068/C0069/C0076/C0065/C0089 /C0065/C0078/C0068 /C0080/C0072/C0065/C0083/C0069 /C0065/C0076/C0073/C0071/C0078/C0077/C0069/C0078/C0084 SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 jitter specification over recommended operating free-air temperature range and VCC (unless otherwise noted) (continued) PARAMETER CLKOUT TEST CONDITIONS MIN TYP † MAX UNIT t(jitter) (Divider mode with phase alignment and MULT0:1 = 00 (Divider Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) ps phase alignment and programmable delay features selected. See Figure 2.) (Divider ratio = 2) Period RMS (1Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) 6.5 ps † All typical values are at VDD = 3.3 V, TA = 25°C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT t(DC) Output duty cycle See Figure 3 45% 55% tr, tf Output rise and fall times (measured at 20%−80% of output voltage) See Figure 5 and Figure 1 150 350 ps † All typical values are at VDD = 3.3 V, TA = 25°C.

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

† All typical values are at VDD = 3.3 V, TA = 25°C. Figure 1. Test Load and Voltage Definitions (VO(STOP) , VOX , VOH , VOL )

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 7. MULT Transition Timings Figure 8. STOPB Transition Timings

19.44 MHz

155.52 MHz

Figure 9. Using the CDC5801A Device as a Multiplier by 8 and Aligning Two Different Clocks

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC5801ADBQR SSOP DBQ 24 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 2

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