CDC516 TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 11
Technical content
3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS575A – JULY 1996 – REVISED JANUARY 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications /C0068Distributes One Clock Input to Four Banks of Four Outputs /C0068Separate Output Enable for Each Output Bank /C0068External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input /C0068No External RC Network Required /C0068Operates at 3.3-V VCC /C0068Packaged in Plastic 48-Pin Thin Shrink Small-Outline Package
description
The CDC516 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC516 operates at 3.3-V V CC and is designed to drive up to five clock loads per output. Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC516 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC516 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL may be bypassed for test purposes by strapping AV CC to ground. The CDC516 is characterized for operation from 0°C to 70°C. Copyright 1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VCC 1Y0 1Y1 GND GND 1Y2 1Y3 V CC GND AV CC CLK AGND AGND GND V CC 2Y0 2Y1 GND GND 2Y2 2Y3 V CC VCC 4Y0 4Y1 GND GND 4Y2 4Y3 V CC GND AV CC FBIN AGND FBOUT GND V CC 3Y0 3Y1 GND GND 3Y2 3Y3 V CC DGG PACKAGE (TOP VIEW)
3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS575A – JULY 1996 – REVISED JANUARY 1998
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(0:3) (0:3) (0:3) (0:3) FBOUT X X X X L L L L L L L LLLHL LLL H L LLH HL LLH H L LHLHL LHL H L LHHHL LHH H L HLLHL HLL H L HLHHL HLH H L HHLHL HHL H L HHHHL HHH H H LLLH H LLL H H LLH H H LLH H H LHLHH LHL H H LHHHH LHH H H HLLHH HLL H H HLHHH HLH H H HHLHH HHL H H H H H H H H H H H AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (PW) 0°C to 70°C CDC516DGGR
3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS575A – JULY 1996 – REVISED JANUARY 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram 3Y2 3Y1 3Y0 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁ PLL FBIN AV CC CLK 4Y2 4Y1 4Y0 4Y3 FBOUT 3Y3 2Y2 2Y1 2Y0 2Y3 1Y2 1Y1 1Y0 1Y3
3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS575A – JULY 1996 – REVISED JANUARY 1998
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NAME NO. TYPE DESCRIPTION CLK 12 I Clock input. CLK provides the clock signal to be distributed by the CDC516 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 37 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. 1G 9 I Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same frequency as CLK. 2G 16 I Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. 3G 33 I Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same frequency as CLK. 4G 40 I Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same frequency as CLK. FBOUT 35 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. 1Y(0:3) 2, 3, 6, 7 O Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G. These outputs can be disabled to a logic-low state by deasserting the 1G control input. 2Y(0:3) 18, 19, 22, 26 O Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G. These outputs can be disabled to a logic-low state by deasserting the 2G control input. 3Y(0:3) 31, 30, 27, 26 O Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G. These outputs can be disabled to a logic-low state by deasserting the 3G control input. 4Y(0:3) 47, 46, 43, 42 O Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G. These outputs can be disabled to a logic-low state by deasserting the 4G control input. AV CC 11, 38 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, the PLL is bypassed and CLK is buffered directly to the device outputs. AGND 13, 14, 36 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC 1, 8, 17, 24, 25, 32, 41, 48Power Power supply GND 4, 5, 10, 15, 20, 21, 28, 29, 34, 39, 44, 45 Ground Ground
3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS575A – JULY 1996 – REVISED JANUARY 1998 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range applied to any output in the high or low state, V † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V IOH High-level output current –20 mA IOL Low-level output current 20 mA TA Operating free-air temperature 0 70 °C NOTE 4: Unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP ‡ MAX UNIT VIK II = –18 mA 3 V –1.2 V VOH IOH = –100 mA MIN to MAX VCC –0.2 VVOH IOH = –20 mA 3 V 2.4 V VOL IOL = 100 mA MIN to MAX 0.2 VVOL IOL = 20 mA 3 V 0.55 V II VI = VCC or GND 3.6 V ±5 mA ICC § VI = VCC or GND IO = 0, Outputs: low or high 3.6 V 20 mA DICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V 500 mA C i VI = VCC or GND 3.3 V 4 pF C o VO = VCC or GND 3.3 V 6 pF ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § For ICC of AVCC , see Figure 5. For dynamic digital ICC , see Figure 6.
3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS575A – JULY 1996 – REVISED JANUARY 1998
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT fclock Clock frequency 25 125 MHz Input clock duty cycle 40% 60% Stabilization time† 1 ms † Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Note 5 and Figures 1 and 2)‡ PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.165 V VCC = 3.3 V ± 0.3 V UNIT(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX tphase error reference (see Figure 3) 66 MHz < CLKIN↑ < 100 MHz FBIN↑ –80...400 ps tphase error, – jitter, (see Note 6) CLKIN ↑ = 100 MHz FBIN↑ 170 360 240 ps tsk(o)§ Any Y or FBOUT Any Y or FBOUT 200 ps Jitter(pk-pk) F(clkin > 66 MHz) Any Y or FBOUT –100 100 ps Duty cycle F(clkin ≤ 66 MHz) Any Y or FBOUT 45% 55% D uty cycle F(clkin > 66 MHz) Any Y or FBOUT 43% 57% tr Any Y or FBOUT 1.1 1.5 0.7 1.6 ns tf Any Y or FBOUT 0.8 1.3 0.5 1.5 ns ‡ These parameters are not production tested. § The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 6. Phase error does not include jitter. The total phase error is 70 ps to 460 ps for the 5% VCC range.
2 VOutput500 /C0087 50% V CC30 pF
NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 W , tr ≤ 1.2 ns, tf≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 2. Phase Error and Skew Calculations
3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS575A – JULY 1996 – REVISED JANUARY 1998
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/D 08/96
48 PIN SHOWN
14,10 13,90 0,25 48DIM A MAX A MIN PINS ** 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 12,40 12,60 0,75 0,50 Seating Plane 0,27 0,17 A 0,05 MIN1,20 MAX 17,10 16,90 M0,08 0,10 0,50 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-153
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated