CDC421A156RGER

CDC421AXXX TI | Alldatasheet

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Divider PFD/Charge□Pump Loop□Filter VCO Prescaler Output□Divider LVPECL External Crystal CLK NCLK CDC421AXXX www.ti.com SCAS875 MAY 2009 Fully-Integrated, Fixed-Frequency, Low-Jitter Crystal Oscillator Clock Generator Low-Cost, Low-Jitter Frequency Multiplier Single 3.3-V Supply High-Performance Clock Generator, Incorporating Crystal Oscillator Circuitry with Integrated Frequency Synthesizer The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated Low Output Jitter: As low as 380 fs (RMS low-noise, LC-based voltage-controlled oscillator integrated between kHz to MHz) (VCO) that operates within the 1.75 GHz to 2.35 GHz Low Phase Noise at 312.5 MHz: frequency range. It has an integrated crystal oscillator Less than 120 dBc/Hz at kHz and that operates in conjunction with an external AT-cut 147 dBc/Hz at 10-MHz offset from carrier crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency Supports Crystal or LVCMOS Input synthesizer. The output frequency OUT is Frequencies at 31.25 MHz, 33.33 MHz, and proportional to the frequency of the input crystal 35.42 MHz XTAL Output Frequencies: 100 MHz, 106.25 MHz, The device operates in 3.3-V supply environment and 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and is characterized for operation from C to +85 312.5 MHz The CDC421Axxx is available in a QFN-24 4-mm Differential Low-Voltage Positive Emitter 4-mm package. Coupled Logic (LVPECL) Outputs The CDC421Axxx differs from the CDC421xxx in Fully-Integrated Voltage-Controlled Oscillator the following ways: (VCO): Runs from 1.75 GHz to 2.35 GHz Device Startup Typical Power Consumption: 300 mW The CDC421Axxx has an improved startup circuit Chip Enable Control Pin to enable correct operation for all power-supply ramp times. Available in 4-mm 4-mm QFN-24 Package ESD Protection Exceeds kV (HBM) Industrial Temperature Range: C to +85 C CDC421Axxx Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1) RECOMMENDED OPERATING CONDITIONS CDC421AXXX SCAS875 MAY 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) INPUT OUTPUT FREQUENCY OR FREQUENCY FOR CRYSTAL SPECIFIED INPUT PACKAGE- PACKAGE ORDERING TRANSPORT MEDIA, PRODUCT VALUE (MHz) FREQUENCY (MHz) LEAD MARKING INFORMATION QUANTITY CDC421A100RGET Tape and reel, 250 CDC421A100 33.3333 100.00 QFN-24 421A100 CDC421A100RGER Tape and reel, 2500 CDC421A106RGET Tape and reel, 250 CDC421A106 35.4167 106.25 QFN-24 421A106 CDC421A106RGER Tape and reel, 2500 CDC421A125RGET Tape and reel, 250 CDC421A125 31.2500 125.00 QFN-24 421A125 CDC421A125RGER Tape and reel, 2500 CDC421A156RGET Tape and reel, 250 CDC421A156 31.2500 156.25 QFN-24 421A156 CDC421A156RGER Tape and reel, 2500 CDC421A212RGET Tape and reel, 250 CDC421A212 35.4167 212.50 QFN-24 421A212 CDC421A212RGER Tape and reel, 2500 CDC421A250RGET Tape and reel, 250 CDC421A250 31.2500 250.00 QFN-24 421A250 CDC421A250RGER Tape and reel, 2500 CDC421A312RGET Tape and reel, 250 CDC421A312 31.2500 312.50 QFN-24 421A312 CDC421A312RGER Tape and reel, 2500 (1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or refer to our web site at www.ti.com Over operating free-air temperature range (unless otherwise noted). PARAMETER CDC421Axxx UNIT V CC Supply voltage (2) 0.5 to 4.6 V V I Voltage range for all other input pins (2) 0.5 to V CC to +0.5 V I O Output current for LVPECL mA ESD Electrostatic discharge (HBM) kV T A Specified free-air temperature range (no airflow) to +85 C T J Maximum junction temperature +125 C T STG Storage temperature range to +150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. Over operating free-air temperature range (unless otherwise noted). MIN NOM MAX UNIT V CC Supply voltage 3.0 3.30 3.60 V T A Ambient temperature (no airflow, no heatsink) +85 C Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

Charge□Pump Prescaler Loop□FilterXIN□1 XIN□2 VCO Crystal Oscillator CDC421AXXX www.ti.com SCAS875 MAY 2009 Over recommended operating conditions (unless otherwise noted). CDC421Axxx PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V CC Supply voltage 3.00 3.30 3.60 V I VCC Total current 110 mA LVPECL OUTPUT f CLK Output frequency 100 312.5 MHz V OH LVPECL high-level output voltage V CC 1.20 V CC 0.81 V V OL LVPECL low-level output voltage V CC 2.17 V CC 1.36 V OD LVPECL differential output voltage 407 1076 mV t R Output rise time 20% to 80% of V OUT(PP) 230 ps t F Output fall time 20% to 80% of V OUT(PP) 230 ps Duty cycle of the output waveform t j RMS jitter kHz to MHz ps, RMS LVCMOS INPUT V IL, CMOS Low-level CMOS input voltage V CC 3.3 V 0.3 V CC V V IH, CMOS High-level CMOS input voltage V CC 3.3 V 0.7 V CC V I CMOS Low-level CMOS input current V CC V CC, max V IL 0.0 V 200 µ A I CMOS High-level CMOS input current V CC V CC, min V IH 3.7 V 200 µ A Figure CDC421Axxx: High-Level Block Diagram Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback

V CC VCC NC NC NC Thermal□Pad (Bottom□Side) CDC421AXXX NC OUTN NC GND XIN2 GND XIN1 OUTP NC NC NC NC CDC421AXXX SCAS875 MAY 2009 www.ti.com RGE PACKAGE QFN-24 (TOP VIEW) CDC421Axxx Pin Descriptions TERMINAL ESD NAME NO. TYPE PROTECTION V CC 16, Power Y 3.3-V power supply GND Ground Y Ground XIN1 I Y In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the other end of the crystal. In LVCMOS single-ended driven mode, XIN1 (pin 21) acts as input reference XIN2 I N and XIN2 should connect to GND. Chip enable (LVCMOS input) CE I Y CE enables the device and the outputs. CE disables all current sources (LVPECLP LVPECLN Hi-Z). High-speed positive differential LVPECL output. (Outputs are enabled by CE OUTP O Y pin.) High-speed negative differential LVPECL output. (Outputs are enabled by CE OUTN O Y pin.) 15, TI test pin. Do not connect; leave floating. NC Y 20, 23, Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

Phase□Noise Analyzer 150 /c87 XIN□1 XIN□2 50 /c87 150 /c87 100□pF 0.1□pF 50 /c87 CDC421AXXX www.ti.com SCAS875 MAY 2009 Jitter characterization tests are performed using an LVCMOS input signal driving the CDC421Axxx device, as Figure illustrates. Figure Jitter Test Configuration for an LVTTL Input Driving CDC421Axxx When the CDC421Axxx is referenced by an external, clean LVCMOS input of 31.25 MHz, 33.33 MHz, and 35.4167 MHz, Table to Table list the measured SSB phase noise of all the outputs supported by the CDC421Axxx device (100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and 312.5 MHz) from 100 Hz to MHz from the carrier. Table Phase Noise Data with LVCMOS Input of 33.3333 MHz and LVPECL Output at 100.00 MHz (1) PARAMETER MIN TYP MAX UNIT phn 100 Phase noise at 100 Hz 111 dBc/Hz phn Phase noise at kHz 121 dBc/Hz phn 10k Phase noise at kHz 131 dBc/Hz phn 100k Phase noise at 100 kHz 133 dBc/Hz phn Phase noise at MHz 142 dBc/Hz phn 10M Phase noise at MHz 149 dBc/Hz phn 20M Phase noise at MHz 149 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 507 fs T j Total jitter 35.33 ps D j Deterministic jitter 11.54 ps (1) Phase noise specifications under following conditions: input frequency 33.3333 MHz, output frequency 100.00 MHz. Table Phase Noise Data with LVCMOS Input of 35.4167 MHz and LVPECL Output at 106.25 MHz (1) PARAMETER MIN TYP MAX UNIT phn 100 Phase noise at 100 Hz 112 dBc/Hz phn Phase noise at kHz 121 dBc/Hz phn 10k Phase noise at kHz 125 dBc/Hz phn 100k Phase noise at 100 kHz 129 dBc/Hz phn Phase noise at MHz 142 dBc/Hz phn 10M Phase noise at MHz 151 dBc/Hz phn 20M Phase noise at MHz 151 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 530 fs T j Total jitter 30.39 ps D j Deterministic jitter ps (1) Phase noise specifications under following conditions: input frequency 35.4167 MHz, output frequency 106.25 MHz. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback

www.ti.com Table Phase Noise Data with LVCMOS Input of 31.2500 MHz and LVPECL Output at 125.00 MHz (1) PARAMETER MIN TYP MAX UNIT phn 100 Phase noise at 100 Hz 108 dBc/Hz phn Phase noise at kHz 118 dBc/Hz phn 10k Phase noise at kHz 127 dBc/Hz phn 100k Phase noise at 100 kHz 130 dBc/Hz phn Phase noise at MHz 139 dBc/Hz phn 10M Phase noise at MHz 147 dBc/Hz phn 20M Phase noise at MHz 147 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 529 fs T j Total jitter 47.47 ps D j Deterministic jitter 25.2 ps (1) Phase noise specifications under following conditions: input frequency 31.2500 MHz, output frequency 125.00 MHz. Table Phase Noise Data with LVCMOS Input of 31.2500 MHz and LVPECL Output at 156.25 MHz (1) PARAMETER MIN TYP MAX UNIT phn 100 Phase noise at 100 Hz 106 dBc/Hz phn Phase noise at kHz 117 dBc/Hz phn 10k Phase noise at kHz 126 dBc/Hz phn 100k Phase noise at 100 kHz 128 dBc/Hz phn Phase noise at MHz 139 dBc/Hz phn 10M Phase noise at MHz 147 dBc/Hz phn 20M Phase noise at MHz 147 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 472 fs T j Total jitter 31.54 ps D j Deterministic jitter 9.12 ps (1) Phase noise specifications under following conditions: input frequency 31.2500 MHz, output frequency 156.25 MHz. Table Phase Noise Data with LVCMOS Input of 35.4167 MHz and LVPECL Output at 212.50 MHz (1) PARAMETER MIN TYP MAX UNIT phn 100 Phase noise at 100 Hz 105 dBc/Hz phn Phase noise at kHz 115 dBc/Hz phn 10k Phase noise at kHz 119 dBc/Hz phn 100k Phase noise at 100 kHz 123 dBc/Hz phn Phase noise at MHz 135 dBc/Hz phn 10M Phase noise at MHz 148 dBc/Hz phn 20M Phase noise at MHz 148 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 512 fs T j Total jitter 33.96 ps D j Deterministic jitter 13.78 ps (1) Phase noise specifications under following conditions: input frequency 35.4167 MHz, output frequency 212.50 MHz. Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

www.ti.com SCAS875 MAY 2009 Table Phase Noise Data with LVCMOS Input of 31.2500 MHz and LVPECL Output at 250.00 MHz (1) PARAMETER MIN TYP MAX UNIT phn 100 Phase noise at 100 Hz 105 dBc/Hz phn Phase noise at kHz 112 dBc/Hz phn 10k Phase noise at kHz 121 dBc/Hz phn 100k Phase noise at 100 kHz 124 dBc/Hz phn Phase noise at MHz 134 dBc/Hz phn 10M Phase noise at MHz 148 dBc/Hz phn 20M Phase noise at MHz 149 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 420 fs T j Total jitter 36.98 ps D j Deterministic jitter 18.52 ps (1) Phase noise specifications under following conditions: input frequency 31.2500 MHz, output frequency 250.00 MHz. Table Phase Noise Data with LVCMOS Input of 31.2500 MHz and LVPECL Output at 312.50 MHz (1) PARAMETER MIN TYP MAX UNIT phn 100 Phase noise at 100 Hz 102 dBc/Hz phn Phase noise at kHz 111 dBc/Hz phn 10k Phase noise at kHz 120 dBc/Hz phn 100k Phase noise at 100 kHz 123 dBc/Hz phn Phase noise at MHz 135 dBc/Hz phn 10M Phase noise at MHz 147 dBc/Hz phn 20M Phase noise at MHz 147 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 378 fs T j Total jitter 29.82 ps D j Deterministic jitter ps (1) Phase noise specifications under following conditions: input frequency 31.2500 MHz, output frequency 312.50 MHz. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDC421A100RGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 100 CDC421A100RGER.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 100 CDC421A100RGET Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 100 CDC421A100RGET.B Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 100 CDC421A106RGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 106 CDC421A106RGER.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 106 CDC421A106RGET Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 106 CDC421A106RGET.B Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 106 CDC421A125RGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 125 CDC421A125RGER.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 125 CDC421A125RGET Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 125 CDC421A125RGET.B Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 125 CDC421A125RGETG4 Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 125 CDC421A125RGETG4.B Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 125 CDC421A156RGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 156 CDC421A156RGER.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 156 Addendum-Page 1

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDC421A156RGET Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 156 CDC421A156RGET.B Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 156 CDC421A212RGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 212 CDC421A212RGER.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 212 CDC421A212RGET Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 212 CDC421A212RGET.B Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 212 CDC421A250RGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 250 CDC421A250RGER.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 250 CDC421A250RGET Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 250 CDC421A250RGET.B Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 250 CDC421A312RGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 312 CDC421A312RGER.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 312 CDC421A312RGET Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 312 CDC421A312RGET.B Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 421A 312 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. Addendum-Page 2

www.ti.com 7-Oct-2025 (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC421A100RGER VQFN RGE 24 3000 353.0 353.0 32.0 CDC421A100RGET VQFN RGE 24 250 213.0 191.0 35.0 CDC421A106RGER VQFN RGE 24 3000 353.0 353.0 32.0 CDC421A106RGET VQFN RGE 24 250 213.0 191.0 35.0 CDC421A125RGER VQFN RGE 24 3000 353.0 353.0 32.0 CDC421A125RGET VQFN RGE 24 250 213.0 191.0 35.0 CDC421A125RGETG4 VQFN RGE 24 250 213.0 191.0 35.0 CDC421A156RGER VQFN RGE 24 3000 353.0 353.0 32.0 CDC421A156RGET VQFN RGE 24 250 213.0 191.0 35.0 CDC421A212RGER VQFN RGE 24 3000 353.0 353.0 32.0 CDC421A212RGET VQFN RGE 24 250 213.0 191.0 35.0 CDC421A250RGER VQFN RGE 24 3000 353.0 353.0 32.0 CDC421A250RGET VQFN RGE 24 250 213.0 191.0 35.0 CDC421A312RGER VQFN RGE 24 3000 353.0 353.0 32.0 CDC421A312RGET VQFN RGE 24 250 213.0 191.0 35.0 Pack Materials-Page 2

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4204104/H

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 24X 0.3 0.2 2.45 0.1 24X 0.5 0.3

1 MAX

(0.2) TYP 0.05 0.00 20X 0.5 2.5 2X 2.5 A 4.1 3.9 B 4.1 3.9 0.3 0.2 0.5 0.3 VQFN - 1 mm max heightRGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 PIN 1 INDEX AREA 0.08 C SEATING PLANE 6 13 7 12 24 19 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 EXPOSED THERMAL PAD

25 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

24X (0.25) 24X (0.6) ( 0.2) TYP VIA 20X (0.5) (3.8) (3.8) ( 2.45) (R0.05) TYP (0.975) TYP VQFN - 1 mm max heightRGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 SYMM 7 12 1924 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 24X (0.6) 24X (0.25) 20X (0.5) (3.8) (3.8) 4X ( 1.08) (0.64) TYP (0.64) TYP (R0.05) TYP VQFN - 1 mm max heightRGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 25 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 7 12 1924

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