CDC421XXX TI | Alldatasheet

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APPLICATIONS

External□Crystal Feedback Divider PFD/Charge□Pump Loop□Filter VCO Prescaler Output□Divider LVPECL CLK NCLK B0216-02

DESCRIPTION

LOW-JITTER, CRYSTAL-OSCILLATOR CLOCK GENERATOR Output Frequencies: 100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, Single 3.3 V Supply and 312.5 MHz High-Performance Clock Generator, Differential Low-Voltage Positive Emitter Incorporating Crystal Oscillator Circuitry With Coupled Logic (LVPECL) Output Integrated Frequency Synthesizer Fully Integrated Voltage-Controlled Oscillator Low Output Jitter, as Low as 380 fs (rms (VCO) Running from 1.75 GHz to 2.35 GHz integrated between kHz MHz) Typical Power Consumption 300 mW Low Phase Noise at 312.5 MHz, Less Than 120 dBc/Hz at kHz and 147 dBc/Hz at Chip-Enable Control Pin MHz Offset From the Carrier QFN-24 Package Supports Crystal Frequencies or LVCMOS ESD Protection Exceeds kV HBM Input Frequencies at 31.25 MHz, 33.33 MHz, Industrial Temperature Range C to C and 35.42 MHz A A Low-Cost, Low-Jitter Frequency Multiplier A A CDC421xxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. The output frequency out is proportional to the frequency of the input crystal xtal The device operates in a 3.3 V supply environment and is characterized for operation from C to CDC421xxx is available in a QFN-24 package. A high-level block diagram of the CDC421xxx is shown in Figure Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com Crystal Oscillator Feedback Divider Output Divider PFD/ Charge□Pump Prescaler Loop□FilterXIN□1 XIN□2 B0230-01 VCO PACKAGE (QFN-24) NC VCC RGE□PACKAGE (TOP VIEW) CDC421xxx NC NC XIN2XIN□1NC NC 24 23 22 21 20 19 NC NC 4NC 5NC GND 7 8 9 GND 10 11 OUTP NC NC 18 NC

17 VCC

a QFN-24 terminal package. The QFN package footprint is shown. Terminal locations and numbers are shown in Figure Figure Pinout of the CDC421xxx QFN-24 Package The terminal functions table shows the terminal descriptions for the CDC421xxx QFN-24 package. Table TERMINAL FUNCTIONS TERMINAL ESD TYPE NO. V CC 16, Power Y 3.3V power supply GND GND Y Ground In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the XIN I Y other end of the crystal. In LVCMOS single-ended driven mode, XIN1 (pin 21) acts XIN I N as input reference and XIN2 should connect to GND. Submit Documentation Feedback

www.ti.com DEVICE SELECTION ABSOLUTE MAXIMUM RATINGS CDC421xxx SLAS540 APRIL 2007 Table TERMINAL FUNCTIONS (continued) TERMINAL ESD TYPE NO. Chip enable (LVCMOS input) CE I Y CE enables the device and the outputs. CE disables all current sources (LVPECLP LVPECLN Hi-Z). OUTP O Y High-speed positive differential LVPECL output. (Outputs are enabled by CE OUTN O Y High-speed negative differential LVPECL output. (Outputs are enabled by CE 15, NC 20, 23, I or O Y TI test pin. Do not connect; leave floating. The CDC421xxx device is an LVPECL low-phase-noise clock generator designed to work with a low-frequency AT-crystal oscillator of a single-ended LVCMOS. Table Device Selection Table for CDC421xxx CDC421xxx OUTPUT FREQUENCY FOR INPUT FREQUENCY OR PACKAGE THE SPECIFIED INPUT DEVICE ORDERING CRYSTAL VALUE (MHz) FREQUENCY (MHz) MARKING PART NUMBER 421100 CDC421100RGER QFN-24 tape and reel 33.3333 100.00 421100 CDC421100RGET QFN-24 small tape and reel 33.3333 100.00 421106 CDC421106RGER QFN-24 tape and reel 35.4167 106.25 421106 CDC421106RGET QFN-24 small tape and reel 35.4167 106.25 421125 CDC421125RGER QFN-24 tape and reel 31.2500 125.00 421125 CDC421125RGET QFN-24 small tape and reel 31.2500 125.00 421156 CDC421156RGER QFN-24 tape and reel 31.2500 156.25 421156 CDC421156RGET QFN-24 small tape and reel 31.2500 156.25 421212 CDC421212RGER QFN-24 tape and reel 35.4167 212.50 421212 CDC421212RGET QFN-24 small tape and reel 35.4167 212.50 421250 CDC421250RGER QFN-24 tape and reel 31.2500 250.00 421250 CDC421250RGET QFN-24 small tape and reel 31.2500 250.00 421312 CDC421312RGER QFN-24 tape and reel 31.2500 312.50 421312 CDC421312RGET QFN-24 small tape and reel 31.2500 312.50 over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT V CC Supply voltage (2) 0.5 to 4.6 V V I Voltage range for all other input pins (2) 0.5 to V CC 0.5 V I O Output current for LVPECL mA Electrostatic discharge (HBM) k V T A Characterized free-air temperature range (no airflow) to C T J Maximum junction temperature 125 C T stg Storage temperature range to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. Submit Documentation Feedback

www.ti.com RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS CDC421xxx SLAS540 APRIL 2007 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V CC Supply voltage 3.3 3.6 V T A Ambient temperature, no airflow, no heat sink C over recommended operating conditions for CDC421xxx device PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V CC Supply voltage 3.3 3.6 V I VCC Total current at 3.3 V 3.3 312.5 MHz 110 mA LVPECL OUTPUT f CLK Output frequency 100 312.5 MHz V OH LVPECL high-level output voltage V CC 1.20 V CC 0.81 V V OL LVPECL low-level output voltage V CC 2.17 V CC 1.36 V OD LVPECL differential output voltage 407 1076 mV t r Output rise time 20% to 80% of V OUTpp 170 ps t f Output fall time 80% to 20% of V OUTpp 170 ps Duty cycle of the output waveform 45% 55% LVCMOS INPUT V IL,CMOS Low-level CMOS input voltage V CC 3.3 V 0.3 V CC V V IH,CMOS High-level CMOS input voltage V CC 3.3 V 0.7 V CC V I L,CMOS Low-level CMOS input current V CC V CC max V IL V 200 µ A I H,CMOS High-level CMOS input current V CC V CC min V IH 3.7 V 200 µ A Submit Documentation Feedback

www.ti.com JITTER CHARACTERISTICS IN INPUT CLOCK MODE S0246-02 CDC421xxx Phase□Noise Analyzer 150 /c87 150 /c87 150 /c87 50 /c87 XIN□1 XIN□2

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100□pF CDC421xxx SLAS540 APRIL 2007 The jitter characterization test is performed using an LVCMOS input signal driving the CDC421xxx device. Figure Jitter Test Configuration for an LVTTL Input Driving CDC421xxx For the cases of the CDC421xxx being referenced by an external, clean LVCMOS input of 31.25 MHz, 33.33 MHz and 35.4167 MHz, the following tables list the measured SSB phase noise of all the outputs supported by the CDC421xxx device, (100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and 312.5 MHz) from 100 Hz to MHz from the carrier. Table Phase Noise Parameters With LVCMOS Input of 33.3333 MHz and LVPECL Output at 100.00 MHz PARAMETER MIN TYP MAX UNIT Phase Noise Specifications Under Following Conditions: f in 33.3333 MHz, f out 100.00 MHz phn 100 Phase noise at 100 Hz 111 dBc/Hz phn Phase noise at kHz 121 dBc/Hz phn 10k Phase noise at kHz 131 dBc/Hz phn 100k Phase noise at 100 kHz 133 dBc/Hz phn Phase Noise at MHz 142 dBc/Hz phn 10M Phase noise at MHz 149 dBc/Hz phn 20M Phase noise at MHz 149 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 507 fs Tj Total jitter 35.33 ps Dj Deterministic jitter 11.54 ps Table Phase Noise Parameters With LVCMOS Input of 35.4167 MHz and LVPECL Output at 106.25 MHz PARAMETER MIN TYP MAX UNIT Phase Noise Specifications Under Following Conditions: f in 35.4167 MHz f out 106.25 MHz phn 100 Phase noise at 100 Hz 112 dBc/Hz phn Phase noise at kHz 121 dBc/Hz phn 10k Phase noise at kHz 125 dBc/Hz phn 100k Phase noise at 100 kHz 129 dBc/Hz phn Phase noise at MHz 142 dBc/Hz phn 10M Phase noise at MHz 151 dBc/Hz phn 20M Phase noise at MHz 151 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 530 fs Tj Total jitter 30.39 ps Dj Deterministic jitter ps Submit Documentation Feedback

www.ti.com CDC421xxx SLAS540 APRIL 2007 Table Phase Noise Parameters With LVCMOS Input of 31.2500 MHz and LVPECL Output at 125.00 MHz PARAMETER MIN TYP MAX UNIT Phase Noise Specifications Under Following Conditions: f in 31.2500 MHz, f out 125.00 MHz phn 100 Phase noise at 100 Hz 108 dBc/Hz phn Phase noise at kHz 118 dBc/Hz phn 10k Phase noise at kHz 127 dBc/Hz phn 100k Phase noise at 100 kHz 130 dBc/Hz phn Phase noise at MHz 139 dBc/Hz phn 10M Phase noise at MHz 147 dBc/Hz phn 20M Phase noise at MHz 147 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 529 fs Tj Total jitter 47.47 ps Dj Deterministic jitter 25.2 ps Table Phase Noise Parameters With LVCMOS Input of 31.2500 MHz and LVPECL Output at 156.25 MHz PARAMETER MIN TYP MAX UNIT Phase Noise Specifications Under Following Conditions: f in 31.2500 MHz, f out 156.25 MHz phn 100 Phase noise at 100 Hz 106 dBc/Hz phn Phase noise at kHz 117 dBc/Hz phn 10k Phase noise at kHz 126 dBc/Hz phn 100k Phase noise at 100 kHz 128 dBc/Hz phn Phase noise at MHz 139 dBc/Hz phn 10M Phase noise at MHz 147 dBc/Hz phn 20M Phase noise at MHz 147 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 472 fs Tj Total jitter 31.54 ps Dj Deterministic jitter 9.12 ps Table Phase Noise Parameters With LVCMOS Input of 35.4167 MHz and LVPECL Output at 212.50 MHz PARAMETER MIN TYP MAX UNIT Phase Noise Specifications Under Following Conditions: f in 35.4167 MHz, f out 212.50 MHz phn 100 Phase noise at 100 Hz 105 dBc/Hz phn Phase noise at kHz 115 dBc/Hz phn 10k Phase noise at kHz 119 dBc/Hz phn 100k Phase noise at 100 kHz 123 dBc/Hz phn Phase noise at MHz 135 dBc/Hz phn 10M Phase noise at MHz 148 dBc/Hz phn 20M Phase noise at MHz 148 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 512 fs Tj Total jitter 33.96 ps Dj Deterministic jitter 13.78 ps Submit Documentation Feedback

www.ti.com CDC421xxx SLAS540 APRIL 2007 Table Phase Noise Parameters With LVCMOS Input of 31.2500 MHz and LVPECL Output at 250.00 MHz PARAMETER MIN TYP MAX UNIT Phase Noise Specifications Under Following Conditions: f in 31.2500 MHz, f out 250.00 MHz phn 100 Phase noise at 100 Hz 103 dBc/Hz phn Phase noise at kHz 112 dBc/Hz phn 10k Phase noise at kHz 121 dBc/Hz phn 100k Phase noise at 100 kHz 124 dBc/Hz phn Phase noise at MHz 134 dBc/Hz phn 10M Phase noise at MHz 148 dBc/Hz phn 20M Phase noise at MHz 149 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 420 fs Tj Total jitter 36.98 ps Dj Deterministic jitter 18.52 ps Table Phase Noise Parameters With LVCMOS Input of 31.2500 MHz and LVPECL Output at 312.50 MHz PARAMETER MIN TYP MAX UNIT Phase Noise Specifications Under Following Conditions: f in 31.2500 MHz, f out 312.50 MHz phn 100 Phase noise at 100 Hz 102 dBc/Hz phn Phase noise at kHz 111 dBc/Hz phn 10k Phase noise at kHz 120 dBc/Hz phn 100k Phase noise at 100 kHz 123 dBc/Hz phn Phase noise at MHz 135 dBc/Hz phn 10M Phase noise at MHz 147 dBc/Hz phn 20M Phase noise at MHz 147 dBc/Hz J RMS RMS jitter integrated from kHz to MHz 378 fs Tj Total jitter 29.82 ps Dj Deterministic jitter ps Submit Documentation Feedback

PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 1

Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CDC421100RGER RGE 24 MLA 330 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421100RGET RGE 24 MLA 180 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421106RGER RGE 24 MLA 330 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421106RGET RGE 24 MLA 180 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421125RGER RGE 24 MLA 330 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421125RGET RGE 24 MLA 180 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421156RGER RGE 24 MLA 330 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421156RGET RGE 24 MLA 180 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421212RGER RGE 24 MLA 330 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421212RGET RGE 24 MLA 180 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421250RGER RGE 24 MLA 330 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421250RGET RGE 24 MLA 180 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421312RGER RGE 24 MLA 330 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P CDC421312RGET RGE 24 MLA 180 12 4.3 4.3 1.5 12 12 PKGORN T2TR-MS P PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 2

TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) CDC421100RGER RGE 24 MLA 346.0 346.0 29.0 CDC421100RGET RGE 24 MLA 190.0 212.7 31.75 CDC421106RGER RGE 24 MLA 346.0 346.0 29.0 CDC421106RGET RGE 24 MLA 190.0 212.7 31.75 CDC421125RGER RGE 24 MLA 346.0 346.0 29.0 CDC421125RGET RGE 24 MLA 190.0 212.7 31.75 CDC421156RGER RGE 24 MLA 346.0 346.0 29.0 CDC421156RGET RGE 24 MLA 190.0 212.7 31.75 CDC421212RGER RGE 24 MLA 346.0 346.0 29.0 CDC421212RGET RGE 24 MLA 190.0 212.7 31.75 CDC421250RGER RGE 24 MLA 346.0 346.0 29.0 CDC421250RGET RGE 24 MLA 190.0 212.7 31.75 CDC421312RGER RGE 24 MLA 346.0 346.0 29.0 CDC421312RGET RGE 24 MLA 190.0 212.7 31.75 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 4

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