CDC328 TI1 | Alldatasheet

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/C0067/C0068/C0067/C0051/C0050/C0056 /C0049/C0262/C0076/C0073/C0078/C0069/C0032/C0084/C0079/C0032/C0054/C0262/C0076/C0073/C0078/C0069/C0032/C0067/C0076/C0079/C0067/C0075/C0032/C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072/C0032/C0083/C0069/C0076/C0069/C0067/C0084/C0065/C0066/C0076/C0069/C0032/C0080/C0079/C0076/C0065/C0082/C0073/C0084/C0089 SCBS116B − JANUARY 1991 − REVISED MARCH 1994 Copyright  1994, Texas Instruments Incorporated 2−1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

  • Replaces SN74ABT328
  • Low Output Skew for Clock-Distribution and Clock-Generation Applications
  • TTL-Compatible Inputs and Outputs
  • Distributes One Clock Input to Six Clock Outputs
  • Polarity Control Selects True or Complementary Outputs
  • Distributed VCC and GND Pins Reduce Switching Noise
  • High-Drive Outputs (−15-mA IOH , 64-mA IOL )
  • State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages

description

The CDC328 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control inputs (T /C), various combinations of true and complementary outputs can be obtained. The CDC328 is characterized for operation from −40°C to 85°C. FUNCTION TABLE INPUTS OUTPUT T/C A OUTPUT Y L L L L HH H LH H H L logic symbol† A 1Y1 1Y2 2Y1 2Y2 1T/C 2T/C 3T/C 4T/C † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. D OR DB PACKAGE (TOP VIEW) GND 1Y2 2Y1 GND 2Y2 GND 1Y1 VCC 2T/C A VCC 3T/C 4T/C EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0067/C0068/C0067/C0051/C0050/C0056 /C0049/C0262/C0076/C0073/C0078/C0069/C0032/C0084/C0079/C0032/C0054/C0262/C0076/C0073/C0078/C0069/C0032/C0067/C0076/C0079/C0067/C0075/C0032/C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072/C0032/C0083/C0069/C0076/C0069/C0067/C0084/C0065/C0066/C0076/C0069/C0032/C0080/C0079/C0076/C0065/C0082/C0073/C0084/C0089 SCBS116B − JANUARY 1991 − REVISED MARCH 1994 2−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 logic diagram (positive logic) 1Y1 1Y2 2Y1 2Y2 A 2T/C 3T/C 4T/C absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range applied to any output in the high state † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. For operation above 25°C free-air temperature, derate to 478 mW at 85°C at the rate of 8.7 mW/°C. recommended operating conditions (see Note 3) MIN NOM MAX UNIT VCC Supply voltage 4.75 5 5.25 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V IOH High-level output current −15 mA IOL Low-level output current 64 mA ∆t/∆v Input transition rise or fall rate 5 ns/V fclock Input clock frequency 80 MHz TA Operating free-air temperature −40 85 °C NOTE 3: Unused inputs must be held high or low.

/C0067/C0068/C0067/C0051/C0050/C0056 /C0049/C0262/C0076/C0073/C0078/C0069/C0032/C0084/C0079/C0032/C0054/C0262/C0076/C0073/C0078/C0069/C0032/C0067/C0076/C0079/C0067/C0075/C0032/C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072/C0032/C0083/C0069/C0076/C0069/C0067/C0084/C0065/C0066/C0076/C0069/C0032/C0080/C0079/C0076/C0065/C0082/C0073/C0084/C0089 SCBS116B − JANUARY 1991 − REVISED MARCH 1994 2−3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 4.75 V, II = −18 mA −1.2 V VOH VCC = 4.75 V, IOH = −15 mA 2.5 V VOL VCC = 4.75 V, IOL = 64 mA 0.55 V II VCC = 5.25 V, VI = VCC or GND ±1 µA IO ‡ VCC = 5.25 V, VO = 2.5 V −15 −100 mA ICC VCC = 5.25 V, I O = 0, Outputs high 50 µA ICC VCC = 5.25 V, I O = 0, VI = VCC or GND Outputs low 20 30 mA C i VI = 2.5 V or 0.5 V 3 pF † All typical values are at VCC = 5 V, TA = 25°C ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT tPLH A Any Y 1.7 7 nstPHL A Any Y 1.5 5.4 ns tPLH T/C Any Y 1.5 8 nstPHL T/C Any Y 1.4 6.6 ns tsk(o) A Any Y (same phase) 0.7 nstsk(o) A Any Y (any phase) 2.6 ns tr 1.2 ns tf 0.5 ns switching characteristics, VCC = 5 V ± 0.25 V, TA = 25°C to 70°C (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tPLH A Any Y 2.1 6.1 nstPHL A Any Y 1.7 4.8 ns tsk(o) A Any Y (same phase) 0.7 nstsk(o) A Any Y (any phase) 2.1 ns

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. Figure 1. Load Circuit and Voltage Waveforms

Figure 2. Waveforms for Calculation of tsk(o)

/C0067/C0068/C0067/C0051/C0050/C0056 /C0049/C0262/C0076/C0073/C0078/C0069/C0032/C0084/C0079/C0032/C0054/C0262/C0076/C0073/C0078/C0069/C0032/C0067/C0076/C0079/C0067/C0075/C0032/C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072/C0032/C0083/C0069/C0076/C0069/C0067/C0084/C0065/C0066/C0076/C0069/C0032/C0080/C0079/C0076/C0065/C0082/C0073/C0084/C0089 SCBS116B − JANUARY 1991 − REVISED MARCH 1994 2−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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