CDC319 TI | Alldatasheet
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1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM (Synchronous DRAM) Clock Buffering Applications /C0068 Output Skew, tsk(o), Less Than 250 ps /C0068 Pulse Skew, tsk(p), Less Than 500 ps /C0068 Supports up to Two Unbuffered SDRAM DIMMs (Dual Inline Memory Modules) /C0068 I2C Serial Interface Provides Individual Enable Control for Each Output /C0068 Operates at 3.3 V /C0068 Distributed VCC and Ground Pins Reduce Switching Noise /C0068 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 /C0068 Packaged in 28-Pin Shrink Small Outline (DB) Package
description
The CDC319 is a high-performance clock buffer that distributes one input (A) to 10 outputs (Y) with minimum skew for clock distribution. The CDC319 operates from a 3.3-V power supply, and is characterized for operation from 0°C to 70°C. The device provides a standard mode (100K-bits/s) I 2C serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs (SDATA and SCLOCK) provide integrated pullup resistors (typically 140 kΩ ) and are 5-V tolerant. Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register. The registers are write only and must be accessed in sequential order (i.e., random access of the registers is not supported). The CDC319 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state. When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor. Copyright 2001, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VCC 1Y0 1Y1 GND VCC 1Y2 1Y3 GND A V CC 3Y0 GND VCC SDATA VCC 2Y3 2Y2 GND VCC 2Y1 2Y0 GND OE V CC 3Y1 GND GND SCLOCK DB PACKAGE (TOP VIEW)
1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001
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OE A 1Y0–1Y3 2Y0–2Y3 3Y0–3Y1 L X Hi-Z Hi-Z Hi-Z H L L L L H H H † H † H † † The function table assumes that all outputs are enabled via the appropriate I2C configuration register bit. If the output is disabled via the appropriate configuration bit, then the output is driven to a low state, regardless of the state of the A input. logic diagram (positive logic) 1Y0–1Y3 2Y0–2Y3 3Y0 – 3Y1 OE SDATA SCLOCK A I2C Register Space I2C 2, 3, 6, 7 22, 23, 26, 27 11, 18 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION 1Y0–1Y3 2, 3, 6, 7 O 3.3-V SDRAM byte 0 clock outputs 2Y0–2Y3 22, 23, 26, 27 O 3.3-V SDRAM byte 1 clock outputs 3Y0–3Y1 11, 18 O 3.3-V clock outputs provided for feedback control of external PLLs (phase-locked loops) A 9 I Clock input OE 20 I Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal 140-kΩ pullup resistor is internally integrated. SCLOCK 15 I I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated. SDATA 14 I/O Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally integrated. GND 4, 8, 12, 16, 17, 21, 25 Ground VCC 1, 5, 10, 13, 19, 24, 28 3.3-V power supply
1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I2C DEVICE ADDRESS A7 A6 A5 A4 A3 A2 A1 A0 (R/W) H H L H L L H — I2C BYTE 0-BIT DEFINITION† BIT DEFINITION DEFAULT VALUE
7 Reserved H
6 Reserved H
5 Reserved H
4 Reserved H
3 1Y3 enable (pin 7) H 2 1Y2 enable (pin 6) H 1 1Y1 enable (pin 3) H 0 1Y0 enable (pin 2) H † When the value of the bit is high, the output is enabled. When the value of the bit is low, the output is forced to a low state. The default value of all bits is high. I2C BYTE 1-BIT DEFINITION† BIT DEFINITION DEFAULT VALUE 7 2Y3 enable (pin 27) H 6 2Y2 enable (pin 26) H 5 2Y1 enable (pin 23) H 4 2Y0 enable (pin 22) H
3 Reserved H
2 Reserved H
1 Reserved H
0 Reserved H
† When the value of the bit is high, the output is enabled. When the value of the bit is low, the output is forced to a low state. The default value of all bits is high. I2C BYTE 2-BIT DEFINITION† BIT DEFINITION DEFAULT VALUE 7 3Y1 enable (pin 18) H 6 3Y0 enable (pin 11) H † When the value of the bit is high, the output is enabled. When the value of the bit is low, the output is forced to a low state. The default value of all bits is high.
1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) MIN TYP MAX UNIT VCC 3.3-V core supply voltage 3.135 3.465 V A, OE 2 VCC +0.3 V VIH High-level input voltage SDATA, SCLOCK (see Note 3) 2.2 5.5 V A, OE –0.3 0.8 V VIL Low-level input voltage SDATA, SCLOCK (see Note 3) 0 1.04 V IOH High-level output current Y outputs –24 mA IOL Low-level output current Y outputs 24 mA R I Input resistance to VCC SDATA, SCLOCK (see Note 3) 140 kΩ f(SCL) SCLOCK frequency 100 kHz t(BUS) Bus free time 4.7 µs tsu(START) START setup time 4.7 µs th(START) START hold time 4 µs tw(SCLL) SCLOCK low pulse duration 4.7 µs tw(SCLH) SCLOCK high pulse duration 4 µs tr(SDATA) SDATA input rise time 1000 ns tf(SDATA) SDATA input fall time 300 ns tsu(SDATA) SDATA setup time 250 ns th(SDATA) SDATA hold time 0 ns tsu(STOP) STOP setup time 4 µs TA Operating free-air temperature 0 70 °C NOTE 3: The CMOS-level inputs fall within these limits: VIH min = 0.7× VCC and VIL max = 0.3 × VCC .
1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIK Input clamp voltage VCC = 3.135 V, II = –18 mA –1.2 V VOH High-level output voltageY outputs VCC = 3.135 V, IOH = –1 mA 2.4 V Y outputs VCC = 3.135 V, IOL = 1 mA 0.4 VOL Low-level output voltage SDATA VCC = 3 135 V IOL = 3 mA 0.1 0.4 V SDATA VCC = 3.135 V IOL = 6 mA 0.2 0.6 SDATA VCC = 3.135 V, VO = VCC MAX 20 µA IOH High level output current VCC = 3.135 V, VO = 2 V –54 –126 IOH High-level output current Y outputs VCC = 3.3 V, VO = 2.6 V –60 mA VCC = 3.465 V, VO = 3.135 V –21 –46 VCC = 3.135 V, VO = 1 V 49 118 IOL Low-level output current Y outputs VCC = 3.3 V, VO = 0.7 V 58 mA VCC = 3.465 V, VO = 0.4 V 23 53 A 5 IIH High-level input current OE VCC = 3.465 V, VI = VCC 20 µA SCLOCK, SDATA 20 A –5 IIL Low-level input current OE VCC = 3.465 V, VI = GND –10 –50 µA SCLOCK, SDATA –10 –50 IOZ High-impedance-state output current VCC = 3.465 V, VO = 3.465 V or 0 ±10 µA Ioff Off-state current SCLOCK, SDATA VCC = 0 V, VI = 0 V to 5.5 V 50 µA ICC Supply current VCC = 3.465 V, IO = 0 0.2 0.5 mA ∆ICC Change in supply current VCC = 3.135 V to 3.465 V, One input at VCC – 0.6 V, All other inputs at VCC or GND 500 µA C i Input capacitiance VI = VCC or GND, VCC = 3.3 V 4 pF C o Output capacitance VO = VCC or GND, VCC = 3.3 V 6 pF C I/O SDATA I/O capacitance VI/O = VCC or GND, VCC = 3.3 V 7 pF
1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001
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switching characteristics over recommended operating conditions PARAMETER FROM TO TEST CONDITIONS MIN MAX UNIT A Y 1.2 3.6 ns tPLH Low-to-high level propagation delay timeSCLOCK ↓ SDATA valid VCC = 3.3 V ±0.185 V, See Figure 3 2 µs tPLH Low-to-high level propagation delay timeSDATA ↑ Y VCC = 3.3 V ±0.185 V, See Figure 3 150 ns A Y 1.2 3.6 ns tPHL High-to-low level propagation delay timeSCLOCK ↓ SDATA valid VCC = 3.3 V ±0.185 V, See Figure 3 2 µs tPHL High-to-low level propagation delay timeSDATA ↑ Y VCC = 3.3 V ±0.185 V, See Figure 3 150 ns tPZH Enable time to the high level tPZL Enable time to the low level OE Y 1 47 ns tPHZ Disable time from the high level OE Y 1 4.7 ns tPLZ Disable time from the low level tsk(o) Skew time A Y 250 ps tsk(p) Skew time A Y 500 ps tsk(pr) Skew time A Y 1 ns tr Rise time Y 0.5 1.3 ns t Rise time (see Note 4 and SDATA C L = 10 pF 6 nstr Figure 3) SDATA C L = 400 pF 250 ns tf Fall time Y 0.5 1.3 ns tf Fall time (see Note 4 and SDATA C L = 10 pF 20 nstf Figure 3) SDATA C L = 400 pF 250 ns C L = 30 pF, TA = 70°C 100 f Operating frequency (see Note 5) C L = 20 pF, TA = 70°C 125 MHz C L = 15 pF, TA = 70°C 140 NOTES: 4. This parameter has a lower limit than BUS specification. This allows use of series resistors for current spike protection. 5. See Figure 4 (Frequency versus Capacitive Load).
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms
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B. Pulse skew, tsk(p), is calculated as the greater of |tPLHn – tPHLn | (n = 1:10). Figure 2. Waveforms for Calculation of tsk(o), tsk(p), tsk(pr)
0.7 VCC
0.3 VCC
1 I2C address
2 Command (dummy value, ignored)
3 Byte count (dummy value, ignored)
4 I2C data byte 0
5 I2C data byte 1
6 I2C data byte 2
NOTES: A. The repeat start condition is not supported. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 kHz, ZO = 50 Ω , tr ≥ 10 ns, tf≥ 10 ns. Figure 3. Propagation Delay Times, tr and tf
1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001
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SUPPORTED MAXIMUM CLOCK FREQUENCY f – Supported Maximum Clock Frequency – MHz 130 50 70 90 110 120100806040 140 150 – Capaccitive Load – pFCL TA = 55°C TJ = 130°C VDD = 3.465 V TA = 70°C TJ = 130°C VDD = 3.6 V NOTES: A. With a total capacitive load of 20 pF for each output, the CDC319 is capable of running up to about 125 MHz. A lower capacitive load will allow higher application frequencies, up to 133 MHz (140 MHz). B. CPD for the CDC319 is about 25 pF per output (21 pF if CL < 20 pF) P(total) = VDD2 × CPD × FO × N + (VOH – VOL )2 × CL × FO × N + DC load where: N = number of switching outputs FO = clock frequency Package thermal impedance (junction-to-ambient) = 92.4°C/W Maximum junction temperature = 150°C (<125°C recommended) Figure 4
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDC319DB Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 CDC319 CDC319DB.B Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 CDC319 CDC319DBR Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 CDC319 CDC319DBR.B Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 CDC319 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC319DBR SSOP DB 28 2000 356.0 356.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CDC319DB DB SSOP 28 50 530 10.5 4000 4.1 CDC319DB.B DB SSOP 28 50 530 10.5 4000 4.1 Pack Materials-Page 3
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