CDC318ADLG4

CDC318A_12 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SCAS614,A]
• PDF pages: 14

Technical content

/C0067/C0068/C0067/C0051/C0049/C0056/C0065 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0056/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications /C0068Output Skew, tsk(o), Less Than 250 ps /C0068Pulse Skew, tsk(p), Less Than 500 ps /C0068Supports up to Four Unbuffered SDRAM Dual Inline Memory Modules (DIMMs) /C0068I2C Serial Interface Provides Individual Enable Control for Each Output /C0068Operates at 3.3 V /C0068Distributed VCC and Ground Pins Reduce Switching Noise /C0068100-MHz Operation /C0068ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 /C0068Packaged in 48-Pin Shrink Small Outline (DL) Package

description

The CDC318A is a high-performance clock buffer designed to distribute high-speed clocks in PC applications. This device distributes one input (A) to 18 outputs (Y) with minimum skew for clock distribution. The CDC318A operates from a 3.3-V power supply. It is characterized for operation from 0°C to 70°C. This device has been designed with consideration for optimized EMI performance. Depending on the application layout, damping resistors in series to the clock outputs (like proposed in the PC100 specification) may not be needed in most cases. The device provides a standard mode (100K-bits/s) I 2C serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs (SDATA and SCLOCK) are 5-V tolerant and provide integrated pullup resistors (typically 140 kΩ). Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register. The registers are write only and must be accessed in sequential order (i.e., random access of the registers is not supported). The CDC318A provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state. When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor. Copyright  2002, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DL PACKAGE (TOP VIEW) NC NC VCC 1Y0 1Y1 GND V CC 1Y2 1Y3 GND A VCC 2Y0 2Y1 GND V CC 2Y2 2Y3 GND V CC 5Y0 GND VCC SDATA NC NC V CC 4Y3 4Y2 GND V CC 4Y1 4Y0 GND OE V CC 3Y3 3Y2 GND V CC 3Y1 3Y0 GND V CC 5Y1 GND GND SCLOCK NC − No internal connection

/C0067/C0068/C0067/C0051/C0049/C0056/C0065 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0056/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002

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OE A 1Y0−1Y3 2Y0−2Y3 3Y0−3Y3 4Y0−4Y3 5Y0−5Y1 L X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L L L L L † The function table assumes that all outputs are enabled via the appropriate I2C configuration register bit. If the output is disabled via the appropriate configuration bit, then the output is driven to a low state, regardless of the state of the A input. logic diagram (positive logic) 1Y0−1Y3 2Y0−2Y3 3Y0−3Y3 4Y0−4Y3 5Y0−5Y1 OE SDATA SCLOCK A I2C Register Space I2C 4, 5, 8, 9 13, 14, 17, 18 31, 32, 35, 36 40, 41, 44, 45 21, 28

/C0067/C0068/C0067/C0051/C0049/C0056/C0065 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0056/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION 1Y0−1Y3 4, 5, 8, 9 O 3.3-V SDRAM byte 0 clock outputs 2Y0−2Y3 13, 14, 17, 18 O 3.3-V SDRAM byte 1 clock outputs 3Y0−3Y3 31, 32, 35, 36 O 3.3-V SDRAM byte 2 clock outputs 4Y0−4Y3 40, 41, 44, 45 O 3.3-V SDRAM byte 3 clock outputs 5Y0−5Y1 21, 28 O 3.3-V clock outputs provided for feedback control of external phase-locked loops (PLLs) A 11 I Clock input OE 38 I Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal 140-kΩ pullup resistor is internally integrated. SCLOCK 25 I I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated. SDATA 24 I/O Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally integrated. GND 6, 10, 15, 19, 22, 26, 27, 30, 34, 39, 43 Ground NC 1, 2, 47, 48 No internal connection. Reserved for future use. VCC 29, 33, 37, 42, 46 3.3-V power supply I2C DEVICE ADDRESS A7 A6 A5 A4 A3 A2 A1 A0 (R/W) H H L H L L H — I2C BYTE 0-BIT DEFINITION† BIT DEFINITION DEFAULT VALUE 7 2Y3 enable (pin 18) H 6 2Y2 enable (pin 17) H 5 2Y1 enable (pin 14) H 4 2Y0 enable (pin 13) H 3 1Y3 enable (pin 9) H 2 1Y2 enable (pin 8) H 1 1Y1 enable (pin 5) H 0 1Y0 enable (pin 4) H † When the value of the bit is high, the output is enabled. When the value of the bit is low, the output is forced to a low state. The default value of all bits is high.

/C0067/C0068/C0067/C0051/C0049/C0056/C0065 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0056/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002

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I2C BYTE 1-BIT DEFINITION† BIT DEFINITION DEFAULT VALUE 7 4Y3 enable (pin 45) H 6 4Y2 enable (pin 44) H 5 4Y1 enable (pin 41) H 4 4Y0 enable (pin 40) H 3 3Y3 enable (pin 36) H 2 3Y2 enable (pin 35) H 1 3Y1 enable (pin 32) H 0 3Y0 enable (pin 31) H † When the value of the bit is high, the output is enabled. When the value of the bit is low, the output is forced to a low state. The default value of all bits is high. I2C BYTE 2-BIT DEFINITION† BIT DEFINITION DEFAULT VALUE 7 5Y1 enable (pin 28) H 6 5Y0 enable (pin 21) H

5 Reserved H

4 Reserved H

3 Reserved H

2 Reserved H

1 Reserved H

0 Reserved H

† When the value of the bit is high, the output is enabled. When the value of the bit is low, the output is forced to a low state. The default value of all bits is high.

/C0067/C0068/C0067/C0051/C0049/C0056/C0065 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0056/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. The absolute maximum power dissipation allowed at TA = 55°C (in still air) is 1.2 W. 3. Thermal impedance (ΘJA) can be considerably lower if the device is soldered on the PCB board with a copper layer underneath the (202) in area underneath the package, resulted in ΘJA = 60°C/W. This would allow 1.2 W total power dissipation at TA = 70°C. recommended operating conditions (see Note 4) MIN TYP MAX UNIT VCC 3.3-V core supply voltage 3.135 3.465 V A, OE 2 VCC +0.3 V VIH High-level input voltage SDATA, SCLOCK (see Note 3) 2.2 5.5 V A, OE −0.3 0.8 V VIL Low-level input voltage SDATA, SCLOCK (see Note 3) 0 1.04 V IOH High-level output current Y outputs −36 mA IOL Low-level output current Y outputs 24 mA ri Input resistance to VCC SDATA, SCLOCK (see Note 3) 140 kΩ f(SCL) SCLOCK frequency 100 kHz t(BUS) Bus free time 4.7 µs tsu(START) START setup time 4.7 µs th(START) START hold time 4 µs tw(SCLL) SCLOCK low pulse duration 4.7 µs tw(SCLH) SCLOCK high pulse duration 4 µs tr(SDATA) SDATA input rise time 1000 ns tf(SDATA) SDATA input fall time 300 ns tsu(SDATA) SDATA setup time 250 ns th(SDATA) SDATA hold time 20 ns tsu(STOP) STOP setup time 4 µs TA Operating free-air temperature 0 70 °C NOTE 4: The CMOS-level inputs fall within these limits: VIH min = 0.7× VCC and VIL max = 0.3 × VCC .

/C0067/C0068/C0067/C0051/C0049/C0056/C0065 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0056/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIK Input clamp voltage VCC = 3.135 V, II = −18 mA −1.2 V VOH High-level output voltageY outputs VCC = Min to Max, IOH = −1 mA VCC −

0.1 V VVOH High-level output voltageY outputs

VCC = 3.135 V, IOH = −36 mA 2.4 V Y outputs VCC = Min to Max, IOL = 1 mA 0.1 VOL Low-level output voltage Y outputs VCC = 3.135 V, IOL = 24 mA 0.4 VVOL Low-level output voltage SDATA VCC = 3.135 V IOL = 3 mA 0.4 V SDATA VCC = 3.135 V IOL = 6 mA 0.6 SDATA VCC = 3.135 V, VO = VCC MAX 20 µA IOH High-level output current VCC = 3.135 V, VO = 2 V −54 −126 IOH High-level output current Y outputs VCC = 3.3 V, VO = 1.65 V −92 mAY outputs VCC = 3.465 V, VO = 3.135 V −21 −46 mA VCC = 3.135 V, VO = 1 V 49 118 IOL Low-level output currentY outputs VCC = 3.3 V, VO = 1.65 V 93 mAIOL Low-level output currentY outputs VCC = 3.465 V, VO = 0.4 V 24 53 mA A 5 IIH High-level input currentOE VCC = 3.465 V, VI = VCC 20 µAIIH High-level input current SCLOCK, SDATA VCC = 3.465 V, VI = VCC µA A −5 IIL Low-level input current OE VCC = 3.465 V, VI = GND −10 −50 µAIIL Low-level input current SCLOCK, SDATA VCC = 3.465 V, VI = GND −10 −50 µA IOZ High-impedance-state output current VCC = 3.465 V, VO = 3.465 V or 0 ±10 µA Ioff Off-state current SCLOCK, SDATA VCC = 0, VI = 0 V to 5.5 V 50 µA ICC Supply current VCC = 3.465 V, IO = 0 0.2 0.5 mA ∆ICC Change in supply current VCC = 3.135 V to 3.465 V, One input at VCC − 0.6 V, All other inputs at VCC or GND 500 µA Dynamic ICC at 100 MHz VCC = 3.465 V, C L = 20 pF, 230 mA C I Input capacitance VI = VCC or GND, VCC = 3.3 V 4 pF C O Output capacitance VO = VCC or GND, VCC = 3.3 V 6 pF C I/O SDATA I/O capacitance VI/O = VCC or GND, VCC = 3.3 V 7 pF

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NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

Figure 2. Waveforms for Calculation of tsk(o), tsk(p), tsk(pr)

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.7 VCC

0.3 VCC

1 I2C address

2 Command (dummy value, ignored)

3 Byte count (dummy value, ignored)

4 I2C data byte 0

5 I2C data byte 1

6 I2C data byte 2

NOTES: A. The repeat start condition is not supported. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 kHz, ZO = 50 Ω, tr ≥ 10 ns, tf ≥ 10 ns. Figure 3. Propagation Delay Times, tr and tf

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDC318ADL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDC318ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDC318ADLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDC318ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2006 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC318ADLR SSOP DL 48 1000 367.0 367.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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