CDC303 TI | Alldatasheet
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OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS323A – JULY 1990 – REVISED NOVEMBER 1995 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Replaces SN74AS303 /C0068Maximum Output Skew Between Same Phase Outputs of 1 ns /C0068Maximum Pulse Skew of 1 ns /C0068TTL-Compatible Inputs and Outputs /C0068Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise /C0068Package Options Include Plastic Small-Outline (D) Package and Standard Plastic (N) 300-mil DIPs
description
The CDC303 contains eight flip-flops designed to have low skew between outputs. The eight outputs (six in-phase with CLK and two out-of-phase) toggle on successive CLK pulses. Preset (PRE ) and clear (CLR) inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input. The CDC303 has output and pulse-skew parameters tsk(o) and tsk(p) to ensure performance as a clock driver when a divide-by-two function is required. The CDC303 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS CLR PRE CLK Q1–Q6 Q 7–Q 8 L H X L H H LX H L L LXL † L† H H ↑ Q 0 Q 0 H H L Q 0 Q 0 † This configuration does not persist when PRE or CLR returns to its inactive (high) level. logic symbol‡ S R CLK T PRE CLR Q 8 Q 7 ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Copyright 1995, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. GND GND GND Q CLR VCC VCC CLK PRE Q 8 D OR N PACKAGE (TOP VIEW)
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
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logic diagram (positive logic) CLK R S Q 7 Q 8 PRE CLR absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils, except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IOH High-level output current –24 mA IOL Low-level output current 48 mA fclock Input clock frequency 80 MHz TA Operating free-air temperature 0 70 °C
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS323A – JULY 1990 – REVISED NOVEMBER 1995 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 V VOH VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2 VVOH VCC = 4.5 V, IOH = –24 mA 2 2.8 V VOL VCC = 4.5 V, IOL = 48 mA 0.3 0.5 V II VCC = 5.5 V, VI = 7 V 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 mA IIL VCC = 5.5 V, VI = 0.4 V –0.5 mA IO ‡ VCC = 5.5 V, VO = 2.25 V –50 –150 mA ICC VCC = 5.5 V, See Note 2 40 70 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS . NOTE 2: ICC is measured with CLK and PRE grounded, then with CLK and CLR grounded. timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT fclock Clock frequency 0 80 MHz CLR or PRE low 5 tw Pulse duration CLK high 4 ns CLK low 6 tsu Setup time before CLK↑ CLR or PRE inactive 6 ns switching characteristics over recommended operating free-air temperature range (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN MAX UNIT fmax § 80 MHz tPLH CLK QQ R L = 500W C L =5 0pF 2 9 ns tPHL CLK Q , Q R L = 500 W , C L = 50 pF 2 9 ns tPLH PRE or CLR QQ R L = 500W C L =5 0pF 3 12 ns tPHL PRE or CLR Q , Q R L = 500 W , C L = 50 pF 3 12 ns Q R 500 W C 1 0F t3 0F tsk(o) CLK Q R L = 500 W , See Figure 2 C L = 10 pF to 30 pF, 1 ns() Q, Q See Figure 2 tsk(p) CLK Q, Q R L = 500 W , C L = 10 pF to 30 pF 1 ns tr 4.5 ns tf 3.5 ns § fmax minimum values are at CL = 0 to 30 pF.
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NOTES: A. C L includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = 2.5 ns, tf = 2.5 ns. Figure 1. Load Circuit and Voltage Waveforms
B. tsk(o), CLK to Q, is calculated as the greater of: | tPLH7 – tPLH8 | and | tPHL7 – tPHL8 |. Figure 2. Waveforms for Calculation of tsk(o) and tsk(p)
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CDC303D ACTIVE SOIC D 16 Green (RoHS & no Sb/Br) CU NIPD Level-1-260C-UNLIM CDC303DR ACTIVE SOIC D 16 Green (RoHS & no Sb/Br) CU NIPD Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 2-May-2005 Addendum-Page 1
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