CDC208_16 TI1 | Alldatasheet
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/C0067/C0068/C0067/C0050/C0048/C0056 /C0068/C0085/C0065/C0076 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 /C0261 SCAS109F − APRIL 1990 − REVISED OCTOBER 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low-Skew Propagation Delay Specifications for Clock-Driver
Applications
/C0068TTL-Compatible Inputs and CMOS-Compatible Outputs /C0068Flow-Through Architecture Optimizes PCB Layout /C0068Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise /C0068EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process /C0068500-mA Typical Latch-Up Immunity at 125°C /C0068Package Options Include Plastic Small-Outline (DW)
description
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input. Skew parameters are specified for a reduced temperature and voltage range common to many applications. The CDC208 is characterized for operation from −40°C to 85°C. FUNCTION TABLES INPUTS OUTPUTS 1OE1 1OE2 1A 1Y1 1Y2 1Y3 1Y4 L L L L L L L L LHH HHH L HXL LLL H LXH HHH H H X Z Z Z Z INPUTS OUTPUTS 2OE1 2OE2 2A 2Y1 2Y2 2Y3 2Y4 L L L L L L L L LHH HHH L HXL LLL H LXH HHH H H X Z Z Z Z Copyright 1998, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 /C0261 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. 1Y2 1Y3 1Y4 GND GND GND GND 2Y1 2Y2 2Y3 1Y1 1OE1 1OE2 VCC VCC 2OE1 2OE2 2Y4 DW PACKAGE (TOP VIEW)
/C0067/C0068/C0067/C0050/C0048/C0056 /C0068/C0085/C0065/C0076 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 /C0261 SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol† X/Y 1Y1 1Y2 1Y3 1Y4 EN 2Y1 2Y2 2Y3 2Y4 4, 5 1OE1 1OE2 2OE1 2OE2 4, 5 4, 5 4, 5 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1Y120 1OE1 1OE2 17 1A 19 1Y21 1Y32 1Y43 2Y18 2OE1 13 2OE2 12 2A 14 2Y29 2Y310 2Y411
/C0067/C0068/C0067/C0050/C0048/C0056 /C0068/C0085/C0065/C0076 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 /C0261 SCAS109F − APRIL 1990 − REVISED OCTOBER 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V IOH High-level output current −24 mA IOL Low-level output current 24 mA ∆t/∆v Input transition rise or fall rate 0 10 ns/V fclock Input clock frequency 60 MHz TA Operating free-air temperature −40 85 °C
/C0067/C0068/C0067/C0050/C0048/C0056 /C0068/C0085/C0065/C0076 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 /C0261 SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C MIN MAX UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX UNIT IOH = −50 A 4.5 V 4.4 4.4 IOH = −50 µA 5.5 V 5.4 5.4 VOH IOH = −24 mA V IOH = −75 mA† 5.5 V 3.85 IOL = 50 A 4.5 V 0.1 0.1 IOL = 50 µA 5.5 V 0.1 0.1 VOL IOL = 24 mA V IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 µA IOZ VO = VCC or GND 5.5 V ±0.5 ±5 µA ICC VI = VCC or GND, IO = 0 5.5 V 8 80 µA ∆ICC ‡ One input at 3.4 V, Other inputs at VCC or GND 5.5 V 0.9 1 mA C i VI = VCC or GND 5 V 4 pF C o VO = VCC or GND 5 V 10 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC .
/C0067/C0068/C0067/C0050/C0048/C0056 /C0068/C0085/C0065/C0076 /C0049/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0067/C0076/C0079/C0067/C0075 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 /C0261 SCAS109F − APRIL 1990 − REVISED OCTOBER 1998 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TA = 25°C MIN MAX UNITPARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX MIN MAX UNIT tPLH 1A and 2A Any Y nstPHL 1A and 2A Any Y 3.6 7.7 11 3.6 11.5 ns tPLH 1OE1 , 1OE2, and Any Y nstPHL 1OE1, 1OE2, and tPZH 1OE2 or 2OE2 Any Y nstPZL 1OE1 or 2OE1 Any Y 5 9.6 13.3 5 14.9 ns tPHZ 1OE2 or 2OE2 Any Y ns tPLZ 1OE1 or 2OE1 Any Y ns switching characteristics, VCC = 5 V ± 0.25 V, TA = 25°C to 70°C (see Note 3 and Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tPLH 1A and 2A Any Y 6.6 10.2 nstPHL 1A and 2A Any Y 6.6 9.8 ns tsk(o) 1A and 2A Any Y 1 ns NOTE 3: All specifications are valid only for all outputs switching simultaneously and in phase. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per bank Outputs enabled C L = 50 pF, f = 1 MHz pFC pd Power dissipation capacitance per bank Outputs disabled C L = 50 pF, f = 1 MHz pF
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf≤ 3 ns. For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Figure 1. Load Circuit and Voltage Waveforms
Figure 2. Waveforms for Calculation of tsk(o)
www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples CDC208DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI CDC208DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC208 CDC208DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC208 CDC208DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC208 CDC208DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC208 CDC208N OBSOLETE PDIP N 20 TBD Call TI Call TI CDC208NS ACTIVE SO NS 20 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDC208 CDC208NSG4 ACTIVE SO NS 20 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDC208 CDC208NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDC208 CDC208NSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDC208 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
www.ti.com 11-Apr-2013 Addendum-Page 2 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC208DWR SOIC DW 20 2000 367.0 367.0 45.0 CDC208NSR SO NS 20 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2015 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C TYP10.63 9.97
2.65 MAX
18X 1.27 20X 0.51 0.31 11.43 TYP0.33 0.10 0 - 8 0.3 0.1 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 13.0 12.6 B 7.6 7.4 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. 1 20
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.200
www.ti.com EXAMPLE BOARD LAYOUT (9.3)
0.07 MAX
0.07 MIN
20X (2) 20X (0.6) 18X (1.27) (R ) TYP 0.05 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 10 11 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (9.3) 18X (1.27) 20X (0.6) 20X (2) 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 10 11 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01
28 PINS SHOWN
8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
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