CD74AC112E

CD74AC112 TI | Alldatasheet

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CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage /C0068 Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption /C0068 Balanced Propagation Delays /C0068 ±24-mA Output Drive Current – Fanout to 15 F Devices /C0068 SCR-Latchup-Resistant CMOS Process and Circuit Design /C0068 Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 description/ordering information The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE ) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – E Tube CD74AC112E CD74AC112E 55°Ct o1 2 5°C SOIC M Tube CD74AC112M AC112M–55°C to 125°C SOIC – M Tape and reel CD74AC112M96 AC112M CDIP – F Tube CD54AC112F3A CD54AC112F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. CD54AC112 ...F PACKAGE CD74AC112 ...E O R M PACKAGE (TOP VIEW) 1CLK 1PRE GND VCC 1CLR 2CLR 2CLK 2PRE Copyright  2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003

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(each flip-flop) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LXXXL H L LXXX H † H † H H ↓ LL Q 0 Q 0 H H ↓ HLH L H H ↓ LHL H H H ↓ H H Toggle H H H X X Q 0 Q 0 † Output states are unpredictable if PRE and CLR go high simultaneously after both being low at the same time. logic diagram (positive logic) PRE CLK K Q Q CLR J absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) TA = 25°C –55°C to 125°C –40°C to 85°C UNIT MIN MAX MIN MAX MIN MAX VCC = 1.5 V 1.2 1.2 1.2 VIH High-level input voltage VCC = 3 V 2.1 2.1 2.1 V VCC = 5.5 V 3.85 3.85 3.85 VCC = 1.5 V 0.3 0.3 0.3 VIL Low-level input voltage VCC = 3 V 0.9 0.9 0.9 V VCC = 5.5 V 1.65 1.65 1.65 VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH High-level output current VCC = 4.5 V to 5.5 V –24 –24 –24 mA IOL Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA ∆t/∆v Input transition rise or fall rate VCC = 1.5 V to 3 V 50 50 50 ns/V∆t/∆v Input transition rise or fall rate VCC = 3.6 V to 5.5 V 20 20 20 ns/V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C –55°C to 125°C –40°C to 85°C UNITCC MIN MAX MIN MAX MIN MAX 1.5 V 1.4 1.4 1.4 IOH = –50 µA 3 V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 VOH VI = VIH or VIL IOH = –4 mA 3 V 2.58 2.4 2.48 V IOH = –24 mA 4.5 V 3.94 3.7 3.8 IOH = –50 mA† 5.5 V 3.85 IOH = –75 mA† 5.5 V 3.85 1.5 V 0.1 0.1 0.1 IOL = 50 µA 3 V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 VOL VI = VIH or VIL IOL = 12 mA 3 V 0.36 0.5 0.44 V IOL = 24 mA 4.5 V 0.36 0.5 0.44 IOL = 50 mA† 5.5 V 1.65 IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA C i 10 10 10 pF † Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.

CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003

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timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless otherwise noted) –55°C to 125°C –40°C to 85°C UNIT MIN MAX MIN MAX fclock Clock frequency 8 9 MHz t Pulse duration CLK high or low 63 55 nstw Pulse duration CLR or PRE low 56 49 ns tsu Setup time, before CLK↓ J or K 50 44 ns th Hold time, after CLK↓ J or K 0 0 ns trec Recovery time, before CLK↓ CLR ↑ or PRE↑ 31 27 ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) –55°C to 125°C –40°C to 85°C UNIT MIN MAX MIN MAX fclock Clock frequency 71 81 MHz t Pulse duration CLK high or low 7 6 nstw Pulse duration CLR or PRE low 6.3 5.5 ns tsu Setup time, before CLK↓ J or K 5.6 4.9 ns th Hold time, after CLK↓ J or K 0 0 ns trec Recovery time, before CLK↓ CLR ↑ or PRE↑ 3.5 3..1 ns timing requirements over recommended operating free-air temperature0 range, VCC = 5 V ± 0.5 V (unless otherwise noted) –55°C to 125°C –40°C to 85°C UNIT MIN MAX MIN MAX fclock Clock frequency 100 114 MHz t Pulse duration CLK high or low 5 4.4 nstw Pulse duration CLR or PRE low 4.5 3.9 ns tsu Setup time, before CLK↓ J or K 4 3.5 ns th Hold time, after CLK↓ J or K 0 0 ns trec Recovery time, before CLK↓ CLR ↑ or PRE↑ 2.5 2.2 ns

CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) –55°C to 125°C –40°C to 85°C UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX fmax 8 9 MHz tPLH CLK QQ 129 117 nstPLH CLR or PRE Q or Q 153 139 ns tPHL CLK Qo rQ 129 117 nstPHL CLR or PRE Q or Q 153 139 ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) –55°C to 125°C –40°C to 85°C UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX fmax 71 81 MHz tPLH CLK QQ 3.6 14.4 3.7 13.1 nstPLH CLR or PRE Q or Q 4.3 17.1 4.4 15.5 ns tPHL CLK Qo rQ 3.6 14.4 3.7 13.1 nstPHL CLR or PRE Q or Q 4.3 17.1 4.4 15.5 ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) –55°C to 125°C –40°C to 85°C UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX fmax 100 114 MHz tPLH CLK QQ 2.6 10.3 2.7 9.4 nstPLH CLR or PRE Q or Q 3.1 12.2 3.2 11.1 ns tPHL CLK Qo rQ 2.6 10.3 2.7 9.4 nstPHL CLR or PRE Q or Q 3.1 12.2 3.2 11.1 ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TYP UNIT C pd Power dissipation capacitance 56 pF

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NOTES: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms

www.ti.com 29-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CD54AC112F3A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54AC112F3A CD54AC112F3A.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54AC112F3A CD74AC112E Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74AC112E CD74AC112E.A Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74AC112E CD74AC112M Obsolete Production SOIC (D) | 16 - - Call TI Call TI -55 to 125 AC112M CD74AC112M96 Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 AC112M CD74AC112M96.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 AC112M (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 29-May-2025 OTHER QUALIFIED VERSIONS OF CD54AC112, CD74AC112 :

• Catalog : CD74AC112
• Military : CD54AC112 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC112M96 SOIC D 16 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CD74AC112E N PDIP 16 25 506 13.97 11230 4.32 CD74AC112E N PDIP 16 25 506 13.97 11230 4.32 CD74AC112E.A N PDIP 16 25 506 13.97 11230 4.32 CD74AC112E.A N PDIP 16 25 506 13.97 11230 4.32 Pack Materials-Page 3

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